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On Aug 10, 4:34 pm, ferorcue <le_m...@hotmail.com> wrote: > As you already know, cache transfer is 2 words (64-bit) betwen the > Cache Unit and the Processor Fetch Unit. However, this is a hardware > operation internal within PPC and not under control of the user except > to enable/disable the cache. Not entirely true. There are assembler instructions to allocate, fetch, and flush cache lines. This will generate bursts of 64-bit accesses. Kolja SulimmaArticle: 122926
Analogies often are misleading. The telephone system draws a big benefit from the fact that not everybody wants to talk to everybody else at the same time. (Remember Mr Erlang?) And: a crossbar switch is really a humungously large number of interconnects stuffed in a little box (and nowadays often time-division multiplexed.) The electricity-gas-water-sewer connections are non-individualized unidirectional busses. The analogy of urban planning may be more general and more applicable... Peter Alfke On Aug 10, 11:18 am, Frank Buss <f...@frank-buss.de> wrote: > Symon wrote: > > Are you sure about that Peter? I'm sure each house has one telephone wire to > > the exchange. All the complexity gets moved intot he exchange. So, wires are > > proportional to number of houses. Also, each house is on one road, has one > > electricity supply, one gas supply. > > If you want to connect two telephones, you'll need one wire. For three > telephone, you'll need a switch and 3 wires. For many more telephones, > you'll need a hierarchical system (in the beginning the telephone number > digits itself designated the different levels of the hierarchy), if you > don't want to connect each telephone with each other. This needs more wires > than endpoints, maybe a logarithmic number of additional wires per > endpoint, or maybe even more, if you want to handle many parallel > connections (I'm not a telephone expert), in addition to the wires from the > endpoints, but it doesn't increase proportional. > > -- > Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-systems.deArticle: 122927
Peter Alfke wrote: > Analogies often are misleading. > The telephone system draws a big benefit from the fact that not > everybody wants to talk to everybody else at the same time. (Remember > Mr Erlang?) And: a crossbar switch is really a humungously large > number of interconnects stuffed in a little box (and nowadays often > time-division multiplexed.) That's true, but it is still a hierarchical system, which needs more wires than endpoints, with switchers at the different levels, which can route to higher levels, if needed: http://en.wikipedia.org/wiki/Public_switched_telephone_network So it is not proportional to the number of endpoints, but the additional effort may be small with time multiplexed signals etc. I wonder if some of these technics could be used for FPGAs as well. There are some designs which doesn't need full speed interconnects and there are designs with loose coupled parts over the chip (but each part could have a high interconnection factor). So e.g. if one part of the chip needs to transfer x bits of data to another part, it could be serialized and even time multiplexed on a global internal bus system. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 122928
"Göran Bilski" <goran.bilski@xilinx.com> wrote in message news:f9h3ki$d1v1@cnn.xilinx.com... > Hi Fred, > > XPS keeps track of the .mhs settings for each core and stores a copy for > it in implementation/cache > > So what I usually do is to go in the implementation directory and deletes > the files associated with the core. > So when I work with microblaze I delete the microblaze_0_wrapper.ngc in > the implementation and in implementation/cache > In order to for a new system to be generated, I just touch the system.mhs > file since this is a file that is used in the makefile. > Now just microblaze will be regenerated when I generated a bitfile. > > On other option that I use with MicroBlaze is to change a parameter in the > .mhs file which don't change the actual implementation. > Ex. if I don't have HW debug enabled, I can freely change the number of > breakpoints in the .mhs. > XPS will see a difference of the parameter settings in the .mhs file > compared to the cached version and will regenerate the core > I have tried deleting the files and directory in the "implementation" directory and this doesn't update the design. I have since noticed there is a synthesis directory and perhaps I should have deleted the files there as well. Many thanks for your help.. From pcw@freeby.mesanet.com Fri Aug 10 12:41:37 2007 Path: newsdbm02.news.prodigy.net!newsdst02.news.prodigy.net!prodigy.com!newscon02.news.prodigy.net!prodigy.net!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.megapath.net!news.megapath.net.POSTED!not-for-mail NNTP-Posting-Date: Fri, 10 Aug 2007 14:41:37 -0500 From: "Peter C. Wallace" <pcw@freeby.mesanet.com> Subject: Webpack 9.1 and Samba Date: Fri, 10 Aug 2007 12:41:37 -0700 User-Agent: Pan/0.14.2 (This is not a psychotic episode. It's a cleansing moment of clarity.) Message-Id: <pan.2007.08.10.19.41.36.429824@freeby.mesanet.com> Newsgroups: comp.arch.fpga MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 24 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 66.80.14.42 X-Trace: sv3-8h0XjbLQ7b6IWb9xpXmHWHIjY2DtNm8J9w6CWzj3A+CjHGOsBCbb6M6jywAr7GqcF5ZRVnDVkn43OXH!YFuWm0CF1iBeVVVQyarKI1ZQXaDrZknkgvUMMNVoOA5WaLdi36BSZUdHzJjFzfASqtmgQZJCo92i!KXtedrozveCYR2dmkw== X-Complaints-To: abuse@megapath.net X-DMCA-Complaints-To: abuse@megapath.net X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.35 Bytes: 1791 Xref: prodigy.net comp.arch.fpga:134826 X-Received-Date: Fri, 10 Aug 2007 15:41:38 EDT (newsdbm02.news.prodigy.net) I just upgraded? my computer (was W2K) and ISE6.3 to Windows XP and Webpack 9.1 And now have problems with project/working filea mounted on a Samba server (3.0.10) This same setup worked fine with ISE6.3 and W2K I was hoping someone had the same troubles and could help me out here: symptoms: 1. When source files are saved, (either menu or control S) the navigator pops up a file dialog box asking for file type. 2. HTML report files are not found This doesn't happen if the files are local. I realize this may be a Samba/WXP problem, but at this point anyones experience here would be helpful Thanks Peter WallaceArticle: 122929
I am using VCS compiler to do the Xilinx FPGA timing simulation. I have 16 bit state machine in one of my verilog submodule. I am able to do the timing simulation but not sure the exact proecdure in locating the internal state machine and be able to see on the waveform viewer. AlbertArticle: 122930
"Duane Clark" <junkmail@junkmail.com> wrote in message news:yYOui.38$Oo.33@newssvr17.news.prodigy.net... > Fred wrote: >> Every time I make a minor change to one of my local pcores I have to do a >> "Clean Netlist" to ensure that the change is carried out. I find this >> very painful since it then rebuilds all the other IPs. >> >> Is there a way I can just compile the changed file? >> >> Is it more efficient to use a .vhdl file or a .ngd which I can generate >> with ISE. Would this save much time? > > The "OPTION CORE_STATE=DEVELOPMENT", mentioned elsewhere, will cause that > particular core to always be recompiled, regardless of whether it has > changed (at least last time I tried it). Probably not what you want. > > Are you still using the GUI? If you have abandoned that, then you can edit > the makefiles by hand to do this. EDK uses plain makefiles, so it is > puzzling why they don't already handle such a simple task. > > Anyway, in system_incl.make, immediately after > PROGRAMCLEAN_TARGETS = ppc405_1_default_programclean > I added entries like: > > MY_DDR_CLOCKS_IMPLN = implementation/my_ddr_clocks_wrapper.ngc > MY_DDR_CLOCKS_FILES = pcores/ddr_clocks_v1_00_a/hdl/vhdl/ddr_clocks.vhd \ > pcores/ddr_clocks_v1_00_a/data/ddr_clocks_v2_1_0.mpd \ > pcores/ddr_clocks_v1_00_a/data/ddr_clocks_v2_1_0.pao > > MY_REGS_IMPLN = implementation/my_regs_wrapper.ngc > MY_REGS_FILES = pcores/plb_regs_v1_00_a/hdl/vhdl/regs_core.vhd \ > pcores/plb_regs_v1_00_a/hdl/vhdl/plb_ipif_ssp1.vhd \ > pcores/plb_regs_v1_00_a/hdl/vhdl/plb_regs.vhd \ > pcores/plb_regs_v1_00_a/data/plb_regs_v2_1_0.mpd \ > pcores/plb_regs_v1_00_a/data/plb_regs_v2_1_0.pao > > MY_WRAPPER_NGC_FILES = $(MY_DDR_CLOCKS_IMPLN) \ > $(MY_BITS_IMPLN) > > MY_DEVELOPMENT_FILES = $(MY_DDR_CLOCKS_FILES) \ > $(MY_REGS_FILES) > > Then in system.make, I added immediately after: > ################################################################# > # HARDWARE IMPLEMENTATION FLOW > ################################################################# > > $(MY_DDR_CLOCKS_IMPLN): $(MY_DDR_CLOCKS_FILES) > rm -f implementation/my_ddr_clocks_wrapper.ngc > rm -f implementation/cache/my_ddr_clocks_wrapper.ngc > > $(MY_REGS_IMPLN): $(MY_REGS_FILES) > rm -f implementation/my_regs_wrapper.ngc > rm -f implementation/cache/my_regs_wrapper.ngc > > Then changed the lines (note the addition of MY_WRAPPER... and > MY_DEVELOP...: > > implementation/$(SYSTEM).bmm \ > $(CORE_WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \ > $(MY_DEVELOPMENT_FILES) > > @echo "****************************************************" > @echo "Creating system netlist for hardware specification.." > @echo "****************************************************" > platgen $(PLATGEN_OPTIONS) -st xst $(MHSFILE) > > $(POSTSYN_NETLIST): $(MY_WRAPPER_NGC_FILES) $(CORE_WRAPPER_NGC_FILES) > implementation/$(SYSTEM).bmm > @echo "Running synthesis..." > bash -c "cd synthesis; ./synthesis.sh; cd .." Many thanks for your reply. I've been aware of these make files but I've always been reluctant to make any changes in fear of the possible consequences. I find the EDK system very fickle and it's not the first time I've had to reload a saved copy! Perhaps this is the time I ought to start! Many thanks again for your trouble and will later digest the contents of your post. Greatly appreciated.Article: 122931
On Aug 10, 2:28 pm, "Fred" <f...@n0spam.com> wrote: > "G=F6ran Bilski" <goran.bil...@xilinx.com> wrote in message > > news:f9h3ki$d1v1@cnn.xilinx.com... > > > > > Hi Fred, > > > XPS keeps track of the .mhs settings for each core and stores a copy for > > it in implementation/cache > > > So what I usually do is to go in the implementation directory and delet= es > > the files associated with the core. > > So when I work with microblaze I delete the microblaze_0_wrapper.ngc in > > the implementation and in implementation/cache > > In order to for a new system to be generated, I just touch the system.m= hs > > file since this is a file that is used in the makefile. > > Now just microblaze will be regenerated when I generated a bitfile. > > > On other option that I use with MicroBlaze is to change a parameter in = the > > .mhs file which don't change the actual implementation. > > Ex. if I don't have HW debug enabled, I can freely change the number of > > breakpoints in the .mhs. > > XPS will see a difference of the parameter settings in the .mhs file > > compared to the cached version and will regenerate the core > > I have tried deleting the files and directory in the "implementation" > directory and this doesn't update the design. I have since noticed there= is > a synthesis directory and perhaps I should have deleted the files there as > well. > > Many thanks for your help.. You do not need to delete anything in the sysnthesis directory. If you want to force the rebuild of a pcore, delete its .ngc in both implementation and implementation/cache, and delete the sub directory in implementation that is named after the pcore. Get rid of those three things, and EDK will remake the core. Regards, John McCaskill www.fastertechnology.comArticle: 122932
On Aug 10, 12:41 pm, "Peter C. Wallace" <p...@freeby.mesanet.com> wrote: > I just upgraded? my computer (was W2K) and ISE6.3 to Windows XP and > Webpack 9.1 And now have problems with project/working filea mounted on a > Samba server (3.0.10) > > This same setup worked fine with ISE6.3 and W2K > > I was hoping someone had the same troubles and could help me out here: > > symptoms: > > 1. When source files are saved, (either menu or control S) the > navigator pops up a file dialog box asking for file type. > > 2. HTML report files are not found > > This doesn't happen if the files are local. > > I realize this may be a Samba/WXP problem, but at this point anyones > experience here would be helpful > > Thanks > > Peter Wallace Peter, It is a WXP/Samba problem. BTDT. About a year (or so) ago, there was a "security update" to 'doze file sharing, which broke the samba client side. Are you mounting the samba shares, or using a fully-qualified path. (mounted = s:\, fully-qual = \\samba-server\mystuff\) I've had better luck with the mounted shares. Also clear out the 'my network places' folder; stale handles in there can slow things down. And I've had the best results when attaching the drive from a cmd window rather than with the explodingxxxxx explorer GUI. c:\>net use s: \\samba-server\mystuff /persistent=yes (or something like that). Or you could try a different version of Samba. 3.0.25b is current, and 2.2.12 is archived. G.Article: 122933
<Albert Nguyen> wrote in message news:eea895b.-1@webx.sUN8CHnE... >I am using VCS compiler to do the Xilinx FPGA timing simulation. I have 16 >bit state machine in one of my verilog submodule. I am able to do the >timing simulation but not sure the exact proecdure in locating the internal >state machine and be able to see on the waveform viewer. > > Albert My theory is that recently people are taught to never solve their problems by asking questions on the newsgroups. So they make statements and watch for responses. There's a question here? (Besides this one, so far) _________ The VCS compiler is for timing only, right? Is your synthesizer XST? Do you have state machine optimization on or off? Have you looked at your XST technology view to see how the logic was implemented? Chances are you need to do some spelunking in your intermediate files or the XST post-synthesis viewer. Your original state machine may now be a very different representation that what you started with in your HDL. - John_HArticle: 122934
On Fri, 10 Aug 2007 15:33:22 -0700, ghelbig wrote: > On Aug 10, 12:41 pm, "Peter C. Wallace" <p...@freeby.mesanet.com> wrote: >> I just upgraded? my computer (was W2K) and ISE6.3 to Windows XP and >> Webpack 9.1 And now have problems with project/working filea mounted on >> a Samba server (3.0.10) >> >> This same setup worked fine with ISE6.3 and W2K >> >> I was hoping someone had the same troubles and could help me out here: >> >> symptoms: >> >> 1. When source files are saved, (either menu or control S) the >> navigator pops up a file dialog box asking for file type. >> >> 2. HTML report files are not found >> >> This doesn't happen if the files are local. >> >> I realize this may be a Samba/WXP problem, but at this point anyones >> experience here would be helpful >> >> Thanks >> >> Peter Wallace > > Peter, > > It is a WXP/Samba problem. BTDT. About a year (or so) ago, there was a > "security update" to 'doze file sharing, which broke the samba client > side. > > Are you mounting the samba shares, or using a fully-qualified path. > (mounted = s:\, fully-qual = \\samba-server\mystuff\) > > I've had better luck with the mounted shares. Also clear out the 'my > network places' folder; stale handles in there can slow things down. > > And I've had the best results when attaching the drive from a cmd window > rather than with the explodingxxxxx explorer GUI. c:\>net use s: > \\samba-server\mystuff /persistent=yes (or something like that). > > Or you could try a different version of Samba. 3.0.25b is current, and > 2.2.12 is archived. > > G. Thanks. I kind of suspected something like that. I'll try the command line attach, thats a good idea. If that doest work, I'll upgrade Samba. Makes me want to go back to W2K. If it werent for my layout software, I'd switch to Linux. I Peter WallaceArticle: 122935
On 8 11 , 12 31 , austin <aus...@xilinx.com> wrote: > http://www.xilinx.com/support/training/abstracts/embedded-systems.htm > > Austin I think you can learn to be familiar with the bus protocols: ATA/SATA, USB, Network Interface. You can choose one topic to do some experiments. For example, you can add a USB2.0 controller to your embedded system and you write a simple driver for it. I think you can learn much from that.Article: 122936
You can read my blog: http://www.fpgafromscratch.com SvenArticle: 122937
---------------------------- 1. The high end in a family shouldn't have more resources local to the CLB than the low end of the family. ==> This means that "how INTERCONNECT is organized" is the same, within same device family. I opend FPGA EDITOR. The CLB structure 'looks' same, for different device, within same family. 2. Everybody would agree that the need for interconnect grows faster than the number of things to be interconnected. ==> This means that AREA of interconnects grows super-linearly, as AREA of logic linearly grows. ---------------------------- If yes, my first impression is that : High-end device in a family provides "DECREASED ROUTABILITY" than low- end device in a family. For example, Virtex-II Pro-100 will provide "DECREASED ROUTABILITY" than Virtex-II Pro-20. Because: (1) Maximum fan-out that a single wire can drive is 'constant' for different devices. (2) As device size increases, there will be decreased amount of "long distance" wires, when wires are used up for neighbor logics.Article: 122938
hi i have a question. do i have to edit the ucf file by hand in edk 9.1 or is there a editor like in ise? i thought i could use the editor from ise but my ucf file that i created with edk wont load.. thanks urbanArticle: 122939
Bart van Deenen <bart@vandeenensupport-com.invalid> wrote:
> I've told ISE to Locate the bram at X0Y0, and from the FPGA Editor i can
> see that this works. It has implemented a BRAMB16BWE at site
> RAMB16_X0_Y0
it's not necessary to locate the BRAM on a fix position in the
design for a fast data2mem update cycle. All you have to do is to anaylze,
copy and adapt the design flow from the EDK for your own softcore or
your own BRAM usage. To do so you don't need EDK, all the tools like
data2mem are part of ISE.
newest picoblaze (KCPSM3) use it's own design tool like pb_bmm.exe
to get the BRAM-location information from the placed design, but this
pb_bmm tool is not useable in a general way. (maybe Ken Chapman
wasn't aware of the EDK design flow?)
I. for the HDL synthesis:
1. generate a myfile.bmm (ascii textfile) without any location
information as a template for ngdbuild. This .bmm file describe the
data/address width of the BRAM, the number of BRAMs in your
design, the component names, etc.. See the example at the end of
this message [1].
2. use the -bm switch from ngdbuild to "integrate" this bmm template
in the designflow. (first you have to synthesis your design using XST,
Synplify or whatever)
3. just run map/par/bitgen as usual. bitgen will notice the
"bmm-marker attribute" and output automagic an annotated BMM file
"myfile_bd.bmm" with the correct BRAM location information
(PLACED = X?Y?). The add on part "_bm" in the filename is hard
coded in the xilinx tools (ugs!).
II. for the software design:
1. run your compiler/assembler/linker (whatever) as usual.
The output should be a standard intel-hex file (or a binary file).
2. use common tools like s_record (s_cat) to convert the intel
hex or binary file from the compiler to the mem data format, which can be
read by data2mem. data2mem can read elf files too, but i would not
suggest to do so. The "xilinx mem" file format is just a verilog mem
(vmem) format, very simple, take a look in the srecord docu. the
conversion could be a command like:
$ srec_cat rom.hex -Intel -o rom.mem -vmem 8
(remark: for picoblaze you don't need srecord, because the
picoblaze-3 assembler outputs a *.mem file)
III. The final step:
The final step is to use data2mem + the *.mem file from the
compiler + the *_bd.bmm file from the synthesis path to "inject" the
BRAM content in the final bitfile on the correct positions. data2mem
will split the datafile according to the BMM description and will do
all the bit level work. This could be done like:
$ data2mem -bm myfile_bd.bmm -bt design.bit -bd rom.mem -o b final.bit
the final.bit can now be loaded direct to the FPGA or could
be input to promgen/impact to generate a prom file.
for simulation you can use data2mem to generate a vhdl-package
with "-o h final.vhd" - see the xilinx documentation. (which is in
details not complete and not always very accurate. Ths commandline
switch --help or -h outputs very often more information than the PDF
documentation for the xilinx toolchain - ISE9.1.3 )
If you change your software you have only to do a recompile
(II.) and repeat the final step (III.) which is very fast.
[1] example myfile.bmm template, for ngdbuild input:
ADDRESS_MAP mymap PPC405 0 // PPC405 is just a dummy
ADDRESS_SPACE rom COMBINED [0x00000000:0x000007FF]
ADDRESS_RANGE RAMB16
BUS_BLOCK
my_softcore/my_rom_component/BRAM_01 [3:0];
my_softcore/my_rom_component/BRAM_02 [7:4];
END_BUS_BLOCK;
END_ADDRESS_RANGE;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;
you have to modify the BRAM_layout and the BRAM component names
(path from the top of the HDL design) The address space must match the
correct BRAM length. The rest, like "mymap" is just a dummy. You can
choose any name.
bitgen will output a *_bm.bmm file with the location information
from the placing process. For example:
ADDRESS_MAP mymap PPC405 0
ADDRESS_SPACE rom COMBINED [0x00000000:0x000007FF]
ADDRESS_RANGE RAMB16
BUS_BLOCK
my_softcore/my_rom_component/BRAM_01 [3:0] PLACED = X0Y1;
my_softcore/my_rom_component/BRAM_02 [7:4] PLACED = X1Y2;
END_BUS_BLOCK;
END_ADDRESS_RANGE;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;
Remark: for picoblaze you will have only one BRAM in your
*.bmm file. With a databus width of 18 bits [17:0] and a address range
from [0x00000000:0x000003FF]
hope this help's a little bit,
WD
--
Article: 122940What do you want to achieve with these theoretical considerations? As I said, routability is not the problem anymore .. And why do you use 5-year old examples (Virtex-2Pro?) I prefer to address real problems using today's devices... Peter Alfke > > If yes, my first impression is that : > High-end device in a family provides "DECREASED ROUTABILITY" than low- > end device in a family. > > For example, Virtex-II Pro-100 will provide "DECREASED ROUTABILITY" > than Virtex-II Pro-20. > > Because: > (1) Maximum fan-out that a single wire can drive is 'constant' for > different devices. > (2) As device size increases, there will be decreased amount of "long > distance" wires, when wires are used up for neighbor logics.Article: 122941
On Aug 10, 2:37 am, pgw <"SwietyMikolaj["@]poczta.onet.pl> wrote: > Hi > > I want to use in my project (with Spartan3 or Cyclone2) a DDR/DDR2 DIMM > module. I have chosen DDR because is avaiable and cheaper than SDR. > I have no experience with memory controllers and not to big with FPGA, > that's why I don't know which design solution to choose. > I don't need fast data rate (least possible is enough to me) > > I have considered MegaCore function from Altera or solution provide by > Xilinx > > After I read documentation to DDR/DDR2 interface core provide by Xilinx I > have impression that they do it only to prove that it's possible to > interface DDR with their fpgas, but they give no guarantee it will by > works. Am I wrong? > And MIG don't support DIMMs for Spartan3. > > When I compiled a DDR2 controler from MegaCore it take 3000LE. It's quite a > lot. > > I consider too make my own DDR/DDR2 controller. I have read DDR2 > specification and it seems complicated. But maybe if I make it for > particular DDR2 module it will be more easier and take less LE or LUTs. > > Have anyone experience with solution that I mentioned? > Or maybe someone may suggest me another solution? > Any help is appreciated. > > PGW You might want to check out Lattice's XP2 family. Has built-in flash that stores the FPGA configuration which eases design and gives a single- chip, instant-on approach. Has advanced registering in IO cell to take care of all of the DDR- >SDR data path stuff as well as dedicated logic for DQS delay. Lowers LUT count and eases timing - run up to 400Mbps. With 64 bit DRAM interface uses about 2K LUT's (with default values). IPExpress tool provides similar function to Megacore.Article: 122942
John, I have been taking hunt and pack approach in locating the internal signals of the fpga fabric - for example looking at the intermiediate files etc. I felt that there may be a better way to do this. This is why I wanted to pose this question on this forum. It just seems that if there is no direct way then that is a problem that should be fixed. AlbertArticle: 122943
dimtsios@ix.netcom.com wrote: > > You might want to check out Lattice's XP2 family. Has built-in flash > that > stores the FPGA configuration which eases design and gives a single- > chip, > instant-on approach. > > Has advanced registering in IO cell to take care of all of the DDR- > SDR data > path stuff as well as dedicated logic for DQS delay. Lowers LUT count > and eases > timing - run up to 400Mbps. With 64 bit DRAM interface uses about 2K > LUT's > (with default values). IPExpress tool provides similar function to > Megacore. I only forgot to mention that im a student and this is an academic project. :) Also I am looking only free solution or these that I can test before purchase like Megacore. PGWArticle: 122944
Hi Albert - [1] You might want to try bringing the state machine bits to either a port on the module, or even to external I/O signals to facilitate monitoring. Buffer with either one level, or two level of FFs so as not to exacerbate route effects on timing.. [2] I complete maybe 10 FPGA designs per year, and have not performed a timing simulation of gate level netlist in many years. RTL simulations find logic flaws ...... static timing tool ensures timing integrity of design. Good luck. -- Regards, John Retta Owner and Designer Retta Technical Consulting Inc. email : jretta@rtc-inc.com web : www.rtc-inc.com <Albert Nguyen> wrote in message news:eea895b.-1@webx.sUN8CHnE... >I am using VCS compiler to do the Xilinx FPGA timing simulation. I have 16 >bit state machine in one of my verilog submodule. I am able to do the >timing simulation but not sure the exact proecdure in locating the internal >state machine and be able to see on the waveform viewer. > > AlbertArticle: 122945
John Retta, I am relatively new to the FPG design. I normally use the PERIOD constraint on my synchronous designs. But I have this design where I am 5 different clock domains. Some of the clocks are derived from the fpga pll output and to the bufg. The software seems to change names of these clocks so if I specify the PERIOD contraint in the ucf file then it does not get recognized correctly - sometimes it sees no load to the clock with PERIOD constraint and sometimes the software does not see the clock. I am not sure what will be the best wat to specify the PERIOD constraint to intenal clocks of the FPGA fabric. I wish that the Xilinx sofwtare gets smarter here and asks the end user about specifying the PERIOD constraint to "hard to reach" clocks. Albert.Article: 122946
Not to worry .... we were all new to this at some point. So to find out the names of clocks, you have to options. First is to check the .par report file. That should show you the clk domains with named clock net. Other option is to open the constraints editor and select the .ngd file - I think that is the correct one. This tool will then display the list of named clks that you can put a constraint on. For me, I use the constraint editor to find the names of clks ( when tool has not named them in way I expect), or if I want to figure out the syntax for constraints I do not use frequently. "Feature" of constraint editor, is that it mucks with original .ucf file ... and may make this file difficult to read. Like my own formatting a little better. Also, with regards to renaming ... if you keep your clk name same through various levels of hierarcy, clk_100mhz for instance, then the problem of which point in netlist it chose to pick out net name occurs less often. -- Regards, John Retta Owner and Designer Retta Technical Consulting Inc. email : jretta@rtc-inc.com web : www.rtc-inc.com <Albert Nguyen> wrote in message news:eea895b.3@webx.sUN8CHnE... > John Retta, > > I am relatively new to the FPG design. I normally use the PERIOD > constraint on my synchronous designs. But I have this design where I am 5 > different clock domains. Some of the clocks are derived from the fpga pll > output and to the bufg. The software seems to change names of these clocks > so if I specify the PERIOD contraint in the ucf file then it does not get > recognized correctly - sometimes it sees no load to the clock with PERIOD > constraint and sometimes the software does not see the clock. > > I am not sure what will be the best wat to specify the PERIOD constraint > to intenal clocks of the FPGA fabric. I wish that the Xilinx sofwtare gets > smarter here and asks the end user about specifying the PERIOD constraint > to "hard to reach" clocks. > > Albert.Article: 122947
Old examples? I wonder what the breakdown is on the number of FPGAs you ship, Virtex-II Pro vs Virtex-4 vs Virtex-5. Since you aren't shipping all the Virtex-5s yet, an I still can't find small unit quatities of Virtex-4s, I bet the Virtex-II Pro is still very relevant. ---Matthew Hicks > What do you want to achieve with these theoretical considerations? > As I said, routability is not the problem anymore .. > And why do you use 5-year old examples (Virtex-2Pro?) > I prefer to address real problems using today's devices... > Peter Alfke >> If yes, my first impression is that : >> High-end device in a family provides "DECREASED ROUTABILITY" than >> low- >> end device in a family. >> For example, Virtex-II Pro-100 will provide "DECREASED ROUTABILITY" >> than Virtex-II Pro-20. >> >> Because: >> (1) Maximum fan-out that a single wire can drive is 'constant' for >> different devices. >> (2) As device size increases, there will be decreased amount of "long >> distance" wires, when wires are used up for neighbor logics.Article: 122948
Things obviously always look different from the inside than from the outside. As far as I know, Xilinx has been shipping every member of the three announced Virtex-5 sub-families for awhile. Most of them with the ES designation, but many also as "production". Virtex-4 is shipping in larger volume, since it is used in our customers' production equipment. Virtex-2Pro is doing well, but it is 2 generations behind... AFAIK you can order Virtex-5 parts from the two major distributors, Avnet and NewHorizon. That was a contentious issue a few months ago, that seems to be resolved now. I still have some scars from that internal battle. I am sorry that I have driven this obscure posting so far off-topic. Peter Alfke On Aug 11, 5:44 pm, Matthew Hicks <mdhic...@uiuc.edu> wrote: > Old examples? I wonder what the breakdown is on the number of FPGAs you > ship, Virtex-II Pro vs Virtex-4 vs Virtex-5. Since you aren't shipping all > the Virtex-5s yet, an I still can't find small unit quatities of Virtex-4s, > I bet the Virtex-II Pro is still very relevant. > > ---Matthew Hicks > > > What do you want to achieve with these theoretical considerations? > > As I said, routability is not the problem anymore .. > > And why do you use 5-year old examples (Virtex-2Pro?) > > I prefer to address real problems using today's devices... > > Peter Alfke > >> If yes, my first impression is that : > >> High-end device in a family provides "DECREASED ROUTABILITY" than > >> low- > >> end device in a family. > >> For example, Virtex-II Pro-100 will provide "DECREASED ROUTABILITY" > >> than Virtex-II Pro-20. > > >> Because: > >> (1) Maximum fan-out that a single wire can drive is 'constant' for > >> different devices. > >> (2) As device size increases, there will be decreased amount of "long > >> distance" wires, when wires are used up for neighbor logics.Article: 122949
Thanks John. I will follow your advice. I have been afraid of using the constraint editor as it overwrites the ucf file but I can keep a copy of good ucf file. I am using Virtex5 deivce and it is way under utilized as far as the LUTs are concerned. I am hoping that I can run the fabric at 200MHz. Albert
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