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Messages from 121250

Article: 121250
Subject: Re: d-link router?
From: jetmarc@hotmail.com
Date: Fri, 29 Jun 2007 01:37:04 -0700
Links: << >>  << T >>  << A >>
> Does anyone know which cpu do they use in the d-link router/adsl modem
> dsl-g624t ?

It's a MIPS 4KEc V4.8 cpu core in an TI AR7 chip.

> Is there schematics and source free to view some where?

The D-Link source is not free to view, AFAIK.  But you can view the
free source of an alternative firmware for that modem on www.openwrt.org

Regards,
Marc


Article: 121251
Subject: Re: Analogue like signal interaction within cpld possible ????
From: "comp.arch.fpga" <ksulimma@googlemail.com>
Date: Fri, 29 Jun 2007 08:46:45 -0000
Links: << >>  << T >>  << A >>
On Jun 28, 1:00 pm, Jim Granville <no.s...@designtools.maps.co.nz>
wrote:

> So, do not use a CPLD as the Phase Comparitor, but use an LVC Exor gate,
> preferable with Schmitt. eg LVC1G97, with analog Supply decoupling.

Actually, this might not be sufficient. The clock-to-out delay of the
flip-flops in the CPLD and
of the output drivers of the CPLD depend on the supply voltage. The
supply voltage inside
the chip depends on the switching history of all nearby signals in the
chip.
(E.G. the carry chain delay of a Spartan-2 doubles during an interval
of a few hundred picoseconds
after the flip-flops connected to it were switching.)

Similar is true for the input thresholds of the flip flop clock
inputs. At the precisions you are talking about
you will see a lot of crosstalk from different sources.

It surely will help to use discrete fast flip-flops instead of a CPLD
(We use PECL devices from OnSemi).
At least you don't see package ground bounce across packages.

Another option is to measure the positions of the edges individually
and compute the phase difference from that. Many Time To Digital
Converters have two or more channels. See our website www.cronologic.de
for an example.

Kolja Sulimma



Article: 121252
Subject: Re: Execute from SPI flash
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Fri, 29 Jun 2007 10:10:29 +0100
Links: << >>  << T >>  << A >>
Jim Granville <no.spam@designtools.maps.co.nz> writes:

> Jim Granville wrote:
>
>> Execute from SPI flash has always appealed as one way to
>> reduce the PCB cost of the Code memory needed by Soft CPUs.
>> Winbond have had Double rate SPI devices at 150MBd, and
>> I see they plan to release Quad-SPI devices, that target
>> Execute of code direct from the Flash.
>
> More info: Advance data is here
> http://www.winbond.com.tw/NR/rdonlyres/4C63AD62-967C-4B72-AF85-1F5984E8B199/0/W25Q80.pdf
>
> Still an 8 pin package (or SO16 where die is too large )
>
> Best speed is from Fast Read Quad I/O opcode
>
> Looks like the first byte is 1-bit SPI (8Ck), then the 32 bit address
> is loaded 4 bits wide (8Ck), then 4 wait clocks, and then bytes stream
> out
> two Ck per byte, so the latency to first byte is 8+8+4+2 = 20-22clks,
> and the Speed-Equivalent-Skip is 10 bytes - ie for short forward jumps,
> of up to 10 bytes, you are better to simply skip, than re-address.
> Clock is 80MHz, gives 320MBd, or 40 MBytes/s memory bandwith.
> Enough for some serious uC programming, and you can split into 2 SPI
> devices, and double that again, or perhaps x3, for 18-24 bit opcode cores ?
>

At what point do you call it a parallel flash (admittedly with an
address counter built in :-)

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

Article: 121253
Subject: Re: USB JTAG Programming
From: "Amontec, Larry" <laurent.gauch@ANTI-SPAMamontec.com>
Date: Fri, 29 Jun 2007 11:11:13 +0200
Links: << >>  << T >>  << A >>
neilla@pipstechnology.co.uk wrote:

> On 29 Jun, 07:20, "Amontec, Larry" <laurent.ga...@ANTI-
> SPAMamontec.com> wrote:
> 
>>nei...@pipstechnology.co.uk wrote:
>>
>>>I'm looking at adding an embedded USB JTAG programmer onto our latest
>>>board, and am just looking for a bit of advice.  The board has on it
>>>an Spartan 3, and an XCF08P Platform Flash prom, the main processor on
>>>the board is a Compulab computer on module.  We need to be able to
>>>program the flash in system using the Compulab CoM.  We currently do
>>>this using the LPC interface on the CoM, and an extra CPLD, using the
>>>xilinx JDrive software.  Currently doing an erase, program, and verify
>>>of the XCF08P takes ~60 seconds.  I was thinking it might be a nicer
>>>solution to use a USB device like the FTDI 2232 to give us JTAG
>>>access, but would like a bit of advice as to how easy it is to use
>>>these things, and is the programming time likely to be any quicker.
>>
>>>Neill.
>>
>>Amontec has designed a generic SVF Player for the JTAGkey.
>>We can run any SVF for programming any FPGA/CPLD/FLASH from Altera
>>Lattice Xilinx Cypress ...
>>
>>Amontec JTAGkey is based on FT2232.
>>
>>If you send me your XCF08P.svf file, I can play it ( vide) and found
>>how much time it takes for doing the JOB. (please zip before sending)
>>
>>email to laurent.gauch@REMOVE_THIS_ANTI_SPAMamontec.com
>>
>>Regards,
>>Laurent Gauchwww.amontec.com
> 
> 
> Larry,
> 
> The main problem with using an SVF file for programming the XCF08P is
> the erase time. The file from the xilinx tools has the erase time set
> to 140 seconds, this is actually the time needed for the larger
> platform flash, with the XCF08P the this can be reduced to 50
> seconds.  This is the maximum time needed to gurantee it is erased
> correctly.  The problem with SVF is that it just sits and waits for
> this time, at least with the jdrive software after an erase it sits
> polling a bit in a register to see when the erase is really completed,
> which is normally much less than the 50 seconds.  This is also similar
> with the programming times.
> 
> Neill
> 

Yes, you're 100% right. Jdrive could be faster than SVF -> it is 
dedicated for PLD.
... SVF is much more generic.

We reach the same problem when Flashing ARM7 and need to wait on the 
debug mode !

Laurent
www.amontec.com

Article: 121254
Subject: Re: Execute from SPI flash
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Fri, 29 Jun 2007 21:42:42 +1200
Links: << >>  << T >>  << A >>
Martin Thompson wrote:
> Jim Granville <no.spam@designtools.maps.co.nz> writes:
> 
>>Looks like the first byte is 1-bit SPI (8Ck), then the 32 bit address
>>is loaded 4 bits wide (8Ck), then 4 wait clocks, and then bytes stream
>>out
>>two Ck per byte, so the latency to first byte is 8+8+4+2 = 20-22clks,
>>and the Speed-Equivalent-Skip is 10 bytes - ie for short forward jumps,
>>of up to 10 bytes, you are better to simply skip, than re-address.
>>Clock is 80MHz, gives 320MBd, or 40 MBytes/s memory bandwith.
>>Enough for some serious uC programming, and you can split into 2 SPI
>>devices, and double that again, or perhaps x3, for 18-24 bit opcode cores ?
>>
> 
> At what point do you call it a parallel flash (admittedly with an
> address counter built in :-)

You are right :) - they are inching [nibbling ? ;) ] their
way back to the memory segment that
has mostly died off (except in some game cartridges ?) of
Address latched and Clocked Code Flash/Rom Memory.

Still, getting a Nibble-wide memory in a 8 pin package is
quite nice, and using 2-3-4 of these is probably quite practical.

 From an energy and EMC angle, it makes much more sense to have
a loadable address counter, so I hope these contine to expand.
Next, we might see Byte-wide ones in SO16 ?

-jg


Article: 121255
Subject: Re: vista 64 bits
From: "RedskullDC" <red@oz.org>
Date: Fri, 29 Jun 2007 20:16:43 +1000
Links: << >>  << T >>  << A >>
Hi Christophe,

Been using ISE9.1 with Vista Ultimate x64 for the last few months.
Compiles my projects without any problem.

Only problem I've had is the non-signed parallel/usb drivers from Xilinx 
won't install
with the final release versions of Vista X64, since you can no longer 
disable
the driver-signing checks as you could with the pre-release versions of 
Vista(AFAIK).

Programming files are saved to a network shared directory, and another 
machine
running XPhome is used to actually program the hardware.
Cumbersome, but the machine running vista is considerably higher spec, and 
compiles
projects in a third of the time as the old XP box.

Come on Xilinx. **PLEASE** release some signed hardware drivers!!
Ditto Altera.......

Red

"christophe ALEXANDRE" <christophe.alexandre@gmail.com> wrote in message 
news:1183055040.264539.195390@w5g2000hsg.googlegroups.com...
> hi Xilinx,
>
> i had a look at ISE 9.2 today.
> It's supporting Vista 32 bits.
>
> When should we have a Vista 64 bits support ?
>
> regards
> 


Article: 121256
Subject: Re: Analogue like signal interaction within cpld possible ????
From: "Ulrich Bangert" <df6jb@ulrich-bangert.de>
Date: Fri, 29 Jun 2007 13:44:50 +0200
Links: << >>  << T >>  << A >>
Kolja,

I needed only a vague look to your website to see that you surely know what
you are talking about. Yes, clearly an TDC can be used for that purpose. My
efforts to do it the linear way have the background to make an very cheap
technology available that would enable say radio amateurs to characterize
precise oscillators. In terms of price the modern cplds come very handy.
I will think about your suggestions.

Best regards
Ulrich Bangert

Best regards
Ulrich Bangert
"comp.arch.fpga" <ksulimma@googlemail.com> schrieb im Newsbeitrag
news:1183106805.864519.234350@q75g2000hsh.googlegroups.com...
> On Jun 28, 1:00 pm, Jim Granville <no.s...@designtools.maps.co.nz>
> wrote:
>
> > So, do not use a CPLD as the Phase Comparitor, but use an LVC Exor gate,
> > preferable with Schmitt. eg LVC1G97, with analog Supply decoupling.
>
> Actually, this might not be sufficient. The clock-to-out delay of the
> flip-flops in the CPLD and
> of the output drivers of the CPLD depend on the supply voltage. The
> supply voltage inside
> the chip depends on the switching history of all nearby signals in the
> chip.
> (E.G. the carry chain delay of a Spartan-2 doubles during an interval
> of a few hundred picoseconds
> after the flip-flops connected to it were switching.)
>
> Similar is true for the input thresholds of the flip flop clock
> inputs. At the precisions you are talking about
> you will see a lot of crosstalk from different sources.
>
> It surely will help to use discrete fast flip-flops instead of a CPLD
> (We use PECL devices from OnSemi).
> At least you don't see package ground bounce across packages.
>
> Another option is to measure the positions of the edges individually
> and compute the phase difference from that. Many Time To Digital
> Converters have two or more channels. See our website www.cronologic.de
> for an example.
>
> Kolja Sulimma
>
>



Article: 121257
Subject: Re: Coding style of verilog for FPGA synthesis
From: Allen <lphplab@gmail.com>
Date: Fri, 29 Jun 2007 04:50:55 -0700
Links: << >>  << T >>  << A >>
Hi guys,

Thanks for your replies first.
I forget to say that function of this design is correct by using
Design Vision and the testbench for that and this are the same.

I check description of testbench.
Timescale directive was includeded on the top of testbench and the
custom design ( `timescale 1ns/10ps).

The clock speed is 5 MHz ( #100 clock = ~ clock) and the design still
doesn't work properly.

The input singals are as what I described in the testbench.

I still have no idea about how to debug or modify the design?

Thanks again.

Regards,

Allen



Article: 121258
Subject: Re: modelsim search path
From: "cpope" <cepope@nc.rr.com>
Date: Fri, 29 Jun 2007 07:54:05 -0400
Links: << >>  << T >>  << A >>

"HT-Lab" <hans64@ht-lab.com> wrote in message
news:%E2hi.8371$_14.3447@newsfe2-gui.ntli.net...
>
> "cpope" <cepope@nc.rr.com> wrote in message
> news:46846fca$0$30640$4c368faf@roadrunner.com...
> > Does any one know how to set the search path so my modelsim pe 6.0c will
> > find the .mif file associated with my coregen blocks? I get the
following
> > error:
> >
> > # Loading C:/Xilinx/vhdl/mti_pe/XilinxCoreLib.cordic_v3_0(behavioral)
> > # ** Error: (vsim-7) Failed to open VHDL file
> > "dds_SINCOS_TABLE_TRIG_ROM.mif" in rb mode.
> > # No such file or directory. (errno = ENOENT)
> > #    Time: 0 ns  Iteration: 0  Instance:
/ddr_9479_tb/uut/bfo_g1/nco/bu273
> > # ** Fatal: (vsim-7) Failed to open VHDL file
> > "dds_SINCOS_TABLE_TRIG_ROM.mif" in rb mode.
> > # No such file or directory. (errno = ENOENT)
> > #    Time: 0 ns  Iteration: 0  Process:
> > /ddr_9479_tb/uut/bfo_g1/nco/bu273/dp_primitive File:
> > C:/Xilinx/vhdl/mti_pe/XilinxCoreLib/XilinxCoreLib_source.vhd
> > # Fatal error at
> > C:/Xilinx/vhdl/mti_pe/XilinxCoreLib/XilinxCoreLib_source.vhd line 80173
> >
> > If I copy the .mif to the root directory it works okay, but I want to
keep
> > my top module and test bench one directory up from the subblocks.
> >
>
> The mif file might be specified as a generic in your vhd wrapper file,
> change the path, recompile and bob's your uncle :-)
>
> Hans
> www.ht-lab.com
>
>
>
>
> > Thanks,
> > Clark
> >
> >
>
>

You mean change in dds.vhd, for example, (see below)? Wouldn't that mean I
have to edit everytime I regenerate that core?

   BU273 : blkmemdp_v6_0
      GENERIC MAP (
         c_reg_inputsb => 0,
         c_reg_inputsa => 0,
         c_has_ndb => 0,
         c_has_nda => 0,
         c_ytop_addr => "1024",
         c_has_rfdb => 0,
         c_has_rfda => 0,
         c_ywea_is_high => 1,
         c_yena_is_high => 1,
         c_yhierarchy => "hierarchy1",
         c_yclka_is_rising => 1,
         c_ysinita_is_high => 1,
         c_ybottom_addr => "0",
         c_width_b => 10,
         c_width_a => 10,
         c_sinita_value => "0000",
         c_sinitb_value => "0000",
         c_limit_data_pitch => 18,
         c_write_modeb => 0,
         c_write_modea => 0,
         c_has_rdyb => 0,
         c_yuse_single_primitive => 0,
         c_has_rdya => 0,
         c_addra_width => 10,
         c_addrb_width => 10,
         c_has_limit_data_pitch => 0,
         c_default_data => "0000",
         c_pipe_stages_b => 0,
         c_yweb_is_high => 1,
         c_yenb_is_high => 1,
         c_pipe_stages_a => 0,
         c_yclkb_is_rising => 1,
         c_yydisable_warnings => 1,
         c_enable_rlocs => 0,
         c_ysinitb_is_high => 1,
         c_has_web => 0,
         c_has_default_data => 0,
         c_has_wea => 0,
         c_has_sinitb => 0,
         c_has_sinita => 0,
         c_has_dinb => 0,
         c_has_dina => 0,
         c_ymake_bmm => 0,
         c_has_enb => 1,
         c_has_ena => 1,
         c_mem_init_file => "dds_SINCOS_TABLE_TRIG_ROM.mif",
         c_depth_b => 1024,
         c_depth_a => 1024,
         c_has_doutb => 1,
         c_has_douta => 1,
         c_yprimitive_type => "4kx4"
      )
      PORT MAP (
         addra => BU273_addra,
         addrb => BU273_addrb,
         clka => BU273_clka,
         clkb => BU273_clkb,
         dina => BU273_dina,
         dinb => BU273_dinb,
         douta => BU273_douta,
         doutb => BU273_doutb,
         ena => BU273_ena,
         enb => BU273_enb,
         nda => BU273_nda,
         ndb => BU273_ndb,
         rfda => BU273_rfda,
         rfdb => BU273_rfdb,
         rdya => BU273_rdya,
         rdyb => BU273_rdyb,
         sinita => BU273_sinita,
         sinitb => BU273_sinitb,
         wea => BU273_wea,
         web => BU273_web
      );



Article: 121259
Subject: Re: Xilinx FPGA to interface to special I/O
From: "Albert Nguyen" <>
Date: Fri, 29 Jun 2007 05:53:49 -0700
Links: << >>  << T >>  << A >>
Ben,

I did a little reading on the bipolar transistors and made some calculations to figure out the base resistor value. But my caluclation does not match the base resistor value of 1K.

Icollecor = (1.2-(-1.3))/500

= 2.5/500

= 5 mA

IBase = 0.7/28.6 = 0.0244 Amps

If the FPGA is driving 3.3V signal then

Rbase = (3.3 - 0.7)/0.0244

= 106 Ohm.

You mentioned about using 1K Ohm base resistor but as per my calucaltion it needs to be about 106 Ohms if the FPGA is driving 0 to 3.3V signals.

Thus Rcollector = 500 Ohms and R base = 106 Ohms.

Does this make sense?

Thanks.

Albert

Article: 121260
Subject: Re: modelsim search path
From: "HT-Lab" <hans64@ht-lab.com>
Date: Fri, 29 Jun 2007 13:06:44 GMT
Links: << >>  << T >>  << A >>

"cpope" <cepope@nc.rr.com> wrote in message 
news:4684f390$0$8933$4c368faf@roadrunner.com...
>
> "HT-Lab" <hans64@ht-lab.com> wrote in message
> news:%E2hi.8371$_14.3447@newsfe2-gui.ntli.net...
>>
>> "cpope" <cepope@nc.rr.com> wrote in message
>> news:46846fca$0$30640$4c368faf@roadrunner.com...
>> > Does any one know how to set the search path so my modelsim pe 6.0c 
>> > will
>> > find the .mif file associated with my coregen blocks? I get the
> following
>> > error:
>> >
>> > # Loading C:/Xilinx/vhdl/mti_pe/XilinxCoreLib.cordic_v3_0(behavioral)
snip
>> > # Fatal error at
>> > C:/Xilinx/vhdl/mti_pe/XilinxCoreLib/XilinxCoreLib_source.vhd line 80173
>> >
>> > If I copy the .mif to the root directory it works okay, but I want to
> keep
>> > my top module and test bench one directory up from the subblocks.
>> >
>>
>> The mif file might be specified as a generic in your vhd wrapper file,
>> change the path, recompile and bob's your uncle :-)
>>
>> Hans
>> www.ht-lab.com
>>
>>
>> > Thanks,
>> > Clark
>> >
>
> You mean change in dds.vhd, for example, (see below)? Wouldn't that mean I
> have to edit everytime I regenerate that core?

Yes, but how often do you re-generate your core(s)?

c_mem_init_file => "<my_path>/dds_SINCOS_TABLE_TRIG_ROM.mif",

Regards,
Hans.
www.ht-lab.com




Article: 121261
Subject: Re: Trace capturing
From: "Ravishankar S" <ravishankar.s@in.bosch.com>
Date: Fri, 29 Jun 2007 20:07:08 +0530
Links: << >>  << T >>  << A >>
Hi Jonathan,

Nexus is a OnChip mechanism which works in conjunction with the debug port
(JTAG). So the debug port controls the  device and sets up triggers , the
AUX port send out the trace information and takes in trace data.
More at the Nexus site: can find through google.
One  similarity to logic analzysis is the capturing happens synchronous to
the clock: in case of  LA its memory clock and Nexus its a special nexus
output clock. The data though in case of Nexus is variable length and is
compressed.


Kind Regards,
Ravishankar




"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message
news:e8n48315ihhbona54ldajv7b3fng5afrek@4ax.com...
> On Wed, 27 Jun 2007 17:34:43 +0530,
> "Ravishankar S" <ravishankar.s@in.bosch.com> wrote:
>
> Ravishankar,
>
> >But this is a processor with no external bus.
>
> Ah.  Bad assumption by me.  I just (foolishly) assumed that
> Nexus was yet another regular CPU.  Any links I can follow
> to take a look?
>
> > (Also its for experimentation).
>
> OK, fair enough.
>
> >So logic analyser as far as I know wont help here. The idea is to build
an
> >emulator which can caputure the Nexus public messages and also write into
> >internal memories of the controller for calibration of variables.
>
> Logic analysers can be persuaded to decode all manner of
> protocol stuff, but I agree that this sounds a bit too specialised.
>
> Sorry to have misunderstood.
> -- 
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.bromley@MYCOMPANY.com
> http://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.



Article: 121262
Subject: Re: modelsim search path
From: pontus.stenstrom@gmail.com
Date: Fri, 29 Jun 2007 07:49:10 -0700
Links: << >>  << T >>  << A >>

> Yes, but how often do you re-generate your core(s)?

Every time you "build" from scratch (you can run coregen -b
dds_SINCOS_TABLE_TRIG_ROM.xco and only check in the .xco and .coe
files),
or if you change ISE version, or if you change core parameters.
And I agree its painful to edit auto generated files.
I use "sed" to cut and paste in the generated file.


> c_mem_init_file => "<my_path>/dds_SINCOS_TABLE_TRIG_ROM.mif",

Modelsim seems to resolve environment variables in this case, so you
can write:
(the environment variable is resolved at elaboration, not
compilation!)

c_mem_init_file => "$MY_SUBMODULE_PATH/coregen/
dds_SINCOS_TABLE_TRIG_ROM.mif"

I think the .mif file is only for simulation, but I might be wrong!?
Do you know if the .mif file is ever used by ngdbuild?

Regards /Pontus


Article: 121263
Subject: Re: d-link router?
From: mikeandmax@aol.com
Date: Fri, 29 Jun 2007 07:52:57 -0700
Links: << >>  << T >>  << A >>
On Jun 28, 8:44 pm, Mark McDougall <m...@vl.com.au> wrote:
> John_H wrote:
> > Hey - while I have your ear, do you have any idea why the cup holders for
> > the BMW Z-4 are so shallow?
>
> Because the people who drive them are? ;)
>
> Regards,
>
> --
> Mark McDougall, Engineer
> Virtual Logic Pty Ltd, <http://www.vl.com.au>
> 21-25 King St, Rockdale, 2216
> Ph: +612-9599-3255 Fax: +612-9599-3266

I was gonna go with the car is so fast you don't have time to drink a
large coffee, but I actually enjoyed yours more :)
shouldn't this be in comp.arch.starbucs?
Miket


Article: 121264
Subject: Re: modelsim search path
From: "cpope" <cepope@nc.rr.com>
Date: Fri, 29 Jun 2007 11:00:50 -0400
Links: << >>  << T >>  << A >>

<pontus.stenstrom@gmail.com> wrote in message
news:1183128550.700825.295540@o61g2000hsh.googlegroups.com...
>
> > Yes, but how often do you re-generate your core(s)?
>
> Every time you "build" from scratch (you can run coregen -b
> dds_SINCOS_TABLE_TRIG_ROM.xco and only check in the .xco and .coe
> files),
> or if you change ISE version, or if you change core parameters.
> And I agree its painful to edit auto generated files.
> I use "sed" to cut and paste in the generated file.
>
>
> > c_mem_init_file => "<my_path>/dds_SINCOS_TABLE_TRIG_ROM.mif",
>
> Modelsim seems to resolve environment variables in this case, so you
> can write:
> (the environment variable is resolved at elaboration, not
> compilation!)
>
> c_mem_init_file => "$MY_SUBMODULE_PATH/coregen/
> dds_SINCOS_TABLE_TRIG_ROM.mif"
>
> I think the .mif file is only for simulation, but I might be wrong!?
> Do you know if the .mif file is ever used by ngdbuild?
>
> Regards /Pontus
>

Probably easier for me to copy the .mif files up to the directory where I
run the simulation. Would be nice if I could just add the subdirectory to
the search path somehow.

I think you are right: .mif is only for simulation/coregen.

Thanks,
Clark



Article: 121265
Subject: Re: Xilinx FPGA to interface to special I/O
From: "John_H" <newsgroup@johnhandwork.com>
Date: Fri, 29 Jun 2007 08:40:18 -0700
Links: << >>  << T >>  << A >>
<Albert Nguyen> wrote in message news:eea7b1c.13@webx.sUN8CHnE...
> Ben,
>
> I did a little reading on the bipolar transistors and made some 
> calculations to figure out the base resistor value. But my caluclation 
> does not match the base resistor value of 1K.
>
> Icollecor = (1.2-(-1.3))/500
>
> = 2.5/500
>
> = 5 mA
>
> IBase = 0.7/28.6 = 0.0244 Amps
>
> If the FPGA is driving 3.3V signal then
>
> Rbase = (3.3 - 0.7)/0.0244
>
> = 106 Ohm.
>
> You mentioned about using 1K Ohm base resistor but as per my calucaltion 
> it needs to be about 106 Ohms if the FPGA is driving 0 to 3.3V signals.
>
> Thus Rcollector = 500 Ohms and R base = 106 Ohms.
>
> Does this make sense?
>
> Thanks.
>
> Albert

Read further on "current gain" or Hfe, alpha, or Beta for transistors.  The 
transistor you choose will affect the level of current gain for your 
calculation.  Another thing to read up on is "saturation" where you can 
start to understand how much base overdrive gives you what saturation 
voltage, information also found in the transistor data sheet. 



Article: 121266
Subject: Latches
From: "devices" <me@home>
Date: Fri, 29 Jun 2007 18:01:32 +0200
Links: << >>  << T >>  << A >>


Unwanted latch inference is a design conditioning
issue. I'm quite comfortable in avoiding the
inference in combinational logic. But when i use
clocked "always blocks" or "processes" there are
cases in which omitting an "else" or a "case"
would be useful in order to keep a previously
registered value. In these cases i'm often
concerned about the synthsesis inferring some
latch. Let me explain.

I consider the missing "else" in two scenarios:

A) - Combinational
B) - Sequential

I just turn my attention to the Scenario B.

Is it safe to assume that no latch is inferred
when there's already a flip flop that stores a
value?

I'm corcerned about the fact that "if" or "case"
logic might become combinational logic (connected
to the input of the flip flop) and, as such, might
pose latch inference issues.

I chose the simple following example (perhaps
too simple or too specialized). Here's a flip
flop with an enable pin:

  VHDL
  ====

  process (clk)
  begin
    if (clk'event and clk='1') then

      if (ce = '1') then
        q <= d;
      end if;

    end if;
  end process;

  VERILOG
  =======

  always @(posedge clk)
  begin

    if (ce)
      q <= d;

  end

1) If the HDL descriptions above match a
built-in flip flop, i have to find another
(less specialized) example!

2) If the selection infers a mux i would
represent the situation with the following
schematics:



- FIGURE A

 ?
 |   _                
 |  | \    +--------+  
 +--|0 |   |        |  
    |  |---|In   Out|--> q
 d--|1 |   |        |
    | /    |   FF   |
     -   +-|>       |  
     |   | +--------+    
     |   |
    ce   clk

In Figure A, the question mark would ask
for a latch, wouldn't it? But if Figure B
is the right guess instead, perhaps it's
safe to assume that no latch will be
inferred.

- FIGURE B

 +---------------------+
 |   _                 |
 |  | \    +--------+  |
 +--|0 |   |        |  |
    |  |---|In   Out|--+-> q
 d--|1 |   |        |
    | /    |   FF   |
     -   +-|>       |  
     |   | +--------+    
     |   |
    ce   clk

1) If Figure B holds true, does it ALWAYS
go like this?

2) Or else, do i always have to store (register)
the value in a q_reg variable and use it to initialize
q, like this? Is it safer?

    q <= q_reg;
    if (ce)
      q <= d;

    OR

    if (ce)
      q <= d;
    else
      q <= q_reg;

-- 

Regards 





Article: 121267
Subject: Re: Latches
From: Jon Beniston <jon@beniston.com>
Date: Fri, 29 Jun 2007 09:06:21 -0700
Links: << >>  << T >>  << A >>
>   always @(posedge clk)
>   begin
>
>     if (ce)
>       q <= d;
>
>   end

Omitting an else here is fine if you ask me.

Cheers,
Jon


Article: 121268
Subject: Xilinx ngdbuild question
From: Kuo <chinchia.kuo@sbcglobal.com>
Date: Fri, 29 Jun 2007 16:11:24 GMT
Links: << >>  << T >>  << A >>
Hi,
I use Coregen (CORE Generator of Xilinx) to generate a fifo and I get 
.ngc. How do I specify this in ngdbuild command line? I tried to use
" -l myFifo.ngc", but I got the following error

  ERROR:NgdBuild:604 - logical block 'rtl/ddr_async_interface/myFifo' with
    type 'myFifo' could not be resolved. A pin name misspelling can cause
    this, a missing edif or ngc file, or the misspelling of a type name. 
Symbol
    'myFifo' is not supported in target 'virtex5'.


Any help is appreciated.


Thanks

Article: 121269
Subject: Re: How to snoop an inout signal in EDK?
From: motty <mottoblatto@yahoo.com>
Date: Fri, 29 Jun 2007 09:56:34 -0700
Links: << >>  << T >>  << A >>
A somewhat easy workaround is to use the Xilinx provided
util_vector_logic core.  It one of the IP available in the utility
section of the EDK cores.  I have two in my project right now just so
i can route some things up to the top without having to buffer them in
the custom IP.

I just use an AND funtion and tie one of the input high and the other
to my signal of interest.  Then the output gets routed out
externally.  You'll have to rebuild, but that shouldn't be a big deal.



Article: 121270
Subject: Re: Xilinx ngdbuild question
From: "davide" <davide@xilinx.com>
Date: Fri, 29 Jun 2007 10:01:18 -0700
Links: << >>  << T >>  << A >>
Kuo,

There is no need to use the -l switch for CoreGen.  If the .ngc resides in 
the main project directory, you do not need to do anything (in terms of 
command line options).  If the .ngc resides elsewhere you need to specify 
the -sd option.  The primary reason for a NgdBuild:604 error is because the 
core is seen as a black box in synthesis and the netlist is required in this 
implementation phase.  By default, NgdBuild looks in the main project 
directory for the netlist.  If the netlist is not there it needs to know 
where it resides and this can be done by the -sd switch or if using the GUI 
in the properties box for NgdBuild (set macro search path).

-David

"Kuo" <chinchia.kuo@sbcglobal.com> wrote in message 
news:Maahi.462$eY.6@newssvr13.news.prodigy.net...
> Hi,
> I use Coregen (CORE Generator of Xilinx) to generate a fifo and I get 
> .ngc. How do I specify this in ngdbuild command line? I tried to use
> " -l myFifo.ngc", but I got the following error
>
>  ERROR:NgdBuild:604 - logical block 'rtl/ddr_async_interface/myFifo' with
>    type 'myFifo' could not be resolved. A pin name misspelling can cause
>    this, a missing edif or ngc file, or the misspelling of a type name. 
> Symbol
>    'myFifo' is not supported in target 'virtex5'.
>
>
> Any help is appreciated.
>
>
> Thanks 



Article: 121271
Subject: Re: Latches
From: "John_H" <newsgroup@johnhandwork.com>
Date: Fri, 29 Jun 2007 10:10:29 -0700
Links: << >>  << T >>  << A >>
It *is* safe to assume that no latch is inferred when there's already 
a flop that stores the value.

The latches in combinatorial equations are because the LHS or 
combinatorial output relies on itself as a combinatorial input in the 
RHS.  In sequential logic, the new register value depends on the onld 
register value and nowhere tries to assign the new value based on the 
new value which *would* generate a latch.

Your figure B always holds true always because the implied "q <= q" in 
the absent else clause is effectively "next_q <= prev_q" rather than 
"next_q <= next_q" which is *not* implied.

The sequential logic LHS equation is always the value after the clock 
edge.  The sequential logic RHS is always the value before the clock 
edge.  Everything flows nicely.

- John_H

"devices" <me@home> wrote in message news:46852a0c$0$10616$4fafbaef@reader2.news.tin.it...

  Unwanted latch inference is a design conditioning
  issue. I'm quite comfortable in avoiding the
  inference in combinational logic. But when i use
  clocked "always blocks" or "processes" there are
  cases in which omitting an "else" or a "case"
  would be useful in order to keep a previously
  registered value. In these cases i'm often
  concerned about the synthsesis inferring some
  latch. Let me explain.

  I consider the missing "else" in two scenarios:

  A) - Combinational
  B) - Sequential

  I just turn my attention to the Scenario B.

  Is it safe to assume that no latch is inferred
  when there's already a flip flop that stores a
  value?

  I'm concerned about the fact that "if" or "case"
  logic might become combinational logic (connected
  to the input of the flip flop) and, as such, might
  pose latch inference issues.

  I chose the simple following example (perhaps
  too simple or too specialized). Here's a flip
  flop with an enable pin:

    VHDL
    ====

    process (clk)
    begin
      if (clk'event and clk='1') then

        if (ce = '1') then
          q <= d;
        end if;

      end if;
    end process;

    VERILOG
    =======

    always @(posedge clk)
    begin

      if (ce)
        q <= d;

    end

  1) If the HDL descriptions above match a
  built-in flip flop, i have to find another
  (less specialized) example!

  2) If the selection infers a mux i would
  represent the situation with the following
  schematics:

  - FIGURE A

   ?
   |   _                
   |  | \    +--------+  
   +--|0 |   |        |  
      |  |---|In   Out|--> q
   d--|1 |   |        |
      | /    |   FF   |
       -   +-|>       |  
       |   | +--------+    
       |   |
      ce   clk

  In Figure A, the question mark would ask
  for a latch, wouldn't it? But if Figure B
  is the right guess instead, perhaps it's
  safe to assume that no latch will be
  inferred.

  - FIGURE B

   +---------------------+
   |   _                 |
   |  | \    +--------+  |
   +--|0 |   |        |  |
      |  |---|In   Out|--+-> q
   d--|1 |   |        |
      | /    |   FF   |
       -   +-|>       |  
       |   | +--------+    
       |   |
      ce   clk

  1) If Figure B holds true, does it ALWAYS
  go like this?

  2) Or else, do i always have to store (register)
  the value in a q_reg variable and use it to initialize
  q, like this? Is it safer?

      q <= q_reg;
      if (ce)
        q <= d;

      OR

      if (ce)
        q <= d;
      else
        q <= q_reg;

  --

  Regards 
  



Article: 121272
Subject: Re: Xilinx ngdbuild question
From: Sean Durkin <news_jun07@durkin.de>
Date: Fri, 29 Jun 2007 19:12:56 +0200
Links: << >>  << T >>  << A >>
Kuo wrote:
> Hi,
> I use Coregen (CORE Generator of Xilinx) to generate a fifo and I get
> .ngc. How do I specify this in ngdbuild command line? I tried to use
> " -l myFifo.ngc", but I got the following error
> 
>  ERROR:NgdBuild:604 - logical block 'rtl/ddr_async_interface/myFifo' with
>    type 'myFifo' could not be resolved. A pin name misspelling can cause
>    this, a missing edif or ngc file, or the misspelling of a type name.
> Symbol
>    'myFifo' is not supported in target 'virtex5'.
You have to specify the macro search path with the "-sd" option
on the command line. That's the path where ngdbuild is supposed to look
for netlists. You can also specify multiple paths like this "-sd path1
-sd path2"

HTH,
Sean

-- 
My email address is only valid until the end of the month.
Try figuring out what the address is going to be after that...

Article: 121273
Subject: Re: Xilinx ngdbuild question
From: Kuo <chinchia.kuo@sbcglobal.com>
Date: Fri, 29 Jun 2007 17:52:21 GMT
Links: << >>  << T >>  << A >>
Thanks for the answer form Sean and Davide.

Sean Durkin wrote:
> Kuo wrote:
>> Hi,
>> I use Coregen (CORE Generator of Xilinx) to generate a fifo and I get
>> .ngc. How do I specify this in ngdbuild command line? I tried to use
>> " -l myFifo.ngc", but I got the following error
>>
>>  ERROR:NgdBuild:604 - logical block 'rtl/ddr_async_interface/myFifo' with
>>    type 'myFifo' could not be resolved. A pin name misspelling can cause
>>    this, a missing edif or ngc file, or the misspelling of a type name.
>> Symbol
>>    'myFifo' is not supported in target 'virtex5'.
> You have to specify the macro search path with the "-sd" option
> on the command line. That's the path where ngdbuild is supposed to look
> for netlists. You can also specify multiple paths like this "-sd path1
> -sd path2"
> 
> HTH,
> Sean
> 

Article: 121274
Subject: Re: Bidirectional LVDS
From: Richard Henry <pomerado@hotmail.com>
Date: Fri, 29 Jun 2007 11:19:03 -0700
Links: << >>  << T >>  << A >>
On Jun 27, 1:06 pm, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de>
wrote:
> In comp.arch.fpga Steve at fivetrees <s...@nospamtafivetrees.com> wrote:
> ...
>
> > To the OP re bidirectional: it's not clear to me whether you expect to
> > run two loops (one outgoing, one incoming), or shove data down one pair
> > of wires in boith directions. If the latter, I'm not clear on where
> > you'd put the receiver load - at both ends? If so, expect to see half
> > the voltage across each receiver.
>
> That's what Bus-LVDS for.
>
> Called also M-LVDS, LVDM or ...

How about a hybrid solution?  I don't want to run so many wires (I
don't have room for such a big connector).  Could I gang up 4 signals
per pair without a lot of overhead, and still keep it bidirectional?




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