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Jim Granville wrote: > Herbert Kleebauer wrote: > > Here a description of the students project: > > ftp://137.193.64.130/pub/mproz/mproz_e.pdf > > This is such a simple CPU, that I quickly tried it targeting the > ATF1508 - which _is_ 5V and _is_ PLCC84, so you can keep all your design > notes, and just re-map the pins on the PCB layout you have. Thanks for the mail. But this example clearly shows the difference between a textual and a graphical representation of circuit. > > /* ~~~~~~~~~~~~~~~ ALU, pre-adder ~~~~~~~~~~~~~~~~~ */ > /* ALU: IF (s7=0) THEN out=in1 ADD in2 , F=carry > ELSE out=in1 NOR in2 , F=zero > */ > ALU = s7 & !(XGate # YGate) > # !s7 & (XGate $ YGate); /* Dummy, until adder done */ How should the student get a feeling how many gates are necessary to implement this two lines? It's the same as programming in a HLL. No question, it is much more effective to us a HLL than using an assembler. But any HLL programmer should have done assembly programming so he has a feeling what a HLL code snippet has for consequences for the CPU and so he not always selects the code which is most easily written but the code which most easily can be calculated by the CPU.Article: 116951
On Tue, 20 Mar 2007 18:19:11 -0700, Austin <austin@xilinx.com> wrote: >Taylor, > >Well, Peter and I read the newsgroup, so we can provide an omudsman >function. > >Did you register? Did you get confirmation back? What was it that did >not allow you to file a webcase? > >If possible, send me what went wrong (links, steps taken, etc.). > >With 250,000 seats of software, some people are able to file >webcases...so it can't be completely broken! For example, I see the >reports on what cases get filed, and what category they are assigned to >(software, hardware, and so on). > >One other comment: our synthesis tool (XST) was never meant to compete >with the "real" tools that exist. XST is a vehicle for research into >synthesis, where we have an opportunity to test how synthesis works with > our FPGAs. We share all synthesis ideas and improvements with the >"real" synthesis tool vendors, so that they may add value by performing >more efficient synthesis using our devices. This is in no way an >apology for bugs, but a statement of fact. XST is not intended to >compete with "real" synthesis tools. It is made available in Webpack, >as a means to allow others to get some feeling for the flow, and the >potential. The XST team is dedicated to pioneering improvements, and >they very much like to get feedback. > >Efficient synthesis for things like our DSP48e, and other features are >not trivial: and older tool may synthesis correctly, yet be horribly >inefficient, and turn out huge areas and slow logic. > >In any event, I will pass your issues along to the XST development team >once I get the details of what did not work. > >Austin I wonder how many customers Xilinx has lost because they see that the performance of their parts with their own tools isn't as good as the competition...? I would think that many users will assume that Xilinx know their parts best, therefore their own software ought to get the most out of them, and so would look at competing devices before thinking of looking at third-party software.Article: 116952
> I'm going to work on a Virtex 4 FX100 soon so I'll
> need all the horsepower I can get for the P&R runs...
I've been working on a Virtex4 LX100 design early this
year and the main problem was memory usage. I upgraded
my Windows XP Box to 4 GBytes (and patched to allow
3 GBytes/process) and even that was not enough!
Above something like 55% Lut/FF usage par 8.2 failed
("out of memory") after 2 hours or more.
I wonder how it should be possible to work with
even larger FPGAs!?
bye,
Michael
Article: 116953On Mar 20, 11:24 pm, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > InmateRemo wrote: > > I've played around with Xilinx PicoBlaze processor, but it's time to step up > > into 32-bit softcore CPU world for more serious designs, potentially getting > > in line with embedded OS. > > > I am facing a choice, whether to use always up to date Xilinx EDK tools > > integrated with ISE and MicroBlaze, which comes with good documentation, > > there is a third party uClinux port. > > > The other alternative is using Altium Designer FPGA goodies bag. They offer > > a wide range of Wishbone compatible cores (no source code though), platform > > independent primitive libraries, a choice of few softcore processors > > including 32-bit RISC core TSK3000, and even support for the same > > MicroBlaze, but I've noticed that supported version is a bit behind. > > > Currently I am considering Altium route as it brings more value to the > > table, providing vendor independence, but at the same time I would entirely > > depend on Altium continuous support towards FPGAs. > > > I would appreciate if anybody could share a similar experience or thoughts. > > Aren't these two mutually exclusive ?! > "(no source code though)" > and > "providing vendor independence" > > ie, with no source code, you have just locked yourself into vendor > Altium - surely a crazy thing to do ? > > If you like vendor independance, then look at Lattice Mico8/Mico32, > which are open source. > > -jg Yes Lattice Mico8/Mico32 are open source, but can you really use them anywhere else except only with Lattice ISP Lever and Lattice FPGA devices??? Yes, seems like Atlium has invested heavily into FPGAs, leading EDA industry with seamless integration, and having schematics, layout, FPGA code as well as C/C++ code for softcore CPU all integrated into single environment does bring benefits to the design team. And I am sure Altium will support this vision as long as it brings cash on the table.Article: 116954
On 2007-03-20, Brandon Jasionowski <killerhertz@gmail.com> wrote: > > For some reason I'm only getting zero-valued data out of channel 1 and > consequently is never being enabled, unlike channel 2... Any ideas? Does it do that even if you change your trigger to only wait for data on channel 1? -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 116955
On Mar 20, 9:50 pm, j...@mit.edu wrote: > Wow, I've been using xst (and webpack, base-x, and foundation) for > years now and never once heard this. I've used it in over 20 designs, > including some moderately-high-end virtex-4 stuff, and never had the > slightest idea that I was using inferior tools. > > Who makes these other synthesis tools? Are they expensive? Is this > what happens when you do all of your engineering at a university? > > ...Eric Very Interesting thread - 2 of the "other synthesis tools" are from Synplicity, and from Mentor (precision RTL) , and it just so happens both are supplied with Lattice ispLEVER tools - which offer a free d/l from the web - sorry to hear that 250,000 Xilinx customers have been using an inferior synthesis tool all this time, by Xilinx' own admission - All of the vendors work hard to supply reliable toolsets to their customer base - and judging from all the marketing foils on every vendor website, they have the best choice- So the keyword here is choice - try out the toolsets offered free from each vendor website - all it'll cost is some bandwidth and disc space - Michael Thomas Lattice FAE -NYArticle: 116956
Hi All, I'm using the STAPL player to configure my Xilinx chips via JTAG interface. However to get them running correctly, I have to generate the "PROG pulse" (as it was often discussed in this group). The STAPL file is generated in the batch mode with script like this: setmode -bsfile setcable -p stapl -file my_conf.stapl addDevice -p 1 -part xc18v512 addDevice -p 2 -part xc18v512 addDevice -p 3 -file my_conf1.bit addDevice -p 4 -file my_conf2.bit addDevice -p 5 -file my_conf3.bit program -p 3 4 5 closecable quit The problem is, that I can not find the batch command for embedding the "send prog pulse" sequence into the STAPL file. Neither there is such option in the "Generate Programming File" properties in the ISE itself... How can I force the STAPL player to generate the PROG pulse before programming? -- TIA & Regards, Wojtek Zabolotny wzab@ise.pw.edu.plArticle: 116957
Working with a coolrunner2 CPLD. Is there a way to erase whatever has been programmed into the CPLD, without using JTAG?Article: 116958
Dmitry Teytelman wrote: > On Wed, 21 Mar 2007, Duane Clark wrote: > >> dimtey@moc.liamg wrote: >>> ... >>> So here is the problem: the data is written correctly into the SRAM, >>> but not into the block RAM. It is a timing problem - errors go away >>> if I lower >>> the clock frequency. >>> ... >> >> Show the actual clock constraints you are using. > > The data acquisition logic and BRAMs are clocked by a DCM driving a > BUFG. The DCM divides the input clock by 2 (using CLKDV output). Here is > the timing constraint on the DCM input clock: > > NET "clkp" TNM_NET = FFS(*) "clkp"; > TIMESPEC "TS_clkp" = PERIOD "clkp" 3.8 ns HIGH 50 %; Get rid of the FFS(*) and see what happens. The BlockRAM specifically needs RAMS(*) if you're trying to keep other elements such as multipliers and latches off the timing specification. I usually end up with something like NET sysClk TNM_NET = sysClk; to specify my main clock. In this syntax it applies to all sequential elements. - John_HArticle: 116959
On Mar 20, 11:52 pm, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > Well, I don't quite take the same meaning from the above web-statement, > as I do from your posting : > > "our synthesis tool (XST) was never meant to compete with the "real" > tools that exist." " It is made available in Webpack, as a means to > allow others to get some feeling for the flow, and the potential." <snip> > Your posting moves XST into the "not for real designs"/ > [as is, where is] pigenhole, which is frankly startling. I think what he means is quite simple: XST is not Synplify (etc), and was not meant to replace it, since the most serious customers would be using something like that anyway. Rather than compete with those tool vendors, Xilinx actually shares information with them.Article: 116960
Hi, can somebody help me to find an implementation of LZW compression/decompression algorithm in VHDL? Thanks a lot. EricArticle: 116961
Picking a Softcore is tough because it requires purchasing software tools no matter which path you choose (Xilinx EDK, or Altium FPGA Suite). The frustrating thing with Xilinx is the constant Tool upgrades every few months... I still have ISE Webpack 7.2 at home and now they are on 9.2. I don't think Altium requires you to upgrade as often. I guess you wouldn't have to upgrade Xilinx tools either. Altium brings a lot more to the table (with multiple cores with compilers for each). Vender independence isn't that big of a deal... now that Xilinx has the Spartan 3AN with the built in Flash... I don't even need to look at the Altera MAXII anymore. The Lattice Mico32 is pretty cool especially since it has a Wishbone bus. I haven't looked, but I've been told the Mico32 is written in behavioral VHDL. So you could port it to Xilinx. You would have to use the command line GCC and manually figure a way to put the code in the block RAM or external RAM. I think the Mico32 License says Lattice only parts, but for home/research use you would be fine. If you don't want to spend money on tools Mico32 or an 8051 core would be good choices. You could use SDCC for the 8051 compiler, and you could get FreeRTOS running on it... That isn't as cool as uClinux, but you won't have to spend money on tools. If you have the money I probably would go the MicroBlaze route. The knowledge gained by training yourself on the Microblaze is more transferable to another job, if you switch companies... You can pretty easily talk a company into spending $1000 on ISE and EDK, but spending $10,000 on Altium is a harder sell. ERicArticle: 116962
How's about getting some XC95108 in PLCC-84? Use Webpack/ISE for schematic entry.. You have the perfect opportunity to build on this to introduce an HDL afterwards... Only thing might be cost and availability of devices and proto-boards for them, and the efficiency of only 108 macrocells in creating a useable microcontroller. Just an idea. but... I _wish_ i'd been introduced to VHDL in level one at university. All digital logic design ties together, and in my opinion all the different aspects can and should be taught as interrelated topics. (contrary to some practices) Have you asked your students if they're interested in messing around with Viewlogic and associated parts versus getting their feet wet with FPGA/CPLD/VHDL/Xilinx? just my 2p. Ben "Herbert Kleebauer" <klee@unibwm.de> wrote in message news:46010821.9FBCAAF6@unibwm.de... > Jim Granville wrote: >> Herbert Kleebauer wrote: > >> > Here a description of the students project: >> > ftp://137.193.64.130/pub/mproz/mproz_e.pdf >> >> This is such a simple CPU, that I quickly tried it targeting the >> ATF1508 - which _is_ 5V and _is_ PLCC84, so you can keep all your design >> notes, and just re-map the pins on the PCB layout you have. > > Thanks for the mail. But this example clearly shows the difference > between a textual and a graphical representation of circuit. > > >> >> /* ~~~~~~~~~~~~~~~ ALU, pre-adder ~~~~~~~~~~~~~~~~~ */ >> /* ALU: IF (s7=0) THEN out=in1 ADD in2 , F=carry >> ELSE out=in1 NOR in2 , F=zero >> */ >> ALU = s7 & !(XGate # YGate) >> # !s7 & (XGate $ YGate); /* Dummy, until adder done */ > > How should the student get a feeling how many gates are necessary > to implement this two lines? It's the same as programming in a > HLL. No question, it is much more effective to us a HLL than > using an assembler. But any HLL programmer should have done > assembly programming so he has a feeling what a HLL code > snippet has for consequences for the CPU and so he not always > selects the code which is most easily written but the code which > most easily can be calculated by the CPU.Article: 116963
Tommy, Touche. AustinArticle: 116964
On Mar 21, 5:25 am, Herbert Kleebauer <k...@unibwm.de> wrote: > Thanks for the mail. But this example clearly shows the difference > between a textual and a graphical representation of circuit. > > > /* ~~~~~~~~~~~~~~~ ALU, pre-adder ~~~~~~~~~~~~~~~~~ */ > > /* ALU: IF (s7=0) THEN out=in1 ADD in2 , F=carry > > ELSE out=in1 NOR in2 , F=zero > > */ > > ALU = s7 & !(XGate # YGate) > > # !s7 & (XGate $ YGate); /* Dummy, until adder done */ > > How should the student get a feeling how many gates are necessary > to implement this two lines? It's the same as programming in a > HLL. No question, it is much more effective to us a HLL than > using an assembler. But any HLL programmer should have done > assembly programming so he has a feeling what a HLL code > snippet has for consequences for the CPU and so he not always > selects the code which is most easily written but the code which > most easily can be calculated by the CPU. By making them implement select pieces of the design in gates - on paper, in a graphical simulator (various java thingies are popular in course work for that purpose), on a piece of graph paper representing the configuration of a classic sum-of-products PLD, or even in 74xx ttl. A major point of engineering education (both academic and on-the-job) is learning to manage abstraction and scope. Learning to look at some pieces in ultimate detail where that is important, but learning to look at others in their abstract or high-level representation, so that you can get actual work done and build interesting things in finite amounts of time. As a working engineer, probably my most valuable skill is having the "knack" for rapidly finding the specific part of the system where I need to drill down to the basic level to fix a fundamental problem - vs. the many parts where the high level abstraction is valid. If you really want to stick to date level design, another thing you could do is write or adapt your own gate level graphical design too that outputs simplistic HDL. Then you have a tool that you can port - both across computing platforms and across target hardware devices.Article: 116965
are bumps allowed here? bumpArticle: 116966
hi, I have a design with two clock that I want to mux toward a single clock like this with mode select CLK <= CLK_1 when mode_1, CLK_2 when mode_2, CLK_1 when others; Is there another manner to do this because Quartus says that CLK is a gated clock ! thanksArticle: 116967
> In other words, XST is a test vehicle where we are intentionally > experimenting, in order to improve. Hi Austin, is this your personal meaning, or official Xilinx? Do the Xilinx-software-team see their work in this context? Does this mean, that XST and/or ISE should not be used for serious work? ThomasArticle: 116968
"eric" <erixx@gmx.net> wrote in message news:etre5p$ork$1@aioe.org... > Hi, can somebody help me to find an implementation of > LZW compression/decompression algorithm in VHDL? > > Thanks a lot. > > Eric I'd be surprised to see anything for free. I was working on an LZW style algorithm for my employer because there just isn't much out there that you can get without paying big $$ to the big players in IP. I found later another internal group in our 50k+ employee company also developed an LZW style algorithm for their ASIC work. You might be able to find the algorithm for big money. LZW is a memory-hungry scheme and will take up a large chunk of your memory resources especially if you have more than one stream. Interoperability is another issue if you expect to work with other "standard" LZW schemes as opposed to something proprietary. I can understand why there wasn't anything out there when I was developing the algorithm for a proprietary, closed system. It's still a push for me to consider it in the newest generation of low cost FPGAs.Article: 116969
OK. I've found it by watching the IMPACT console, while using GUI. It is a "-prog" option for "program" command. -- Regards, WojtekArticle: 116970
On Mar 21, 8:34 am, mtsuka...@gmail.com wrote: > Working with a coolrunner2 CPLD. Is there a way to erase whatever has > been programmed into the CPLD, without using JTAG? As far as I know, the only way to erase/program Xilinx CPLDs is via JTAG. -Dave PollumArticle: 116971
"Benjamin Todd" <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPITALS.ch> wrote in message news:etrgnt$gov$1@cernne03.cern.ch... > > I _wish_ i'd been introduced to VHDL in level one at university. All > digital logic design ties together, and in my opinion all the different > aspects can and should be taught as interrelated topics. (contrary to some > practices) > Hi Benjamin, OTOH, I'm glad that I know what the VHDL is compiled into. I think Herbert's intention in this class is to show his students what the logic is made up from, and schematics of gates and FFs do achieve this. As you say, I'd expect the course to then go on to show how the same thing can be implemented in 5 minutes with 10 lines of Verilog (or 50 lines of VHDL! :-)) but I do see where he's coming from. Cheers, Syms.Article: 116972
<patrick.melet@dmradiocom.fr> wrote in message news:1174490375.699450.296690@p15g2000hsd.googlegroups.com... > hi, > > I have a design with two clock that I want to mux toward a single > clock like this > > with mode select CLK <= > CLK_1 when mode_1, > CLK_2 when mode_2, > CLK_1 when others; > > Is there another manner to do this because Quartus says that CLK is a > gated clock ! > > thanks > Patrick, Are the two clocks asynchronous? Cheers, Syms.Article: 116973
i have a byte array of size 10 and i need to shift values in the
array
to left by 5 positions in 5 clocks.
here is the code im using.
reg [7:0] data[0:9];
// data shifting process
reg ps_shift_start;
reg ps_done;
reg [1:0] ps_state;
parameter ps_s0 = 2'b00;
parameter ps_s1 = 2'b01;
reg [12:0] ps_shift;
integer ps_index;
always @ (posedge clk) begin
if(reset == 1) begin
ps_done <= 0;
ps_state <= ps_s0;
end
else begin
case(ps_state)
ps_s0: begin
if(ps_shift_start == 1) begin
ps_done <= 0;
ps_shift <= 0;
ps_state <= ps_s1;
end
end
//
ps_s1: begin
if(ps_shift < 5) begin
for(ps_index = 0; ps_index < 10;
ps_index = ps_index + 1) begin
data[ps_index] <=
data[ps_index + 1];
end
end
else begin
ps_done <= 0;
ps_state <= ps_s0;
end
end
endcase
end
end
the problem is XST syntherziser infferes lot of flip-flops for the
signal 'data'. is't is possible to use
distributed RAM for signal 'data'. if posssible, how do i do that?
thank you
Article: 116974Dear all I am trying to manually map "2-bit AND" function into single slice, with no luck -: I type the commands below in the FPGA editor. Problem is that, "F" port of slice is NOT connected to "D" pin of LUT. I wonder if following is correct. F:\#LUT:D=A1\*A2\ If someone has experience, let us know how I should modify the command. Any document or pointer will be also grateful. I am using ISE 8.2.03 and Virtex-4. Thank you in advance. -------------------------------------------------------------------------------------------------------------------------- select site "SLICE_X0Y2" add setattr comp $COMP_0 Name s0 unselect -all select site "SLICE_X2Y2" add setattr comp $COMP_1 Name s1 unselect -all select comp "s1" setattr comp s1 F A1*A2 setattr comp s1 G A1*A2 setattr comp s1 Config COUTUSED:\#OFF\ YUSED:0\ XUSED:0\ F5USED:\#OFF\ YBMUX:\#OFF\ YINIT:\#OFF\ F:\#LUT:D=A1\*A2\ REVUSED:\#OFF\ SYNC_ATTR:\#OFF \ SRFFMUX:\#OFF\ FFY_SR_ATTR:\#OFF\ FFX:\#OFF\ FFY:\#OFF\ FFX_SR_ATTR:\#OFF\ G_ATTR: \#OFF\ DIG_MUX:\#OFF\ CY0G:\#OFF\ FXUSED:\#OFF\ DIF_MUX:\#OFF\ F_ATTR: \#OFF\ CY0F:\#OFF\ DIGUSED:\#OFF\ SHIFTOUTUSED:\#OFF\ BYOUTUSED:\#OFF\ FFX_INIT_ATTR:\#OFF\ FFY_INIT_ATTR:\#OFF\ .... --------------------------------------------------------------------------------------------------------------------------
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