Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
"LilacSkin" <lpaulo07@iseb.fr> wrote in message
news:1176715616.959521.180000@b75g2000hsg.googlegroups.com...
> Hi,
> I build a IPIF master with Create/Import Peripheral.
> I try the example write in the user_logic.vhd:
> volatile Xuint32* Data;
> Data=(Xuint32*) XPAR_IPIF_MASTER_0_BASEADDR;
>
> // contrôl register
> Data=(Xuint32*)(0x00+0x00);
> *(Data)=0x40;
You just overwrite your "Data" pointer. Unless XPAR_IPIF_MASTER_0_BASEADDR
is 0, you won't be accessing your peripheral.
Didn't you mean
Data=(Xuint32*)(XPAR_IPIF_MASTER_0_BASEADDR+0x00);
...and so on?
-Ben-
Article: 118001On 16 Apr 2007 02:18:30 -0700, "Antti" <Antti.Lukats@xilant.com> wrote: >On 16 Apr., 10:31, "Nokia_E61i : I am waiting for you!!!!!!" ><zhy.sh...@gmail.com> wrote: >> I want to design a prototype of SDIO peripheral card which is enabled >> with GPS function. But I have no experience in SDIO card design. >> >> Who can provide me a reference sample? >> >> Thanks a lot. > >i have a proto-type quality SD card side ip, that could be used as >starting point. > >or you can of course buy the IP from arazan if your budget allows > >Antti Or just buy the Arasan SDIO interface chip : http://www.arasan.com/products/semiconductors.phpArticle: 118002
It seems to work better (much better than 8.1), but seems to have a few issues that make it a bit hard to use. 1/ Sometimes it auto trims logic which is required - particularly when it is associated with Jtag devices. This behaviour seems unpredictable, and happens when completely unrelated logic is moved around, or even when an identical logical expression in vhdl is expressed differently. 2/ Sometimes multiple contending tristate drivers are generated when only one exists. This seems to depend on completely unrelated logic and also seems to depend on the syntax level in vhdl where the driver is declared. 3/ Routing sometimes fails, but adding a bit of extra random stuff can make it work. Sometimes a source program which fails to route on 9.1 routes quite happily on 7.1 . 4/ The random experimentation (usually tedious) to get round these problems is usually successful ,but can be very time consuming. Does anyone have any comment , or way round any of these difficultiesArticle: 118003
Maik Ritter wrote: > On 13 Apr., 15:22, David Brown <d...@westcontrol.removethisbit.com> > wrote: > >> (It's easier to follow threads if you quote appropriately - if you want >> to use Google's broken Usenet interface, you have to learn the tricks.) > > Hello David! > > Sorry for not quoting. I hope this times it works. > Yes, that's working fine. >> It's a while since I did any FPGA stuff, but as far as I know, the web >> edition fully supports the whole Max7000 series. The source code for >> the configuration controller in the EPM7128 is available along with the >> NIOS development kit (although it's easy enough to write your own). > > Now, I figured out that there is no appropriate configuration chip for > the Stratix device on my board. But I also figured out, that the > EPM7128, the FPGA and the Web Interface of the NIOS implementation on > the FPGA together give me the opprtunity to use this board as FPGA dev > Kit (I'm not interested in NIOS, yet). So I can load the VHDL > configurations I made with Quartus II (.hexout file) into the > configuration flash memory via the Web Interface that comes with the > board. > Now I understand, that I don't need any flash functionality of Quartus > II, when I use this board. > I believe you are correct here (when using the Nios board, I never actually downloaded into flash - I always had the jtag connection in). >> If you are thinking about making your own boards, the EPM7128 is a silly >> choice - it's expensive and limited, and completely unnecessary with >> more modern FPGAs. > > You are right! In the case of an own board I would use the appropriate > configuration chip for the chosen FPGA device. I think, the guys from > Altera used the EPM7128 because they needed some custom functions for > this dev board, and because this chip was state of the art at the > time, they build it. > The idea of using the EPM7128 along with a parallel flash is that the same flash device can be used for the FPGA image and the Nios program, it can be programmed under the control of the Nios, and it can store two images (a "working" image and a "safe" image). I don't have the details in my head, but I believe you can get the same sort of functionality with newer FPGAs using either the serial flash devices, or a parallel flash device. Even if you want to use an external CPLD to control booting (not a bad idea for flexibility), there are better (faster and cheaper) choices than the EPM7128 if you can choose freely. > Slowly, I get an idea of using this board and Quartus II . . . > > Greets > Maik >Article: 118004
On 16 avr, 11:45, "Ben Jones" <ben.jo...@xilinx.com> wrote: > "LilacSkin" <lpaul...@iseb.fr> wrote in message > > news:1176715616.959521.180000@b75g2000hsg.googlegroups.com... > > > Hi, > > I build a IPIF master with Create/Import Peripheral. > > I try the example write in the user_logic.vhd: > > volatile Xuint32* Data; > > Data=3D(Xuint32*) XPAR_IPIF_MASTER_0_BASEADDR; > > > // contr=F4l register > > Data=3D(Xuint32*)(0x00+0x00); > > *(Data)=3D0x40; > > You just overwrite your "Data" pointer. Unless XPAR_IPIF_MASTER_0_BASEADDR > is 0, you won't be accessing your peripheral. > > Didn't you mean > > Data=3D(Xuint32*)(XPAR_IPIF_MASTER_0_BASEADDR+0x00); > > ...and so on? > > -Ben- No change, There is something i don't really understand: if I want to send data from an IP to my SOPC (in a BRAM), I need to make a MASTER IPIF which transfer the data to the BRAM. In the MASTER (PLB) IPIF, it takes the data and the address from my IP TEST with the ports Bus2IP and sends it to the BRAM with the ports IP2Bus. What is the aim of the IP2IP port ? When I want to send data to my BRAM, I send the address of the MASTER IPIF or of the BRAM ??? ThanksArticle: 118005
Hi all, My ASIC design requires dual port memories(one port R/W other port only read) but there is a constraint on using it. Instead I am planning to create this memory using single port RAM's. Writes to this memory take place at 60 Mhz while reads can occur at freq varying from 5-30 Mhz. Is there some way out?Article: 118006
g.eckersley@ieee.org writes:
>3/ Routing sometimes fails, but adding a bit of extra random stuff can
>make it work. Sometimes a source program which fails to route on 9.1
>routes quite happily on 7.1 .
Try playing with the -t parameter for map and par. Officially it's called
"cost table" but I think it's just a seed for the random number generator. There
are occasions where par simply won't meet the constraints in 40min, but with
another -t-value it's done in 7min...
--
Georg Acher, acher@in.tum.de
http://www.lrr.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 118007On 16 avr, 11:45, "Ben Jones" <ben.jo...@xilinx.com> wrote: > "LilacSkin" <lpaul...@iseb.fr> wrote in message > > news:1176715616.959521.180000@b75g2000hsg.googlegroups.com... > > > Hi, > > I build a IPIF master with Create/Import Peripheral. > > I try the example write in the user_logic.vhd: > > volatile Xuint32* Data; > > Data=3D(Xuint32*) XPAR_IPIF_MASTER_0_BASEADDR; > > > // contr=F4l register > > Data=3D(Xuint32*)(0x00+0x00); > > *(Data)=3D0x40; > > You just overwrite your "Data" pointer. Unless XPAR_IPIF_MASTER_0_BASEADDR > is 0, you won't be accessing your peripheral. > > Didn't you mean > > Data=3D(Xuint32*)(XPAR_IPIF_MASTER_0_BASEADDR+0x00); > > ...and so on? > > -Ben- No change, when I want to store data from an IP to a BRAM, I send the data with an address to my Master PLB IPIF, but what is this address ? An address of the BRAM ??? The data and the address come from an IP TEST block. The IP TEST block is an IPIF ?? Tk very muchArticle: 118008
<rohit2000s@yahoo.com> wrote in message news:1176665608.491852.100860@n59g2000hsh.googlegroups.com... > Hi, > > I was wondering how the number 166Mhz for DDR came up? Why not say... > 200MHz/250MHz DDR? I am sure there is some thought process behind > that, could someone help me walk through? > > Thanks in advance ! > -Rohit > Hi Rohit, It's because the woman who invented DDR memory had polydactylism. See http://en.wikipedia.org/wiki/Polydactyl . This meant she could count up to 6ns on one hand, so she made the operation frequency 1/6ns = c.166MHz HTH, Syms.Article: 118009
On Apr 16, 8:54 am, "B. Joshua Rosen" <bjro...@polybusPleaseDontSpamMe.com> wrote: > I've been trying to launch ISE (9.1SP3) and I get this error > > FATAL_ERROR:Portability:Port_ExecLoaderInit.c:117:1.4 - The executable > </home/bjrosen/_pn> can't be found. The installation was not > complete. > Process will terminate. For more information on this error, please > consult > the Answers Database or open a WebCase with this project attached at > http://www.xilinx.com/support. > > If I launch it from the $XILINX/bin/lin directory it works fine so it > would appear to be some sort of search path problem but I've got > everything in my paths, > > echo $PATH > /usr/local/tools/Xilinx/bin/lin:/usr/local/tools/Xilinx/java/lin/jre/bin:/ > usr/local/tools/Xilinx/chipscope/bin/lin:/usr/local/tools/Xilinx/bin/ > lin64:.:/usr/local/tools/flexlm/bin:/usr/java/jre1.5.0_02/bin:/usr/local/ > tools/hdlmaker_lib/i686/bin:/usr/local/tools/hdlmaker_lib/csh:/usr/local/ > tools/jre1.5.0_10/bin:/usr/local/bin:/usr/bin:/sbin:/usr/sbin:/bin:/usr/ > X11R6/bin:/usr/local/csh:/usr/local/sbin:/usr/local/tools/acrobat/bin:/ > usr/local/tools/nc_sim/tools/bin > > echo $LD_LIBRARY_PATH > /usr/local/tools/Xilinx/bin/lin:/usr/local/tools/Xilinx/java/lin/jre/lib:/ > usr/local/tools/Xilinx/lib:/usr/local/tools/Xilinx/chipscope/bin/lin:/usr/ > lib:/usr/local/lib:/usr/X11R6/lib:/usr/lib/xemacs:/usr/local/tools/ > jre1.5.0_10/lib > > echo $XILINX > /usr/local/tools/Xilinx > > Is there some missing variable that I need to set. This works for me PLATFORM = lin XILINX = /usr/local/bin/Xilinx91i NPX_PLUGIN_PATH = /usr/local/bin/Xilinx91i/java/lin/jre/plugin/i386/ ns4 LMC_HOME = /usr/local/bin/Xilinx91i/smartmodel/lin/installed_lin LD_LIBRARY_PATH = /usr/local/bin/Xilinx91i/bin/lin:/usr/X11R6/lib PATH = /usr/local/bin/Xilinx91i/bin/linArticle: 118010
We're talking about the picoblaze here....the program space isn't large enough for ANYTHING to take weeks to write.... if it takes more than two hours to run out of program memory, you type too slow! On Apr 14, 12:35 pm, fpga_t...@yahoo.com wrote: > On Apr 14, 7:17 am, n...@puntnl.niks (Nico Coesel) wrote: > > > Are you sure you want to use that compiler? Last time I checked it > > didn't seem very usefull (no optimisations at all). You're probably > > better of writing your program in assembly language. > > For nearly 30 years there have been various C compilers for small > micro's, ever since Ron Cain knocked off the Small-C compiler for the > 8080 with a little help from me (a free SRI International PDP-11 unix > account as long as the compiler was public domain). These compilers do > not need to be perfect, or even great, just correct, to quickly knock > off projects that would take weeks in assembler. For most, careful > coding will get your project 95% of the way toward good/excellent > performance, with a small amount of asm functions and tweeking at the > end to meet timing goals. > > For a tiny PB PLD project, it might not be practical ... for a larger > PB Spartan project, it might be the only quick prototyping choice that > makes sense, from early concept to production.Article: 118011
Hi, I am currently working with a large design with long synthesis and implementation times. The design is synthesized with Precision RTL and the gate-level netlist is exported manually to Quartus II by means of an EDIF file. I use a TCL script to automate implementation, mainly to automatically tweak a few parameters. I would like to modify my Quartus II implementation script to add a SignalTap II component on the *first* implementation pass, and I would also like to be able to assign which pins and buses I'd like to debug without having to deal with the GUI. I went through most of the documentation, and played with the GUI quite a bit, and could not manage to add the SignalTap II component without first implementing the entire design. I typically receive the "Compile the project to continue" message. Any and all advice is appreciated, thanks for your help! EdmondArticle: 118012
B. Joshua Rosen <bjrosen@polybuspleasedontspamme.com> wrote: > I've been trying to launch ISE (9.1SP3) and I get this error > FATAL_ERROR:Portability:Port_ExecLoaderInit.c:117:1.4 - The executable > </home/bjrosen/_pn> can't be found. The installation was not > complete. > Process will terminate. For more information on this error, please > consult > the Answers Database or open a WebCase with this project attached at > http://www.xilinx.com/support. > If I launch it from the $XILINX/bin/lin directory it works fine so it > would appear to be some sort of search path problem but I've got > everything in my paths, > echo $PATH > /usr/local/tools/Xilinx/bin/lin:/usr/local/tools/Xilinx/java/lin/jre/bin:/ > usr/local/tools/Xilinx/chipscope/bin/lin:/usr/local/tools/Xilinx/bin/ > lin64:.:/usr/local/tools/flexlm/bin:/usr/java/jre1.5.0_02/bin:/usr/local/ > tools/hdlmaker_lib/i686/bin:/usr/local/tools/hdlmaker_lib/csh:/usr/local/ > tools/jre1.5.0_10/bin:/usr/local/bin:/usr/bin:/sbin:/usr/sbin:/bin:/usr/ > X11R6/bin:/usr/local/csh:/usr/local/sbin:/usr/local/tools/acrobat/bin:/ > usr/local/tools/nc_sim/tools/bin > echo $LD_LIBRARY_PATH > /usr/local/tools/Xilinx/bin/lin:/usr/local/tools/Xilinx/java/lin/jre/lib:/ > usr/local/tools/Xilinx/lib:/usr/local/tools/Xilinx/chipscope/bin/lin:/usr/ > lib:/usr/local/lib:/usr/X11R6/lib:/usr/lib/xemacs:/usr/local/tools/ > jre1.5.0_10/lib > echo $XILINX > /usr/local/tools/Xilinx > Is there some missing variable that I need to set. I have following script in my nin directory: #!/bin/bash WEBROOT=/opt/web91 sh $WEBROOT/settings.sh $WEBROOT/bin/lin/ise And for impact: #!/bin/bash WEBROOT=/opt/web82 sh $WEBROOT/settings.sh LD_PRELOAD=/usr/local/lib/libusb-driver.so $WEBROOT/bin/lin/impact $@ The LD-PRELOAD is to get rid of this dammed windriver. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 118013
"LilacSkin" <lpaulo07@iseb.fr> wrote in message
news:1176723117.112802.254540@e65g2000hsc.googlegroups.com...
On 16 avr, 11:45, "Ben Jones" <ben.jo...@xilinx.com> wrote:
> There is something i don't really understand:
> if I want to send data from an IP to my SOPC (in a BRAM), I need to
> make a MASTER IPIF which transfer the data to the BRAM.
> In the MASTER (PLB) IPIF, it takes the data and the address from my IP
> TEST with the ports Bus2IP and sends it to the BRAM with the ports
> IP2Bus.
> What is the aim of the IP2IP port ?
> When I want to send data to my BRAM, I send the address of the MASTER
> IPIF or of the BRAM ???
I'm not sure I understood any of that...
If you want to design a piece of IP that attaches to the rest of your system
via a Coreconnect bus like PLB or OPB, then you have some options - it can
be a bus slave, a bus master, or both. In fact, it might even have a master
interface on one bus and a slave interface on another.
The IPIF is supposed to make it easier for you to interface your IP to the
Coreconnect bus, but you do not have to use it if you don't want to.
If your IP is a bus master only, then it will be able to initiate its own
transactions, but it will be inaccessible from the rest of the system. If it
is a bus slave only, then it will be readable and writable from somewhere
else (like your processor), but unable to initiate transactions. If it's
both a master and a slave, then it has all these capabilities.
The piece of code you posted seemed to be targetting a piece of IP with both
a master and a slave interface. My understanding of it was that the
processor would write some command registers to this IP, telling it what
data to write and where to write it. Then when the IP is told to "go", it
will perform its transaction on the PLB. In that case, you need to know
where the IP's slave interface is mapped in memory, so that the processor
can talk to it. It looks like XPAR_IPIF_MASTER_0_BASEADDR should be that
address, but perhaps it is not. Sometimes when using the IPIF you need to
access the peripherals "address range 0" base address instead - check to see
what definitions are present in your xparameters.h file.
Of course, a piece of IP like this is of no immediate practical use, because
it would be just as easy for the processor to perform the transaction itself
instead of going through this proxy. However, it's a useful exercise for
getting to grips with the Coreconnect system and debugging your IP.
You might also find it useful to attach a chipscope analyser to the PLB
signals and watch what happens when your software runs.
Good luck,
-Ben-
Article: 118014On 2007-04-16, Georg Acher <acher@in.tum.de> wrote: > Try playing with the -t parameter for map and par. Officially it's called > "cost table" but I think it's just a seed for the random number generator. There > are occasions where par simply won't meet the constraints in 40min, but with > another -t-value it's done in 7min... The difference between meeting timing easily and not meeting timing at all is a fine edge. A couple of months ago I did some experiments on this and placed the results at http://www.da.isy.liu.se/~ehliar/stuff/place_and_route.html This design easily meets timing at one point but if the constraint is tightened by .1ns the runtime increases sharply without meeting timing at all. Hmm, I guess it might be interesting to rerun this script with different -t parameters. It would also be interesting to try different ISE versions and different options to map/par. /AndreasArticle: 118015
Hi, I intend to wire up an Altera Cyclone 2 to a NET2272 USB controller. The bus of the NET2272 is similar to that of a parallel RAM, with address lines, bidirectional data bus, and read/write strobe signals. I'm concerned about the electrical safety of the bidirectional data lines. If I mess up the FPGA program and assert the read strobe signal while the data lines are set as outputs, this may damage (expensive) parts, right ? Do you know of a simple way to avoid this ? Putting resistors in series on the data lines ? Regards, SebastienArticle: 118016
lokesh schrieb: > could you please explain wht is to be coded in combinatorial and wht to be coded in sequential. am bit confused And I am confused about such a question. What is the source of your confusion? Do you know anything about digital cells? A problem can be solved with combinational logic, if the solution depends only on the values of some input signals. In other words: If the solution can be computed in one step, it can be done with combinational logic. A problem has to be solved with sequential logic if storage elements are needed. In other words: If the solution has to be computed in more than one step, if must be done with sequential logic. Storage elements are latches, flipflops, RAM. process(reset,clk) begin if (reset='0') then accumulator<=(others=>'0'); elsif rising_edge(clk) then accumulator<=accumulator + sum; -- sequential end if; end process; -- accumulator is a storage element (flipflops) sum<=a + b; -- combinational RalfArticle: 118017
On 16 avr, 14:50, "Ben Jones" <ben.jo...@xilinx.com> wrote: > "LilacSkin" <lpaul...@iseb.fr> wrote in message > > news:1176723117.112802.254540@e65g2000hsc.googlegroups.com... > On 16 avr, 11:45, "Ben Jones" <ben.jo...@xilinx.com> wrote: > > > There is something i don't really understand: > > if I want to send data from an IP to my SOPC (in a BRAM), I need to > > make a MASTER IPIF which transfer the data to the BRAM. > > In the MASTER (PLB) IPIF, it takes the data and the address from my IP > > TEST with the ports Bus2IP and sends it to the BRAM with the ports > > IP2Bus. > > What is the aim of the IP2IP port ? > > When I want to send data to my BRAM, I send the address of the MASTER > > IPIF or of the BRAM ??? > > I'm not sure I understood any of that... > > If you want to design a piece of IP that attaches to the rest of your system > via a Coreconnect bus like PLB or OPB, then you have some options - it can > be a bus slave, a bus master, or both. In fact, it might even have a master > interface on one bus and a slave interface on another. > > The IPIF is supposed to make it easier for you to interface your IP to the > Coreconnect bus, but you do not have to use it if you don't want to. > > If your IP is a bus master only, then it will be able to initiate its own > transactions, but it will be inaccessible from the rest of the system. If it > is a bus slave only, then it will be readable and writable from somewhere > else (like your processor), but unable to initiate transactions. If it's > both a master and a slave, then it has all these capabilities. > > The piece of code you posted seemed to be targetting a piece of IP with both > a master and a slave interface. My understanding of it was that the > processor would write some command registers to this IP, telling it what > data to write and where to write it. Then when the IP is told to "go", it > will perform its transaction on the PLB. In that case, you need to know > where the IP's slave interface is mapped in memory, so that the processor > can talk to it. It looks like XPAR_IPIF_MASTER_0_BASEADDR should be that > address, but perhaps it is not. Sometimes when using the IPIF you need to > access the peripherals "address range 0" base address instead - check to see > what definitions are present in your xparameters.h file. > > Of course, a piece of IP like this is of no immediate practical use, because > it would be just as easy for the processor to perform the transaction itself > instead of going through this proxy. However, it's a useful exercise for > getting to grips with the Coreconnect system and debugging your IP. > > You might also find it useful to attach a chipscope analyser to the PLB > signals and watch what happens when your software runs. > > Good luck, > > -Ben- thank you for your fast answer and your kindness, what i "just" want to do is access to a BRAM plugged to the PLB with an "external" IP, that why i want to build a MASTER PLB IPIF. i beging to understand how that system works thanks to the Xilinx sample but i have a problem with the address.Article: 118018
On Apr 15, 12:33 pm, rohit20...@yahoo.com wrote: > Hi, > > I was wondering how the number 166Mhz for DDR came up? Why not say... > 200MHz/250MHz DDR? I am sure there is some thought process behind > that, could someone help me walk through? > > Thanks in advance ! > -Rohit Perhaps this number is how slow one can go, not how fast? If you're not meeting timing with your FPGA, the low frequency number could be important. DDR does have a minimum frequency... G.Article: 118019
On Apr 14, 1:20 pm, "Daniel S." <digitalmastrmind_no_s...@hotmail.com> wrote: > Mike Treseler wrote: > > Daniel S. wrote: > > >> Since not all synthesis and simulation tools agree on how to deal with > >> variables in synthesizable code, some weird bugs can come up so it is > >> generally better to use signals which more closely (less ambiguously) > >> represents how synchronous hardware works. > > > Here are my examples of designs using variables exclusively: > >http://home.comcast.net/~mike_treseler/ > > These examples have been tested on almost all the the > > FPGA synthesis tools, and these agree > > perfectly on how to deal with variables. > > Modelsim also agrees. > > Do you have a single example to support > > your assertion above? > > I do not use variables in my designs, none of the people I have worked with > and none of the projects I have worked on so far used variables in > synthesizable code either. > > Variables for synthesis might work but none of the people I have ever > worked with ever recommended it and many have reported problems of one sort > or another with that - variables used to be testbench-only after all. This > was years ago but the general mindset for the major projects I have worked > on is to never use a feature that once proved to cause unnecessary > simulation or synthesis problems... at the very least not until many tool > revisions after the last known related bugs had been fixed - researcher > hate hunting down tool bugs and ASIC people hate bumping tape-outs due to > last minute bugs or scrapping masks/wafers because third-party tool bugs > related to some new feature were found a little too late. > > Even if variables have been fully supported by all simulation and synthesis > tools for the last couple of years, it does not reduce their potential for > inducing unnecessary confusion - newbies already get confused enough with > simple HDL-based RTL design as it is and I cannot think of any good reason > (other than academic) to use variables instead of signals for synthesis. > > IMO, variables for synthesis are a mostly unnecessary and potentially > confusing convenience. Daniel, Variables provide locality of reference (signals are NOT declarable at the process level). Variable assignments and references work just like they read, unlike signals. Variable assignments allow complex expressions to be simplified instead of repeated. Variables work. Period. The synthesis tool creates a circuit that behaves, on a clock cycle basis, in the same manner as the RTL description behaves, whether you use signals or variables. I prefer a style that makes the behavioral aspect more clear, perhaps even at the expense of the structural aspect. In 17+ years of vhdl use, I've had far more bugs that were caused by behavioral problems than structural ones. Besides, when you turn on pipelining and retiming optimizations, all your carefully constructed distribution of gates between registers goes right out the window. And then you don't even have a good behavioral description to fall back on. I heard the similar arguments for separate combinatorial and clocked processes for years too: you need to be able to see the gates and registers. Why use an HDL to write a netlist? That said, there are times when the structure is critical to the function (synchronization boundaries, for example). These are the times when I fall back on more explicit structural coding styles, if for no other reason than to better support code reviews. AndyArticle: 118020
On Mon, 16 Apr 2007 05:39:49 -0700, g.eckersley wrote: > On Apr 16, 8:54 am, "B. Joshua Rosen" > <bjro...@polybusPleaseDontSpamMe.com> wrote: >> I've been trying to launch ISE (9.1SP3) and I get this error >> >> FATAL_ERROR:Portability:Port_ExecLoaderInit.c:117:1.4 - The executable >> </home/bjrosen/_pn> can't be found. The installation was not >> complete. >> Process will terminate. For more information on this error, please >> consult >> the Answers Database or open a WebCase with this project attached at >> http://www.xilinx.com/support. >> >> If I launch it from the $XILINX/bin/lin directory it works fine so it >> would appear to be some sort of search path problem but I've got >> everything in my paths, >> >> echo $PATH >> /usr/local/tools/Xilinx/bin/lin:/usr/local/tools/Xilinx/java/lin/jre/ bin:/ >> usr/local/tools/Xilinx/chipscope/bin/lin:/usr/local/tools/Xilinx/bin/ >> lin64:.:/usr/local/tools/flexlm/bin:/usr/java/jre1.5.0_02/bin:/usr/ local/ >> tools/hdlmaker_lib/i686/bin:/usr/local/tools/hdlmaker_lib/csh:/usr/ local/ >> tools/jre1.5.0_10/bin:/usr/local/bin:/usr/bin:/sbin:/usr/sbin:/bin:/ usr/ >> X11R6/bin:/usr/local/csh:/usr/local/sbin:/usr/local/tools/acrobat/bin:/ >> usr/local/tools/nc_sim/tools/bin >> >> echo $LD_LIBRARY_PATH >> /usr/local/tools/Xilinx/bin/lin:/usr/local/tools/Xilinx/java/lin/jre/ lib:/ >> usr/local/tools/Xilinx/lib:/usr/local/tools/Xilinx/chipscope/bin/lin:/ usr/ >> lib:/usr/local/lib:/usr/X11R6/lib:/usr/lib/xemacs:/usr/local/tools/ >> jre1.5.0_10/lib >> >> echo $XILINX >> /usr/local/tools/Xilinx >> >> Is there some missing variable that I need to set. > > This works for me > > PLATFORM = lin > XILINX = /usr/local/bin/Xilinx91i > NPX_PLUGIN_PATH = /usr/local/bin/Xilinx91i/java/lin/jre/plugin/i386/ ns4 > LMC_HOME = /usr/local/bin/Xilinx91i/smartmodel/lin/installed_lin > LD_LIBRARY_PATH = /usr/local/bin/Xilinx91i/bin/lin:/usr/X11R6/lib PATH = > /usr/local/bin/Xilinx91i/bin/lin I have all of that, which distro are you using?Article: 118021
> So what the f**k are you talking about? > > Kolja Sulimma Pleasant! Errr. but I dont completely agree. DDR200 = PC1600 = 100MHz ... http://h20000.www2.hp.com/bc/docs/support/SupportManual/c00256987/c00256987.pdf Has a bit more detail which may give the OP some information about why 166MHz was chosen... just a stepping stone really. BenArticle: 118022
Ah! I'm pleased you got it sorted. A colleague of mine had a very similar issue due to the voltage levels of parallel ports being different from one machine to another.. 3.3 versus 5.0 or so - it was going to be my next suggestion to try a different computer. Ben "BERT" <callmevc@gmail.com> wrote in message news:1176476875.675325.13520@w1g2000hsg.googlegroups.com... > On Apr 13, 10:46 am, "Benjamin Todd" > <benjamin.toddREMOVEALLCAPIT...@cernREMOVEALLCAPITALS.ch> wrote: >> you can get that if there's something stuck at one. >> Check the cables! >> Ben"BERT" <callm...@gmail.com> wrote in message >> >> news:1176475217.521694.315060@n76g2000hsh.googlegroups.com... >> >> > Hi, >> >> > I need some help with my Altera Dev Kit (STRATIX DSP S80 Development >> > Board Rev 1.2). I no longer seem to be able to program my device. It >> > was working properly until I started getting the following error: >> >> > "Error: Can't configure device. Expected JTAG ID code 0x20070DD for >> > device 1, but found JTAG ID code 0xFFFFFFFF." >> >> > Also, when I use the "Auto Detect" feature of Quartus II Programmer, >> > I get >> > "EPS180/_HARDCOPY_FPGA_PROTOTYPE" instead of the actual device name >> > EP1S80B9C656. >> >> > Does this mean that my development kit is toast, or am I missing >> > something here ? Has anyone seen such an error before ?I would greatly >> > appreciate any help !! >> >> > I am using Altera ByteBlaster II programming cable. Replacing the >> > cable with a new one doesn't help either. >> >> > Thanks, >> > Vijay. > > > Thanks for your help ! I moved to a different computer and now I am > able to program the device, and everything works properly. Very > strange ... My previous computer was a 10-15 year old laptop, and the > parallel-port is probably not working properly. >Article: 118023
Andreas Ehliar <ehliar@lysator.liu.se> writes:
>On 2007-04-16, Georg Acher <acher@in.tum.de> wrote:
>> Try playing with the -t parameter for map and par. Officially it's called
>> "cost table" but I think it's just a seed for the random number generator. There
>> are occasions where par simply won't meet the constraints in 40min, but with
>> another -t-value it's done in 7min...
>
>The difference between meeting timing easily and not meeting timing at all
>is a fine edge. A couple of months ago I did some experiments on this and
>placed the results at http://www.da.isy.liu.se/~ehliar/stuff/place_and_route.html
>This design easily meets timing at one point but if the constraint is tightened
>by .1ns the runtime increases sharply without meeting timing at all.
And then there is usually more than one constraint that isn't met. Otherwise it
would be too easy to find out *the* critical path ;-)
>Hmm, I guess it might be interesting to rerun this script with different -t
>parameters. It would also be interesting to try different ISE versions and
>different options to map/par.
I'm currently working on a design with an (until now) 30% used 3S1600E, but tight
constraints. In most of the runs par is finished in 4 to 6mins. But there were
also runs with 30min with and without success. Exactly the same input design with
a different -t gives the fast runtimes again.
Maybe this randomness goes away when doing "real" floorplanning, at least it
gets worse with no floorplanning at all.
I have an older design with an 95% used 2S200E which actually needs -t, because
only 1 of 20 routings meets the timing... But at least you can do a batch
lottery :-)
--
Georg Acher, acher@in.tum.de
http://www.lrr.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 118024
Hello,
I read about Matlab/Simulink HDL code and did simple test with it. I
couldn't understand what the meaning of ports to the generated code is and I
couldn't find any sample timing for them. Is there any such detail
information available? I want to use the generated code with ISE is there
any information on how I can use the generated code and test-benches with
ISE?
Best regards
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z