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Hi Can we know actual DIE size ? For example, V2P100-ff1704 As far as I find, data book does not contain the information. I need chip (that we see in the FPGA EDITOR) size -:. Can anyone help me? Should I ask Xilinx?Article: 118376
"Bryan" <sfoo@xilinx.com> writes: > Hi all, thanks to your help, I have managed to solve the JTAG problem on my > XTREME DSP Development Kit. > Great news - what did you do to fix it? > However I had a response which attenuates all frequencies even though my > design is low pass filter.. Anybody can help me with that because i checked > through my design n it seems fine. It is a MAC based FIR 43 tap filter > though. > One thing immediately springs to mind - does the simulation do the same thing as the real hardware? Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 118377
Hi Matthew,
Matthew Hicks <mdhicks2@uiuc.edu> writes:
> I'm working on a RTOS for the PowerPC chip on the Virtex-II XUP board.
> I need an interrupt to trigger so I run my scheduler at regular
> intervals, so I setup the PIT to trigger an interrupt at 1s (purely
> for testing reasons, I will be going down to around 5ms). The program
> seems to pause when I finally enable the interrupt and I see no signs
> that the handler has been run. I looked at several references and
> spent a day shifting around my code, to no avail. If someone could
> take a peek at my code below and offer assistance that would be great.
> Thanks.
>
>
> #include "xparameters.h"
> #include "stdio.h"
> #include "xbasic_types.h"
> #include "gpio_header.h"
> #include "xexception_l.h"
> #include "xtime_l.h"
>
> Xuint32 status;
I don't know about the rest of the code, but this declaration needs to
be volatile...
volatile Xuint32 status;
<snip>
> status = 0;
> while(status != 55)
> {
> ;
> }
Otherwise the compiler optimises this to an infinite loop because it
"knows" that nothing can make status == 55
Cheers,
Martin
--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
Article: 118378(This is my third attempt to send the same post to the group. The previous two posts still have not appeared on the group.) Hi I have been trying to use the OPB PCI bridge in EDK 8.2. So far I have not been able to synthesize it properly. I am using a custom board with Virtex II, I include the PCI bridge during the BSB wizard. Is the assembly view, I configure the IP to be used as a target. My first milestone is to put PCI target on an FPGA board withe the PCI edge connector, put it in a PC and the PC should detect the PCI board. I need to have the PCI target to be configured from the PC side. Now my questions are: 1. When I set all the configurations for the PCI to be used as a target, why dont I see the IDSEL line in my ucf file? 2. In the generated ucf, I see two clocks with the name PCI_CLK_FB and PCI_CLK_OUT. After digging, I came to know that these clocks make more sense when the PCI bridge is to be used as a host (on a mothernboard as is used in ML310 board) where PCI_CLK_OUT is the source PCI clock and PCI_CLK_FB is the feedback clock. AFter consulting some more MHS files from the reference designs, I do see the PCLK appearing in the ucf and MHS file (instead of PCI_CLK_FB and PCI_CLK_OUT clocks). When I set the PCI bridge as a target (by setting C_INCLUDE_OPB_MST2PCI_TARG = 0), I dont see any IDSEL line appearing in my ucf, why is that so? 3. Synthesizing the project as it is, without the IDSEL line available at the ports, I start getting NgdBuild errors on ilmb_BE line to be driven by mulitple sources. I am pasting the MHS file. Kindly guide how to achieve the first milestone. Farhan # ############################################################################## # Created by Base System Builder Wizard for Xilinx EDK 8.2.02 Build EDK_Im_Sp2.4 # Tue Apr 24 17:00:33 2007 # Target Board: Custom # Family: virtex2 # Device: xc2v1000 # Package: fg456 # Speed Grade: -4 # Processor: Microblaze # System clock frequency: 40.000000 MHz # Debug interface: On-Chip HW Debug Module # On Chip Memory : 8 KB # ############################################################################## PARAMETER VERSION = 2.1.0 PORT fpga_0_PCI_Bridge_PAR = fpga_0_PCI_Bridge_PAR, DIR = IO PORT fpga_0_PCI_Bridge_PERR_N = fpga_0_PCI_Bridge_PERR_N, DIR = IO PORT fpga_0_PCI_Bridge_SERR_N = fpga_0_PCI_Bridge_SERR_N, DIR = IO PORT fpga_0_PCI_Bridge_IRDY_N = fpga_0_PCI_Bridge_IRDY_N, DIR = IO PORT fpga_0_PCI_Bridge_FRAME_N = fpga_0_PCI_Bridge_FRAME_N, DIR = IO PORT fpga_0_PCI_Bridge_DEVSEL_N = fpga_0_PCI_Bridge_DEVSEL_N, DIR = IO PORT fpga_0_PCI_Bridge_STOP_N = fpga_0_PCI_Bridge_STOP_N, DIR = IO PORT fpga_0_PCI_Bridge_TRDY_N = fpga_0_PCI_Bridge_TRDY_N, DIR = IO PORT fpga_0_PCI_Bridge_AD = fpga_0_PCI_Bridge_AD, DIR = IO, VEC = [31:0] PORT fpga_0_PCI_Bridge_CBE = fpga_0_PCI_Bridge_CBE, DIR = IO, VEC = [3:0] PORT fpga_0_PCI_CLK_FB = pci_feedback_s, DIR = I, SIGIS = CLK PORT fpga_0_PCI_CLK_OUT = pci_clk_s, DIR = O PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 40000000 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST BEGIN microblaze PARAMETER INSTANCE = microblaze_0 PARAMETER HW_VER = 5.00.c PARAMETER C_USE_FPU = 0 PARAMETER C_DEBUG_ENABLED = 1 PARAMETER C_NUMBER_OF_PC_BRK = 2 BUS_INTERFACE DLMB = dlmb BUS_INTERFACE ILMB = ilmb BUS_INTERFACE DOPB = mb_opb BUS_INTERFACE IOPB = mb_opb PORT DBG_CAPTURE = DBG_CAPTURE_s PORT DBG_CLK = DBG_CLK_s PORT DBG_REG_EN = DBG_REG_EN_s PORT DBG_TDI = DBG_TDI_s PORT DBG_TDO = DBG_TDO_s PORT DBG_UPDATE = DBG_UPDATE_s END BEGIN opb_v20 PARAMETER INSTANCE = mb_opb PARAMETER HW_VER = 1.10.c PARAMETER C_EXT_RESET_HIGH = 1 PORT SYS_Rst = sys_rst_s PORT OPB_Clk = sys_clk_s END BEGIN opb_mdm PARAMETER INSTANCE = debug_module PARAMETER HW_VER = 2.00.a PARAMETER C_MB_DBG_PORTS = 1 PARAMETER C_USE_UART = 1 PARAMETER C_UART_WIDTH = 8 PARAMETER C_BASEADDR = 0x41400000 PARAMETER C_HIGHADDR = 0x4140ffff BUS_INTERFACE SOPB = mb_opb PORT DBG_CAPTURE_0 = DBG_CAPTURE_s PORT DBG_CLK_0 = DBG_CLK_s PORT DBG_REG_EN_0 = DBG_REG_EN_s PORT DBG_TDI_0 = DBG_TDI_s PORT DBG_TDO_0 = DBG_TDO_s PORT DBG_UPDATE_0 = DBG_UPDATE_s END BEGIN lmb_v10 PARAMETER INSTANCE = ilmb PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 1 PORT SYS_Rst = sys_rst_s PORT LMB_Clk = sys_clk_s END BEGIN lmb_v10 PARAMETER INSTANCE = dlmb PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 1 PORT SYS_Rst = sys_rst_s PORT LMB_Clk = sys_clk_s END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = dlmb_cntlr PARAMETER HW_VER = 2.00.a PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00001fff BUS_INTERFACE SLMB = dlmb BUS_INTERFACE BRAM_PORT = dlmb_port END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = ilmb_cntlr PARAMETER HW_VER = 2.00.a PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00001fff BUS_INTERFACE SLMB = ilmb BUS_INTERFACE BRAM_PORT = ilmb_port END BEGIN bram_block PARAMETER INSTANCE = lmb_bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = ilmb_port BUS_INTERFACE PORTB = dlmb_port END BEGIN opb_pci PARAMETER INSTANCE = PCI_Bridge PARAMETER HW_VER = 1.02.a PARAMETER C_DMA_CHAN_TYPE = 0 PARAMETER C_INCLUDE_INTR_MODULE = 0 PARAMETER C_PCIBAR_NUM = 2 PARAMETER C_TRIG_PCI_READ_OCC_LEVEL = 8 PARAMETER C_TRIG_IPIF_WRBURST_OCC_LEVEL = 8 PARAMETER C_TRIG_PCI_DATA_XFER_OCC_LEVEL = 8 PARAMETER C_INHIBIT_IPIF_READ_VAC_LEVEL = 8 PARAMETER C_TRIG_IPIF_READ_OCC_LEVEL = 8 PARAMETER C_NUM_PCI_RETRIES_IN_WRITES = 15 PARAMETER C_NUM_PCI_PRDS_BETWN_RETRIES_IN_WRITES = 15 PARAMETER C_MAX_LAT = 0x54 PARAMETER C_MIN_GNT = 0x32 PARAMETER C_NUM_IDSEL = 1 PARAMETER C_DMA_LENGTH_WIDTH = 11 PARAMETER C_INCLUDE_DEV_PENCODER = 0 PARAMETER C_DEV_MIR_ENABLE = 0 PARAMETER C_DEV_BLK_ID = 6 PARAMETER C_INCLUDE_INTR_A_BUF = 1 PARAMETER C_INCLUDE_REQ_N_BUF = 1 PARAMETER C_IPIFBAR_NUM = 1 PARAMETER C_IPIFBAR2PCIBAR_1 = 0x00000000 PARAMETER C_IPIF_SPACETYPE_1 = 0 PARAMETER C_IPIFBAR2PCIBAR_0 = 0x20000000 PARAMETER C_IPIFBAR_0 = 0x20000000 PARAMETER C_IPIF_HIGHADDR_0 = 0x3fffffff PARAMETER C_IPIFBAR_1 = 0xe8000000 PARAMETER C_IPIF_HIGHADDR_1 = 0xebffffff PARAMETER C_BASEADDR = 0x42600000 PARAMETER C_HIGHADDR = 0x4260ffff PARAMETER C_DMA_BASEADDR = 0x42800000 PARAMETER C_DMA_HIGHADDR = 0x4280ffff PARAMETER C_INCLUDE_OPB_MST2PCI_TARG = 0 PARAMETER C_INCLUDE_PCI_CONFIG = 0 PARAMETER C_DEVICE_ID = 0x1004 PARAMETER C_VENDOR_ID = 0x1004 PARAMETER C_CLASS_CODE = 0x050000 PARAMETER C_REV_ID = 0x01 PARAMETER C_SUBSYSTEM_ID = 0xDCBA PARAMETER C_SUBSYSTEM_VENDOR_ID = 0x9876 PARAMETER C_INCLUDE_DEV_ISC = 0 PARAMETER C_INCLUDE_ERR_REG_MODULE = 0 PARAMETER C_IPIF2PCI_FIFO_ABUS_WIDTH = 6 PARAMETER C_PCI2IPIF_FIFO_ABUS_WIDTH = 6 BUS_INTERFACE MSOPB = mb_opb PORT PAR = fpga_0_PCI_Bridge_PAR PORT PERR_N = fpga_0_PCI_Bridge_PERR_N PORT SERR_N = fpga_0_PCI_Bridge_SERR_N PORT IRDY_N = fpga_0_PCI_Bridge_IRDY_N PORT FRAME_N = fpga_0_PCI_Bridge_FRAME_N PORT DEVSEL_N = fpga_0_PCI_Bridge_DEVSEL_N PORT STOP_N = fpga_0_PCI_Bridge_STOP_N PORT TRDY_N = fpga_0_PCI_Bridge_TRDY_N PORT AD = fpga_0_PCI_Bridge_AD PORT CBE = fpga_0_PCI_Bridge_CBE PORT PCLK = pci_feedback_s PORT RST_N = sys_rst_s END BEGIN dcm_module PARAMETER INSTANCE = dcm_0 PARAMETER HW_VER = 1.00.a PARAMETER C_CLK0_BUF = TRUE PARAMETER C_CLKFX_BUF = TRUE PARAMETER C_CLKFX_DIVIDE = 6 PARAMETER C_CLKFX_MULTIPLY = 5 PARAMETER C_CLKIN_PERIOD = 25.000000 PARAMETER C_CLK_FEEDBACK = 1X PARAMETER C_DFS_FREQUENCY_MODE = LOW PARAMETER C_DLL_FREQUENCY_MODE = LOW PARAMETER C_EXT_RESET_HIGH = 1 PORT CLKIN = dcm_clk_s PORT CLK0 = sys_clk_s PORT CLKFX = pci_clk_s PORT CLKFB = sys_clk_s PORT RST = net_gnd PORT LOCKED = dcm_0_lock ENDArticle: 118379
Hi, I am almost new in google gruops. I build IPIF master to control OPB DDR SDRAM controller. Using Create/Import Peripheral, I could make a IPIF master. In the folder of IPIF master, there was a example code named "user_logic." And "user_logic" has several ports, I can understand most of them. But I am not sure these 2 ports, "IP2IP_addr", "IP2BUS_addr." As long as I know, IP2IP_addr is used to choose slave that I will access. Then, how can I know address of each slave address? Can you anyone explain difference btw 2 ports? Thank you for reading!Article: 118380
Hi, I have a project with a big requeriment of memory. So I have decided to generate a linker script with every section to SDRAM. The problem is that I don't know how can I increase the "default memory area" for my app. The reason is that I do "xil_calloc", but when I put a big number I receive an error and I think I could do it in a Sdram with 32Mb. How can I increase the resources of my Sdram?. What is the section in "Linker Script" for doing it possible?. ThanksArticle: 118381
"Pablo" <pbantunez@gmail.com> wrote in message
news:1177502351.601731.113970@u32g2000prd.googlegroups.com...
> Hi, I have a project with a big requeriment of memory. So I have
> decided to generate a linker script with every section to SDRAM. The
> problem is that I don't know how can I increase the "default memory
> area" for my app. The reason is that I do "xil_calloc", but when I put
> a big number I receive an error and I think I could do it in a Sdram
> with 32Mb. How can I increase the resources of my Sdram?. What is the
> section in "Linker Script" for doing it possible?.
Erm, increase the heap size?
-Ben-
Article: 118382"Martin Thompson" <martin.j.thompson@trw.com> wrote in message news:ud51s4zen.fsf@trw.com... > Nicolas Matringe <nicolas.matringe@fre.fre> writes: > >> wallge a écrit : >>> I don't know about ultraedit, >>> >>> but emacs VHDL mode does a wonderful job colorizing and >>> beautifying source code. >>> I use it exclusively... It also has a nice hierarchy browser and >>> lots of other VHDL specific functionality built in. >>> >>> There are some nice cheat sheets available through >>> a google search that have all the important keyboard shortcuts >>> as well... >> >> The problem with emacs is that all its shortcuts are rather alien to >> most Windows users. I have stopped trying to convince my colleagues to >> use it. >> > > There is now a "pretty" Windows installer and configurator for Emacs > which makes it much more straightforward for traditional windows users > to have a go. It sets up lots of the stuff that is unfamiliar to > Windowsers to be more familiar, so CUA keys work, F1 for help etc. > They'll still feel the slashes are all the wrong way around, but I > don't think that'll ever get into Emacs :-) > > http://www.ourcomments.org/Emacs/EmacsW32.html > > Cheers, > Martin > > -- > martin.j.thompson@trw.com > TRW Conekt - Consultancy in Engineering, Knowledge and Technology > http://www.conekt.net/electronics.html Thanks. I am giving Emacs a try. How can I setup Xilinx ISE to use emacs? RegardsArticle: 118383
Ken Soon wrote: >>> Oh btw I have then tried to add on more register levels. >>> Have tried some structures, and I deduce this coding should be logical. >>> Wonder if there is anything wrong. The lowest I have brought the timing >>> down >>> is a slack of about 1ns >> There are limits to how many registers XST is able to move around when >> using automatic pipelining and it appears to vary from two to four >> depending on constructs and tool versions. > > Yeh Well thanks alot in all for your help. > If not for your help, I wouldn't have make so much progress and most of all, > know more about some FPGA. > Hmm, anyway, currently for my project, I guess pretty stuck already and am > not able to lower the timing delay any further. Maybe > because probably no one knows exactly whether it is possible to port the > design from a Virtex to a Spartan. Maybe it can, maybe it just cannot be > done. Since your only problem here appears to be coming slightly short on BRAMs for a direct re-implementation, going one step up in FPGA size would solve your problem. > Hmm more ways I could progress further on about this would be (maybe) to > find out more on the sequential tables and coefficients tables and whether I > could do something about the wrapper and find out more about this wrapper. > Or I could use the DDR SDRAM (shudders...) If there are large duplicated constant tables stored in a BRAM that get initialized by software, you could make them into a dual-port ROM by putting the constants in the BRAM's INIT. Actually, the write functionality could be preserved too as long as the writes are made synchronous to either read clock. > Lastly, another problem would be the IO ports and how to actually implement > this scaler in practical sense. > > Anyway appreciate your help so far. Many thanks! You're welcome.Article: 118384
Hello! I am using a board with Virtex4 PPC405, external asynchronous SRAM memory and EDK 8.2i. If application program resides in BRAM and I want to write and read from SRAM, it is only possible if there is instruction and data cache enebled and I add XCache_EnableCache in the beginning of the code. So far it works. Then I tried to run application from SRAM. So I generated linker script telling that the program should be in SRAM. After I launched XMD and entered dow executable.elf run it didn't work. When I tried to read downloaded code by mrd command from SRAM, it showed zero values. Furthermore, I tried to explicitly write a value to SRAM with mwr command and read it afterwards, it showed zero value again. So I thought the problem is that cache is still not enabled (because code is not running and XCache_EnableCache function was not executed). Then I set in XMD debug options "Set XMD memory map for PPC405 features" where it is possible to enable caches, but it didn't help. Parameter C_INCLUDE_BURST_CACHELN_SUPPORT in .mhs file is set to 1. Does anybody have any suggestions what it could be? Thanks in advance! Best regards RomanArticle: 118385
Hello, my question is the following: I have created an application created in SDRAM in which I do "xil_malloc(16*4096)". The problem is that it seems like there is not memory sufficient for my application. I have increased "HEAP_SIZE" and "STACK_SIZE" but I suppose that these parameters are not the problem. My sdram is 32Mb so I think I have enough memory for this requeriments. What can I do? How can I increase the memory for an app?. I use Xilkernel. Thanks for your helpArticle: 118386
hallo, people,
I am a beginner on Xilkernel running on PPC405-Virtex 4.
I just want to get interrupt generated from the OPB peripheral and the
have the interrupt handler routine serviced. It seems there is a bug I
can not find. The Xilkernel has no interaction with the interrupt
handler routine. I have taken the example project from Xilinx website,
which generates a periodic interrupts from a timer. The piece of codes
is as following:
#include "xmk.h"
#include <os_config.h>
#include <stdio.h>
#include <xparameters.h>
#include <xtmrctr_l.h>
#include <xstatus.h>
#include <pthread.h>
#include <semaphore.h>
#include <sys/intr.h>
#define TIMER_COUNTER_ID 0
volatile unsigned int mins, hrs, secs, tot_secs = 0;
unsigned int addr=XPAR_TIMER_2_BASEADDR;
int_id_t intTimerID = XPAR_INTC_TIMER_2_INTERRUPT_INTR;
void interval_timer_initialize ()
{
print ("CLOCK: Configuring extra timer to generate one interrupt
per second..\r\n");
XTmrCtr_mWriteReg (addr, TIMER_COUNTER_ID,
XTC_TLR_OFFSET, SYSTMR_CLK_FREQ);
// reset the timers, and clear interrupts
XTmrCtr_mSetControlStatusReg (addr, TIMER_COUNTER_ID,
XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK );
// start the timer
XTmrCtr_mSetControlStatusReg (addr, 0,
XTC_CSR_ENABLE_TMR_MASK |
XTC_CSR_ENABLE_INT_MASK |
XTC_CSR_AUTO_RELOAD_MASK |
XTC_CSR_DOWN_COUNT_MASK );
}
void extra_timer_int_handler ()
{
unsigned int control_reg;
control_reg = XTimerCtr_mReadReg (addr, TIMER_COUNTER_ID,
XTC_TCSR_OFFSET);
XTmrCtr_mWriteReg (addr, TIMER_COUNTER_ID,
XTC_TCSR_OFFSET,
XTC_CSR_LOAD_MASK | XTC_CSR_INT_OCCURED_MASK);
// remove the reset condition such that the timer counter starts
running
// with the value loaded from the compare register
XTmrCtr_mWriteReg (addr, TIMER_COUNTER_ID,
XTC_TCSR_OFFSET,
control_reg | XTC_CSR_ENABLE_TMR_MASK);
}
void* my_main (void *arg)
{
int a = 0;
XStatus status;
if ((status = register_int_handler(intTimerID,
extra_timer_int_handler, NULL)) != XST_SUCCESS) {
xil_printf ("CLOCK: Unable to register handler. Error code: %d.\r\n",
status);
goto err;
}
else print ("CLOCK: Successfully registered a handler for extra
timer interrupts.\r\n");
interval_timer_initialize ();
print ("CLOCK: Enabling the interval timer interrupt...\r\n");
enable_interrupt (intTimerID);
while (1) {
}
err:
xil_printf ("CLOCK: Clock functions unavailable...\r\n");
return NULL;
}
int main(){
xil_printf("main\r\n");
xilkernel_main();
return 0;
}
I think the magic functions with Xilkernal are just the
"register_int_handler" and "enable_interrupt". I have initialized the
timer properly and read the control status register while running. The
timer generates the interrupt bit correctly but THE INTERRUPT HANDLER
JUST KEEPS SILENCE. I have checked everything I can. With Standalone,
the board just runs perfectly.
Could anyone give me a hint or help? I am blocked here for the simple
project for several days and quasi-mad.
Thanks in advance
zl
Article: 118387
hallo, people,
I am a beginner on Xilkernel running on PPC405-Virtex 4.
I just want to get interrupt generated from the OPB peripheral and the
have the interrupt handler routine serviced. It seems there is a bug I
can not find. The Xilkernel has no interaction with the interrupt
handler routine. I have taken the example project from Xilinx website,
which generates a periodic interrupts from a timer. The piece of codes
is as following:
#include "xmk.h"
#include <os_config.h>
#include <stdio.h>
#include <xparameters.h>
#include <xtmrctr_l.h>
#include <xstatus.h>
#include <pthread.h>
#include <semaphore.h>
#include <sys/intr.h>
#define TIMER_COUNTER_ID 0
volatile unsigned int mins, hrs, secs, tot_secs = 0;
unsigned int addr=XPAR_TIMER_2_BASEADDR;
int_id_t intTimerID = XPAR_INTC_TIMER_2_INTERRUPT_INTR;
void interval_timer_initialize ()
{
print ("CLOCK: Configuring extra timer to generate one interrupt
per second..\r\n");
XTmrCtr_mWriteReg (addr, TIMER_COUNTER_ID,
XTC_TLR_OFFSET, SYSTMR_CLK_FREQ);
// reset the timers, and clear interrupts
XTmrCtr_mSetControlStatusReg (addr, TIMER_COUNTER_ID,
XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK );
// start the timer
XTmrCtr_mSetControlStatusReg (addr, 0,
XTC_CSR_ENABLE_TMR_MASK |
XTC_CSR_ENABLE_INT_MASK |
XTC_CSR_AUTO_RELOAD_MASK |
XTC_CSR_DOWN_COUNT_MASK );
}
void extra_timer_int_handler ()
{
unsigned int control_reg;
control_reg = XTimerCtr_mReadReg (addr, TIMER_COUNTER_ID,
XTC_TCSR_OFFSET);
XTmrCtr_mWriteReg (addr, TIMER_COUNTER_ID,
XTC_TCSR_OFFSET,
XTC_CSR_LOAD_MASK | XTC_CSR_INT_OCCURED_MASK);
// remove the reset condition such that the timer counter starts
running
// with the value loaded from the compare register
XTmrCtr_mWriteReg (addr, TIMER_COUNTER_ID,
XTC_TCSR_OFFSET,
control_reg | XTC_CSR_ENABLE_TMR_MASK);
}
void* my_main (void *arg)
{
int a = 0;
XStatus status;
if ((status = register_int_handler(intTimerID,
extra_timer_int_handler, NULL)) != XST_SUCCESS) {
xil_printf ("CLOCK: Unable to register handler. Error code: %d.\r\n",
status);
goto err;
}
else print ("CLOCK: Successfully registered a handler for extra
timer interrupts.\r\n");
interval_timer_initialize ();
print ("CLOCK: Enabling the interval timer interrupt...\r\n");
enable_interrupt (intTimerID);
while (1) {
}
err:
xil_printf ("CLOCK: Clock functions unavailable...\r\n");
return NULL;
}
int main(){
xil_printf("main\r\n");
xilkernel_main();
return 0;
}
I think the magic functions with Xilkernal are just the
"register_int_handler" and "enable_interrupt". I have initialized the
timer properly and read the control status register while running. The
timer generates the interrupt bit correctly but THE INTERRUPT HANDLER
JUST KEEPS SILENCE. I have checked everything I can. With Standalone,
the board just runs perfectly.
Could anyone give me a hint or help? I am blocked here for the simple
project for several days and quasi-mad.
Thanks in advance
zl
Article: 118388Can you please try copying the fft.ngc file produced by the core generator into the implementation sub-directory of your EDK project directory and regenerate the netlist ? --swamyArticle: 118389
Rebecca wrote:
> When I complie the simulation library in EDK 9.1.01i using the library
> compilation wizard, it told me that "modlesim is not found! please
> ensure that the simulator is correctly installed and/or the necessary
> envoroment settings are available".
Click up a shell, bash or cmd.exe
mkdir play
cd play
vcom
If this doesn't give you the vcom usage,
type "exit" to close the shell,
find vcom, and add it's location
to your path and try again.
-- Mike Treseler
From removethisthenleavejea@replacewithcompanyname.co.uk Wed Apr 25 09:51:34 2007
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From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Newsgroups: comp.arch.fpga
References: <1177070132.270147.235340@b75g2000hsg.googlegroups.com> <46291b26$1@clear.net.nz> <1177138805.230884.181070@e65g2000hsc.googlegroups.com> <f0l5v5$kdq$2@f04n12.cac.psu.edu>
Subject: Re: DARNAW! - PGA Style FPGA Module
Date: Wed, 25 Apr 2007 17:51:34 +0100
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Xref: prodigy.net comp.arch.fpga:130058
Eli
A Virtex-4 based one is on our thought path. Probably a FX12 as we use this
part in a number of places already although as yet not yet on our
development boards. This is also a bit of a market tester to see how it
takes and what people like, or not, about the concept.
Our first batch is relatively small but now it is proven we can more to
large numbers very quickly subject to silicon purchase which is usually less
than 8 weeks on Spartan (we already have some unallocated stock). If you
have serious interests in this or a V4 version there are discounts for
educational, or volume, usage.
John Adair
Enterpoint Ltd.
"Eli Hughes" <emh203@psu.edu> wrote in message
news:f0l5v5$kdq$2@f04n12.cac.psu.edu...
> Excellent product! This is perfect for our needs. We usually make 2-4
> layer boards but don't want to deal with BGA.
>
> Keep up the great work!
>
> What kind of quantities are available? This would be really cool with a
> Virtex 4 device (one with a power PC built in!)
>
>
>
> John Adair wrote:
>> Jim
>>
>> What you see on the current photo are the solder joints of a double
>> ended pin so the pins come out the bottom as currently done. Given we
>> don't need to meet a specific pinout we could take them out the top if
>> someone need one that way or even have a socket + pin assembly like we
>> use in out OVERCOAT arrays. We can also make these with an un-
>> populated header and this could be a lot cheaper for high numbers used
>> in production say in a low pin count application.
>>
>> The PGA pin header is not cheap either to purchase or even to assemble
>> so I would recommend anyone with a specific interest that would want a
>> a few+ should come and talk to us. We can deal with Bill of of
>> Materials variants for 5-10+ shipping units and can even be economic
>> on a customised pcb variant of any of our products in fairly small
>> numbers (say 25+ off on a small product like this). Our development
>> board products really are only a demo of what we can do and supply
>> ideas to be used in a mix and match fashion on customer specific
>> designs.
>>
>> John Adair
>> Enterpoint Ltd.
>>
>> On 20 Apr, 20:58, Jim Granville <no.s...@designtools.maps.co.nz>
>> wrote:
>>> John Adair wrote:
>>>> Finally first picture of Darnaw1 our PGA style FPGA board is here here
>>>> http://www.enterpoint.co.uk/moelbryn/darnaw1.html. More information on
>>>> pricing and spec in the next couple of days will appear on the
>>>> website. Those with eagle eyes can work it out the spec from the
>>>> picture.
>>> Are all the components shown - no photo of the rear ?
>>>
>>> Does the PGA plug into the side we see, or the other side ?
>>> [and the side we see is for probing - but not labelled ? ]
>>>
>>> -jg
>>
Article: 118390
Gordon Freeman wrote:
> Can you show me how to take the verilog code for synthesize? I would
> like to know how they process in this code.
It's a black box netlist.
Your choices are
1. instance and use it as is, or
2. write and test your own code for synthesis.
-- Mike Treseler
Article: 118391On Apr 24, 4:06 am, Gordon Freeman <gordonfreeman1...@gmail.com> wrote: > On Apr 24, 4:29 pm, FPGA <esp...@gmail.com> wrote: > > > > > > > Hi Gordon, > > > The core generator only generates the netlist for the IP with Verilog/ > > VHDL wrapper file functional simulation. > > If you use ISE, then you can generate the core inside the ISE and you > > can instantiate the core in your design. > > Just right click on your project and select "New source" and > > IP(Coregen & Arch Wizard) and you can generate > > the same core and ISE will add the necessary files automatically. > > > William > > On Apr 24, 12:16 am, Gordon Freeman <gordonfreeman1...@gmail.com> > > wrote: > > > > Hi everyone! > > > I use Xilinx Core generator to generate DA FIR filter. Right now, I > > > want to take the verilog code for DA FIR filter but I don't know how > > > can I do it. > > > Can you help me? > > Thank you for your reply. > But I can't modify it. > Can you show me how to take the verilog code for synthesize? I would > like to know how they process in this code.- Hide quoted text - > > - Show quoted text - I think you do not understand: There is no verilog code to take. It is a "black-box macro"; the verilog wrapper just sets the parameters (configuration) of that macro. You might be able to learn something by doing a gate level simulation, but that would be very tedious. GH.Article: 118392
On 2007-04-25, M. Hamed <mhs000@gmail.com> wrote:
> Is there a way I can get ModelSim to display the time progress of the
> simulation when it's running in command line/batch mode similar to
> what it would do at the bottom of the GUI window?
Put something like the following in a TCL script:
proc printsimstate {} {
global now
global UserTimeUnit
echo "Simulator time is $now, timescale is $UserTimeUnit"
after 5000 printsimstate
}
after 5000 printsimstate
I haven't tested it much since I just wrote it, but it seems to work
fairly ok.
/Andreas
Article: 118393Is there a way I can get ModelSim to display the time progress of the simulation when it's running in command line/batch mode similar to what it would do at the bottom of the GUI window? Thank you.Article: 118394
Thanks for the tip, I forgot to add it after I went from a print statement
that I was using. It still stalls though.
---Matthew Hicks
> Hi Matthew,
>
> Matthew Hicks <mdhicks2@uiuc.edu> writes:
>
>> I'm working on a RTOS for the PowerPC chip on the Virtex-II XUP
>> board. I need an interrupt to trigger so I run my scheduler at
>> regular intervals, so I setup the PIT to trigger an interrupt at 1s
>> (purely for testing reasons, I will be going down to around 5ms).
>> The program seems to pause when I finally enable the interrupt and I
>> see no signs that the handler has been run. I looked at several
>> references and spent a day shifting around my code, to no avail. If
>> someone could take a peek at my code below and offer assistance that
>> would be great. Thanks.
>>
>> #include "xparameters.h"
>> #include "stdio.h"
>> #include "xbasic_types.h"
>> #include "gpio_header.h"
>> #include "xexception_l.h"
>> #include "xtime_l.h"
>> Xuint32 status;
>>
> I don't know about the rest of the code, but this declaration needs to
> be volatile...
>
> volatile Xuint32 status;
>
> <snip>
>
>> status = 0;
>> while(status != 55)
>> {
>> ;
>> }
> Otherwise the compiler optimises this to an infinite loop because it
> "knows" that nothing can make status == 55
>
> Cheers,
> Martin
Article: 118395"X.Y." <Xieyu1219@gmail.com> wrote in message news:1177133707.465497.263100@y80g2000hsf.googlegroups.com... > To Peter Alfke, Symon and John Larkin: Thank you for your help. We had > design a PCB board to test the method you told us and we could get it > next Tuesday (April, 24th). However, we do a simple experiment to have > a simple qualitative analysis. We use a scope of 2.5G/S and 10GSa/S. > The conclusion is fairly positive. The figures can not be posted here, > so they are posted on my blog. So please visit the site: > http://xieyu1219.blogspot.com/ to see it. Thank you! If we have > further information, we will also tell you. Thanks for sharing the pictures. Please note that for source-series terminated lines, the signal at the load (destination) will be different and closer to ideal than the signal at the driver (source). If your blog image is from the transmit side of the cable, look at the other end. It may also be that the series resistors need to be adjusted. From the looks of your signal, I'd estimate you're using about 2 meters of ribbon cable rather than 1, showing the time from transition until the reflected signal as about 18 ns. I'd estimate the speed of light across ribbon cable as about 2/3 C or about 4.5 ns per meter (but I'm not certain). The return trip for the reflection doubles the time from the driver transition to the observed reflection. You should see a big difference on the other side of the cable. Try slightly greater resistor values (60 ohm to 100 ohm) and see if your signal at the receive side improves further. - John_HArticle: 118396
Thanks for your feedback. What kind of skew are you looking at between the transceivers? Is it few 100 ps or nano seconds? In our protocol there is going to be training algorithm for each bit and then there is also packet alignment algorithm. This gives an opportunity to adjust the skew externally using software programmable delay elements. You sueessted using separate phy layer. Are you suggesting to use external high speed discrete components to achieve this? If so what high speed components you recommend? I have seen On Semi has 8:1 mux and demux that can run at this speed but I was trying to avoid that complexity of syncronizing those mux and demux and high speed clocks. Any suggestions are welcome.Article: 118397
Hi Austin, Thanks for your help...Greatly appreciated! PepiArticle: 118398
lzh08 wrote: > it is work good! > So where's your design then? -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 118399
On Wed, 25 Apr 2007 17:44:18 +0000 (UTC),
Andreas Ehliar <ehliar@lysator.liu.se> wrote:
>On 2007-04-25, M. Hamed <mhs000@gmail.com> wrote:
>> Is there a way I can get ModelSim to display the time progress of the
>> simulation when it's running in command line/batch mode similar to
>> what it would do at the bottom of the GUI window?
>
>
>Put something like the following in a TCL script:
>proc printsimstate {} {
> global now
> global UserTimeUnit
> echo "Simulator time is $now, timescale is $UserTimeUnit"
> after 5000 printsimstate
>}
>after 5000 printsimstate
Andreas,
nice, but be aware that it will leave an "after" action lying around;
if you pause the sim (or it reaches a breakpoint) you will continue
to get "Simulator time is..." messages spitting out of the console
every five seconds.
This seems to be closer to a robust solution, although you might
also want to provide a new timed version of the "continue"
command too. Just source this Tcl script into ModelSim
before running the sim, and then use "trun" instead of "run"
to start the simulation.
# Smarter version of "run" that displays timings as it runs
proc trun {args} {
# Start the periodic runtime display
after 2000 printSimTime
# Do the usual run command
eval run $args
}
#
# Periodic time display, stops itself when the
# run is stopped or interrupted
proc printSimTime {} {
echo "time = $::now"
if { [string equal running [runStatus]] } {
after 2000 printSimTime
}
}
In my own experiments I've found that the value of "now" that this
code reports is not very reliable - presumably, thanks to the very
heavy CPU loading caused by a busy simulation, things don't always
get updated as promptly as you might hope. Even so, it's
better than nothing.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
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