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user@domain.invalid wrote: > Hello all, My email is sietse@cs.rug.nl SietseArticle: 118426
On Apr 26, 11:53 am, Roman <plyas...@googlemail.com> wrote: > have you set in .mss file in xilkernel section PARAMETER > sysintc_spec=<interrupt device>? Thanks for help. Yes, for sure. I have checked all the possible tiny details. But I have figured out a little bit about the reason, perhaps not the direct trigger to the bug. The hardware design is changed from another project, which include UART16550. I want to use Xilkernel instead of Standalone. Therefore, i have to recomplie the hardware design. I just take away those licensed parts, change to Xilkernel and regenerate the Netlist in XPS 8.2. Somehow, when generating the new bitstream, it is informed that it should be done with project navigator. Then I just leave it so and go on with the software design. I guess that is the point. I will ask the hareware people to redesign the hardware and report the result here.Article: 118427
"Pablo" <pbantunez@gmail.com> wrote in message
news:1177589968.992704.94060@t39g2000prd.googlegroups.com...
> Hi, I have written in this chat a pair of threads about Sdram and
> heap_size. I want to say that I think that heap_size cannot be changed
> with Microblaze. I need to do "xil_malloc(16*4096), but in SDRAM
> (32MB) I only can do "xil_malloc(15*4096)". Then I have increased
> "heap_size" in Linker Script since 0x400 to 0x1400000. I have put 24Mb
> for "heap_size" but it seems heap_size keeps as same as 0x400.
Forget about xil_malloc() and just use malloc().
-Ben-
From tbrown@tyzx.com Thu Apr 26 07:04:23 2007
Path: newssvr13.news.prodigy.net!newsdbm04.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!cyclone1.gnilink.net!spamkiller2.gnilink.net!gnilink.net!trndny09.POSTED!95dec472!not-for-mail
From: Terry Brown <tbrown@tyzx.com>
Subject: Re: Modelsim simulation progress in batch/command line mode?
Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog
References: <1177525567.390994.19980@n15g2000prd.googlegroups.com>
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Xref: prodigy.net comp.arch.fpga:130095 comp.lang.vhdl:69762 comp.lang.verilog:35900
On Wed, 25 Apr 2007 11:26:07 -0700, M. Hamed wrote:
> Is there a way I can get ModelSim to display the time progress of the
> simulation when it's running in command line/batch mode similar to what
> it would do at the bottom of the GUI window?
>
> Thank you.
Is there a reason people don't suggest just using an always block in the
test bench?
For example, I use:
//this is a status heartbeat for batch mode operation
integer microseconds;
reg heartbeat;
always #10000 microseconds = microseconds + 10;
always @ (microseconds)
if (heartbeat)
$display("%d us",microseconds);
This has the advantage on not requiring tcl (and the scripting is an
enhanced, pay for it option), and is portable to other simulators.
Terry Brown
Tyzx, Inc.
Article: 118428On 13 Apr, 23:35, Eric Smith <e...@brouhaha.com> wrote: > I was hoping to download Francesco Poderico's Picoblaze C compiler > today, but unfortunately his domain is expired. Google didn't > turn up any other sites from which I can download it; does anyone > know of such a location, or would anyone be willing to make it > available online or send me a copy? (Provided that doing so > doesn't violate any license terms.) > > Thanks! > Eric Hi, I'm Francesco Poderico. I'm trying to move my domain from my old provider to a newone (cheap) Don't know why ... but this operation seems impossible because my hosting has expired before I ask to transfer my domain??? So if you need any help/latest version of the compiler please contact me at francesco_poderico@yahoo.com If in one week time from today (26/4/2007) I still did not manage ro transfer my domain then I will create a new domain. Regards, FrancescoArticle: 118429
I've asked for help once before on this topic and was directed to look at Ap Note #367. Unfortunately, when I unzip the example designs, I didn't find a walk-through or readme file that describes how to go through each example (am I missing something?). I am using a Stratix II part and need to be able to monitor a input pin, after power-up/ reconfiguration is complete, to switch between two different sets of dividers (this pin will tell the FPGA that one of two input clocks are going to be used). From Ap Note 367 and the ALTPLL_RECONFIG Megafunction User's Guide, it appears that this external state machine/logic needs to determine if a reconfigure is required and if so, issue a 1 clock pulse on the reconfig pin of the ALTPLL_RECONFIG line, wait for the reconfiguration to be done, and then issue an asynchronous reset. (The asynchornous reset also needs to be sent even if the reconfig is not needed). None of the documentation that I've seen so far shows examples on how to do this. I've seen included drawings that just show interconnection between the ALTPLL_RECONFIG and ALTPLL -- nothing else is given. Does anyone have a step-by-step example with code and/or drawings that explains how to really design with the ALTPLL_RECONFIG and ALTPLL megawizard functions?Article: 118430
Hello Group, i am working on a project with a cesys card (PCIS3BASE). My problem is as follows: I wish to run the basic tests that are shipped with the card. The programs however fail to detect the card (It appears under various windows utilities though as well as plx utilities like plxmon). I guess this is because I have the wrong version of the driver. Could somebody please help me out on this? Many thanks in advance. Regards, S.j.Article: 118431
Thank you for your relpy. I can't get vcom at the EDK shell. The path for modelsim is added to my PATH varaiable. But I can't run it at a shell. Probably something wrong with my windows setting.Article: 118432
> Click up a shell, bash or cmd.exe > > mkdir play > cd play > vcom > > If this doesn't give you the vcom usage, > type "exit" to close the shell, > find vcom, and add it's location > to your path and try again. > > -- Mike Treseler You are right. I can't find vcom usage. But I do added the location of modelsim and XPS to the PATH. Neither of them work. Probably something wrong with my windows setting. Thanks, RebeccaArticle: 118433
Ive got differential signal ALE (composed from ALE_P and ALE_N) like
in attached vhdl entity:
entity top is
PORT(
ALE_p, ALE_n : IN std_logic
);
end top;
Could anybody tell me how in synplify constraint (sdc) assign
differential pins to this signals for altera stratix 2 device?
Is such assignment valid for Synplify: define_attribute {ALE}
altera_chip_pin_lc {{AA3 AA4}}
??? (lets assume that AA3 and AA4 are differential pair pins)
Article: 118434On Apr 25, 10:56 pm, Matthew Hicks <mdhic...@uiuc.edu> wrote: > Well, I found the solution. When I regenerate the linker script the program > works 100% correctly. Forgive my newness to things like this (I come from > the high-level land of windows application programming not embedded programming), > but is this something that I should have done from the start? I've never heard of this particular problem, but in general, intermediate files can get into unexpected states, so it is a good idea to periodically recompile everything from the beginning (ie. make clean). This is true for hardware and software (and perhaps in life as well :-). Alan Nishioka alan@nishioka.comArticle: 118435
On Apr 25, 7:26 pm, "M. Hamed" <mhs...@gmail.com> wrote: > Is there a way I can get ModelSim to display the time progress of the > simulation when it's running in command line/batch mode similar to > what it would do at the bottom of the GUI window? > > Thank you. ModelSim SE and Questa users can use the JobSpy tool to monitor and interact with batch jobs, including those running under LSF and Grid Engine load sharing software. One of the available JobSpy commands is 'now', which prints the current simulation time. Have a look at the 'Monitoring Simulations with JobSpy' chapter in the User's Manual - NigelArticle: 118436
On 26 abr, 10:16, Andreas Hofmann <ahn...@gmx.net> wrote: > Pablo schrieb: > > > I have incresed heap_size, but it seems like sdram cannot use more > > than 60 kbytes. > > That's no SDRAM problem. As the Xilinx EDK documentation states: > > "The xil_* functions operate on a 64 kilobyte buffer, and allocate > memory from that. The size of this buffer is fixed and cannot be changed > currently. This is a limitation of the xil_* dynamic memory allocation > routines." [oslib_rm.pdf/EDK 8.1] > > I don't know if this has changed in subsequent EDK versions. The PPC405 > malloc/calloc does not suffer from this limitation. > > Best regards, > Andreas Thanks. I think so. Any idea?Article: 118437
Now it is working. I just remove some; and space in the PATH enviroment and then it works. Thank you, RebeccaArticle: 118438
Thank you. This seems to work well. I was wondering if it's possible to format the time display to display in a certain unit like us or ns.Article: 118439
Dear All, Does anyone know of a replacement for the standard C sscanf() function? I need to use this function, but it takes a huge chunk memory, a little bit like printf(), and my system based on the spartan-3 starter kit board only has 16KB of memory. Tanks Jos=E9 MarianoArticle: 118440
On Apr 26, 6:07 am, Colin Paul Gloster <Colin_Paul_Glos...@ACM.org>
wrote:
> Innews:1177343468.316440.109490@n76g2000hsh.googlegroups.com
> timestamped 23 Apr 2007 08:51:08 -0700, wallge <wal...@gmail.com>
> posted:
> "I don't know about ultraedit,
>
> but emacs VHDL mode does a wonderful job colorizing [..]"
>
> To be fair, please do not overrate what modes for Emacs
> accomplish. Many (maybe all) coloring modes for Emacs have a feature I
> have not noticed in any other text editing program: perceptible delays
> in coloring characters. In my experience coloring delays in Emacs tend to
> be less than a second (even for perceptible delays) (except for
> coloring HTML which takes more than two seconds for even recoloring
> this newsgroup post I am composing when I delete or add a quotation
> mark (I am composing with Emacs but not
> posting with Gnus, and this post is not in HTML but the file format which
> Lynx invokes Emacs with is deemed by Emacs to be HTML)), but I have not
> noticed temporarily incorrect coloring in other software. I have
> definitely noticed these delays in Emacs on a number of (>> 100MHz)
> machines on a number of operating systems with little processor
> utilization by other processes over a number of years and definitely
> for at least VHDL; Ada; TeX; and HTML. (On one occassion for Ada, Emacs
> never finished correctly coloring one character even though I provided
> it with many seconds and ordered it to print the file. I do not
> believe that I accidentally deactivated the mode before it was finished.)
>
> "I use it exclusively..."
>
> I believe that people who use text editing software tend to be of one
> of two types of people: people who insist on using the same text
> editing program pretty much all the time; and people who are happy to
> use just about any text editing program. I do not exclusively restrict
> my text editing to one program.
>
> " It also has a nice hierarchy browser and
> lots of other VHDL specific functionality built in."
>
> Different things suit different people. Sometimes VHDL mode is good
> for me when editing VHDL code, sometimes it is annoying (to me) (and
> it is not its fault): as a habit from Ada I sometimes accidentally type
> .. instead of downto and VHDL mode automatically replaces .. with =>.
> TeX mode is so much worse that I often turn it off for a TeX file if I
> want to use a straight quotation mark (") such as for one of the many
> Babel configurations which use " as an active character, because TeX
> mode replaces a straight quotation mark with curved quotation marks
> (`` or '').
>
> "There are some nice cheat sheets available through
> a google search that have all the important keyboard shortcuts
> as well..."
>
> As the keyboard shortcuts can be redefined, those cheat sheets must
> enumerate a lot of shortcuts! :)
The biggest thing I really like about most modes in (x)emacs is that
individual features can be turned off/on to suit. If you don't like a
feature (e.g. ".." -> "=>"), just turn it off, but you can still have
everything else turned on.
I have not seen the performance problems with fontification that you
have seen, at least with vhdl (my primary use for xemacs).
Andy
Article: 118441Test01 wrote: > Thanks for your feedback. What kind of skew are you looking at between the transceivers? Is it few 100 ps or nano seconds? In our protocol there is going to be training algorithm for each bit and then there is also packet alignment algorithm. This gives an opportunity to adjust the skew externally using software programmable delay elements. > > You sueessted using separate phy layer. Are you suggesting to use external high speed discrete components to achieve this? If so what high speed components you recommend? I have seen On Semi has 8:1 mux and demux that can run at this speed but I was trying to avoid that complexity of syncronizing those mux and demux and high speed clocks. > > Any suggestions are welcome. Using multiple GTP SERDES to implement a parallel source synchronous bus is not a supportable implementation and I would strongly encourage you to find an alternative approach to interfacing to your ASIC (or to redesign your ASIC to a different interface). There are a couple of standard with multiple SERDES that have transmitter requirements of channel-to-channel skew with 1-3 UI which can be supported in the V-5 LXT devices, but the other end of the link is a SERDES that implements a CDR for locking the clock to the data inputs. Without this function in your ASIC the likely have a robust and reliable link is very very low. Ed McGettigan -- Xilinx Inc.Article: 118442
Yes I'm using Xilinx tools. For this scenario, FF1(fclk) generates ssclk (sclk after synchronization), and ssclk clocks FF2(ssclk) the output of that is the data input for FF3(fclk) after some logic. I wonder if I can specify a path from FF1 to FF3 cause that's the actual path that I need to limit to one clock cycle, or do I have to provide 2 separate paths FF1 to FF2 and FF2 to FF3? Thank you. On Apr 26, 6:37 am, John_H <newsgr...@johnhandwork.com> wrote: > > Yes, there is a way. > > If you're using Xilinx tools, for instance, you would use a FROM/TO > constraint which you can specify as the fclk period explicitly or with > nanoseconds. You should find the FROM/TO syntax and details in the > constraints guide. >Article: 118443
When I used the EDK simulation library wizard, it never succeeded. So I have to compile the ISE libaray manually under the target directory using: compxlib -s mti_se -lib unisim -lib simprim -lib xilinxcorelib -lib smartmodel -arch virtex -arch virtex2p -arch virtex4 -arch spartan3 - arch virtex5 -l all -dir . -w -smartmodel_setup And then generate the EDK library using the wizard. No error was reported. But when I genenerated the simulation HDL files for the project, EDK gives me error "ISE Sim Library: XPS can not get library information from the path ... please make sure... ". and stoped. Any suggestion? Many thanks, RebeccaArticle: 118444
Hi, The ISE iMPACT 9.1i does offer some expanded capability in this regard. You didn't specify if your "system" is the Spartan-3E Starter Kit or if it's another prototype/development board, or something of your own design. If you clarify what you are working with I can then attempt to describe your options. Thanks, Eric "Sven" <sven@is.com> wrote in message news:463077c7$0$90273$14726298@news.sunsite.dk... >I have a system with a Spartan-3E with an SPI flash. I have been using the >xspi.exe DOS program to configure the SPI flash. But now I'm wondering if >the new ISE IMPACT 9.1 or later is able to configure the SPI flash though >JTAG? > > > > I saw in XAPP974 for the Spartan-3A that it was possible at least for that > device. But is the same possible for Spartan-3E? > > > > > > >Article: 118445
When I used the EDK simulation library wizard, it never succeeded. So I have to compile the ISE libaray manually under the target directory using: compxlib -s mti_se -lib unisim -lib simprim -lib xilinxcorelib -lib smartmodel -arch virtex -arch virtex2p -arch virtex4 -arch spartan3 - arch virtex5 -l all -dir . -w -smartmodel_setup And then generate the EDK library using the wizard. No error was reported. But when I genenerated the simulation HDL files, EDK gives me error "ISE Sim Library: XPS can not get library information from the path ... please make sure... ". and stoped. Any suggestion? Many thanks, RebeccaArticle: 118446
jmariano <jmariano65@gmail.com> wrote: >Dear All, > >Does anyone know of a replacement for the standard C sscanf() >function? > >I need to use this function, but it takes a huge chunk memory, a >little bit like >printf(), and my system based on the spartan-3 starter kit board only >has 16KB of memory. > >Tanks With some luck, you can find a smaller implementation. Otherwise you may be able to write your own scanf. It is always a good idea to create smaller implementations of standard C library functions instead of inventing your own library. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 118447
When I used the EDK simulation library wizard, it never succeeded. So I have to compile the ISE libaray manually under the target directory using: compxlib -s mti_se -lib unisim -lib simprim -lib xilinxcorelib -lib smartmodel -arch virtex -arch virtex2p -arch virtex4 -arch spartan3 -arch virtex5 -l all -dir . -w -smartmodel_setup And then generate the EDK library using the wizard. No error was reported. But when I genenerated the simulation HDL files for the project, EDK gives me error "ISE Sim Library: XPS can not get library information from the path ... please make sure... ". and stoped. Any suggestion? Many thanks, RebeccaArticle: 118448
On Apr 26, 1:07 pm, jmariano <jmarian...@gmail.com> wrote: > Dear All, > > Does anyone know of a replacement for the standard C sscanf() > function? > > I need to use this function, but it takes a huge chunk memory, a > little bit like > printf(), and my system based on the spartan-3 starter kit board only > has 16KB of memory. > > Tanks > > Jos=E9 Mariano sscanf takes a huge chunk of memory because it does a lot of formatting. If your format statements can be limited to a small subset of the available data conversion types, for example %x or %d, you could reduce the code size considerably. What formats do you really need? Perhaps you could get away with atoi (ascii to integer) instead of using sscanf?Article: 118449
Here is a simple reduced version of sscanf I wrote years ago. Hope it
helps!
//
// Reduced version of scanf (%d, %x, %c, %n are supported)
// %d dec integer (E.g.: 12)
// %x hex integer (E.g.: 0xa0)
// %b bin integer (E.g.: b1010100010)
// %n hex, de or bin integer (e.g: 12, 0xa0, b1010100010)
// %c any character
//
int rsscanf(const char* str, const char* format, ...)
{
va_list ap;
int value, tmp;
int count;
int pos;
char neg, fmt_code;
const char* pf;
va_start(ap, format);
for (pf = format, count = 0; *format != 0 && *str != 0; format++, str+
+)
{
while (*format == ' ' && *format != 0)
format++;
if (*format == 0)
break;
while (*str == ' ' && *str != 0)
str++;
if (*str == 0)
break;
if (*format == '%')
{
format++;
if (*format == 'n')
{
if (str[0] == '0' && (str[1] == 'x' || str[1] == 'X'))
{
fmt_code = 'x';
str += 2;
}
else
if (str[0] == 'b')
{
fmt_code = 'b';
str++;
}
else
fmt_code = 'd';
}
else
fmt_code = *format;
switch (fmt_code)
{
case 'x':
case 'X':
for (value = 0, pos = 0; *str != 0; str++, pos++)
{
if ('0' <= *str && *str <= '9')
tmp = *str - '0';
else
if ('a' <= *str && *str <= 'f')
tmp = *str - 'a' + 10;
else
if ('A' <= *str && *str <= 'F')
tmp = *str - 'A' + 10;
else
break;
value *= 16;
value += tmp;
}
if (pos == 0)
return count;
*(va_arg(ap, int*)) = value;
count++;
break;
case 'b':
for (value = 0, pos = 0; *str != 0; str++, pos++)
{
if (*str != '0' && *str != '1')
break;
value *= 2;
value += *str - '0';
}
if (pos == 0)
return count;
*(va_arg(ap, int*)) = value;
count++;
break;
case 'd':
if (*str == '-')
{
neg = 1;
str++;
}
else
neg = 0;
for (value = 0, pos = 0; *str != 0; str++, pos++)
{
if ('0' <= *str && *str <= '9')
value = value*10 + (int)(*str - '0');
else
break;
}
if (pos == 0)
return count;
*(va_arg(ap, int*)) = neg ? -value : value;
count++;
break;
case 'c':
*(va_arg(ap, char*)) = *str;
count++;
break;
default:
return count;
}
}
else
{
if (*format != *str)
break;
}
}
va_end(ap);
return count;
}
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