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I've been trying to use Quartus 7 on Linux (I've tried three different RedHat/Clone distros, FC6, CentOS 5, Scientific Linux 4.4. The fitter is getting a license failure, Current license file does not support the EP2SGX90FF1508C4 device Quartus 6.1 runs fine and my Altera FAE thinks my license file is fine. Has anyone run Quartus 7 on Linux, how about on a RH clone? Is it possible that they put in a check for the distro to see if it's a supported distro?Article: 118926
Hi All, I'm planning to attach a high capacity compact flash card to my Spartan-3 design. I don't want to use any file system on it, just raw data access. Is there any size limitation on the compact flash using the Sysace hw/ sw. I would need as much space as possible, but at least 8 GB. Regards, ZoltanArticle: 118927
Hi! For a small project running Linux on a Virtex2pro, I need to write an IP-component, that recive data from portpins and can transfer data to RAM directly. I'm tring to understand DMA, generated by Xilinx EDK (8.2) wizzard. I think, I've understand some basics. Afer writing the datalength in the register, the transfer will begin. Correct? Writing datalength, source- and destinationaddress is done by the driver? But how cat I write data from the user_logic to the memory?Article: 118928
On May 7, 4:25 am, himassk <hima...@gmail.com> wrote: > Hi, > can any one please clarify me that all the FF in the FPGA has same > setup time and hold time values? > If not why and where these different FF can be used? Why do you ask? There usually is a hidden reason behind questions like yours. Obviously CLB flip-flops and I/O flip-flops are different, as are registers in the BRAM and the DSP48 blocks. But all of these parameters are documented in the data sheet (on the web). Positive hold times have ugly system ramifications, and we try to make them zero or negative whenever possible. Peter Alfke, XilinxArticle: 118929
On May 7, 9:46 am, General Schvantzkoph <schvantzk...@yahoo.com> wrote: > I've been trying to use Quartus 7 on Linux (I've tried three different > RedHat/Clone distros, FC6, CentOS 5, Scientific Linux 4.4. The fitter is > getting a license failure, > > Current license file does not support the EP2SGX90FF1508C4 device > > Quartus 6.1 runs fine and my Altera FAE thinks my license file is fine. > Has anyone run Quartus 7 on Linux, how about on a RH clone? Is it > possible that they put in a check for the distro to see if it's a > supported distro? Hi, There is a bug in 7.0 which will affect the user if the license is for 1 user only. There is a patch available for it. Quartsu II 7.0 Patch 0.02. Please contact mysupport and ask for it. We apologize for any inconvenience this may have caused. Hope this helps, Subroto Datta Altera Corp.Article: 118930
On May 7, 8:38 am, Test01 <cpan...@yahoo.com> wrote: > Andy, > > Here is what I have from the datsheet. > > The HSL outputs are VCC referenced. This means that if an output has a typical 1100 mVp-p differential swing (i.e. 550 mVp-p on each arm), then each output (primary and complementary) varies between approximately Vcc and Vcc - 0.55V, which suggests a common mode voltage, Vcm, that is the average of that range (i.e. Vcc - 0.275V)." You're right, my bad. However, just because the output is referenced from Vcc does NOT mean that one end is @ Vcc. I would not assume that Vcm = Vcc - (Vopp/2) just from what you told me. AndyArticle: 118931
cpope wrote: > Has anyone tried to install xilinx webpack on ubuntu 6.06LTS? If I run the > web download tool (sudo ./setup) I get through the questions but it dies > shortly after I click install. If I use the single file download it asks for > a registration ID which as far as I can tell doesn't exist for webpack? Any > help is appreciated. > > Thanks, > Clark > > Just create an account. It doesn't come with a sales-person ;) And than you can download the Webpack for free. Sietze.Article: 118932
Further reading of the data sheet suggested that the part has a separate pin to control the Vcm from 1.8v to 3.3V. For 1.8V Vcm, the High voltage will be 2.075V and the low voltage will be 1.525V. Can the Xilinx LVPECL input take this ampitude of Vcm = 1.8V and 1100 mV differential voltage (Vhigh = 2.075V, Vcm = 1.8V and Vlow = 1.525V)? Thanks.Article: 118933
On May 7, 1:10 pm, berton <werbu...@gmx.de> wrote: > Hi! > > For a small project running Linux on a Virtex2pro, I need to write an > IP-component, that recive data from portpins and can transfer data to > RAM directly. > I'm tring to understand DMA, generated by Xilinx EDK (8.2) wizzard. > I think, I've understand some basics. Afer writing the datalength in > the register, the transfer will begin. Correct? > Writing datalength, source- and destinationaddress is done by the > driver? > But how cat I write data from the user_logic to the memory? Hi, What kind of developement board are you working with? Are you working with a PCI-based dev board? I've worked with a Spartan3 dev board in Linux and have managed to successfully achieve DMA transfers. Best, IanArticle: 118934
On May 7, 12:54 pm, Test01 <cpan...@yahoo.com> wrote: > Further reading of the data sheet suggested that the part has a separate pin to control the Vcm from 1.8v to 3.3V. > > For 1.8V Vcm, the High voltage will be 2.075V and the low voltage will be 1.525V. > > Can the Xilinx LVPECL input take this ampitude of Vcm = 1.8V and 1100 mV differential voltage (Vhigh = 2.075V, Vcm = 1.8V and Vlow = 1.525V)? The Vityex-5 data book (page 35) calls out: Input common mode voltage between 0.6 V and 2.2 V Differential Input voltahe: 0.1 V to 1.5 V But input max voltage not to exceed Vccaux by more than 200 mV, and input min voltage not to go below minus 500 mV. So the answer to your question in: YES, it's ok. Peter AlfkeArticle: 118935
Mike, Appreciate the comment. We are reading these posts. We are taking note of suggestions. Some of them are intriguing, others are not workable. We also appreciate the posts without the venom, and without the 'agendas.' Many on this board are consultants, who make their money by filling in the spaces that Xilinx has missed, ignored, or not done very well in. More power to them, and thank you for being part of the Xilinx eco-system. Also, thank you for pointing out where Xilinx can improve. Some of these folks add no value, and are struggling to survive. We have to read between the lines. AustinArticle: 118936
On May 7, 4:41 am, Antti <Antti.Luk...@xilant.com> wrote:
[snip]
> I hope mch_opb_ddr2 will work, but I have been wondering
> why such demo design is not available - this could be an
> indication that the "out of the box" DDR2 IP core will not
> work onSpartan-3A, so I am in a waiting mode, hoping
> for someone to confirm the useability ofEDKDDR2
> ipcore on XilinxSpartan-3Astarterkit board.
Antti, I'm in the exact same spot as you are, I just got a Spartan-3A
starter kit to test DDR2 in preparation for a custom board design.
Can you share your EDK design with the group? Please also post updates
if you manage to get DDR2 to work.
I did a very quick test yesterday, and the place and route step
complained that it couldn't meet the timing. When creating the design
with BSB it stated that you have to run at 100MHz for the DDR2
controller to work. I haven't gotten further than that, I hope I
missed something basic.
/ Chris
Article: 118937"Sietze Helfferich" <sietze_h@hotmail.com> wrote in message news:463f7f9c$0$55969$dbd43001@news.wanadoo.nl... > cpope wrote: > > Has anyone tried to install xilinx webpack on ubuntu 6.06LTS? If I run the > > web download tool (sudo ./setup) I get through the questions but it dies > > shortly after I click install. If I use the single file download it asks for > > a registration ID which as far as I can tell doesn't exist for webpack? Any > > help is appreciated. > > > > Thanks, > > Clark > > > > > > Just create an account. It doesn't come with a sales-person ;) And than > you can download the Webpack for free. > > Sietze. Yes, I've done that. I'm saying that both installation methods are failing. The web download method dies after install starts and the single file download method asks for a non-existant registration ID. ThanksArticle: 118938
Mike, I'm probably the one you were looking for at ESC. I am not an expert on open source software, but will give you my thoughts on why it won't work for FPGAs: - We have a fair amount of 3rd party software that we ship with ours and we have no rights to distribute that source. - We have about 250 people writing software. While I'm sure there are 20 or 30 people that think FPGAs are cool enough to want to help out, I doubt there are enough. - Most of our time is spent doing new device support (and this in not just within the map and par groups). How do we get these "volunteers" to deliver new devices when we need them? - We start the software for new devices about 2 years before the software for that family is released. Making the details of a new architecture public at that time is not an option. - Going open source is like handing our source code over to our competitors. - I'm not exactly clear on who would support our customers as they run into bugs, but I guess it would be us meaning we would have to have people ready to fix someone else's code. - The only other open source program for FPGAs failed: http://www.pldesignline.com/news/164900514 There are some applications, like the schematic editor, that I would be willing to consider going to open source if someone could show me how that would benefit us and our customers. Regarless of the negative comments we receive on this newsgroup, most customer comments on ISE 9.1i have been extremely positive. Plus, we have put a number of quality initiatives in place and you should see the results of that over the next year. Steve "Mike Lundy" <novas0x2a@gmail.com> wrote in message news:1178553739.440598.126690@y5g2000hsa.googlegroups.com... > On May 5, 2:04 pm, fpga_t...@yahoo.com wrote: >> When their management learn the products can be supported better with >> the same number of people leading the project, and the developers >> learn they are not likely to lose their jobs, it should be an easier >> decision. It's hard sometimes to understand why they think remaining in >> the >> stone age is better. > > I've been poking Xilinx through various techniques about this. I > talked to three or four people Xilinx about it at the recent Embedded > Systems Conference in San Jose; I also tried to talk to Steve Long(? > might be misremembering his name) who apparently is a software > manager, but I kept missing him. I also asked the support guy who has > been handling the bugs I file to pass an email up the chain, and he > said he did. Perhaps it'll land with someone who is willing to take me > up on an offer to talk about it more. > > If everyone with a complaint about the quality of the software does > this, perhaps Xilinx would realize that there are people out there > (such as myself) who think FPGAs are incredibly cool and are willing > to work on the software without expectation of payment as long as > certain open-source rules are observed. The single best example of > this is Michael Gernoth in the thread entitled "Xilinx Platform cable > USB and impact on linux without windrvr"[1]. He was willing to work on > it despite the lack of source, and his result is /quite/ impressive. > > I think the main problem is some level of confusion. Open-sourcing XST > and the various GUI apps does not mean that map/par need to be fully > open-source. Providing map and par as libraries that user-written apps > could call would be perfectly acceptable, given the level of trade- > secrecy involved. Xilinx is not a software company, and it shows. They > should be leveraging the software to increase adoption of the > hardware, not limiting industry growth with low software quality. Once > the realization of this percolates up, perhaps we'll see some changes. > > So, once again. If you have a complaint about the quality, make a > reasoned argument to whoever at Xilinx will listen. Remember that > zealotry and insults won't work here; there is a strong business case > for this to happen, but it requires such a shift from traditional > thinking that every overzealous attempt will cancel out quite a few > reasonable ones. Perhaps one who is a better wordsmith and evangelist > than I can come up with a template that others can use. > > 1) > http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/f149e5b6028e2c70 >Article: 118939
On 7 Mai, 22:12, idp2 <ian.pei...@gmail.com> wrote: > On May 7, 1:10 pm, berton <werbu...@gmx.de> wrote: > > > Hi! > > > For a small project running Linux on a Virtex2pro, I need to write an > > IP-component, that recive data from portpins and can transfer data to > > RAM directly. > > I'm tring to understand DMA, generated by Xilinx EDK (8.2) wizzard. > > I think, I've understand some basics. Afer writing the datalength in > > the register, the transfer will begin. Correct? > > Writing datalength, source- and destinationaddress is done by the > > driver? > > But how cat I write data from the user_logic to the memory? > > Hi, > > What kind of developement board are you working with? Are you working > with a PCI-based dev board? I've worked with a Spartan3 dev board in > Linux and have managed to successfully achieve DMA transfers. > > Best, > Ian thanks for answering! We are working with the xilinx xup v2p with a patched linux 2.6 kernel.Article: 118940
Are you specifically interfacing to the GTPs? These RocketIO ports *are* CML. I've had trouble coming across the voltage specifics for the interface in the specs (I spend most of my time in Spartan-land) but you might find that your interface is simpler than you imagined. If you're interfacing CML to CML, there's no need to try to support the "niche" LVPECL standard. The IO standards aren't favoring LVPECL across all products anymore. - John_H "Test01" <cpandya@yahoo.com> wrote in message news:eea69d6.8@webx.sUN8CHnE... > Further reading of the data sheet suggested that the part has a separate > pin to control the Vcm from 1.8v to 3.3V. > > For 1.8V Vcm, the High voltage will be 2.075V and the low voltage will be > 1.525V. > > Can the Xilinx LVPECL input take this ampitude of Vcm = 1.8V and 1100 mV > differential voltage (Vhigh = 2.075V, Vcm = 1.8V and Vlow = 1.525V)? > > Thanks.Article: 118941
interrogativo wrote:
> I'm trying to code an 'enhanced' binary-to-7segments display decoder
> with ATF750CL and WinCUPL.
>
> I'm experiencing problems using the truth table CUPL construct , so I
> wrote these test code lines:
>
> Name ATF750CL;
> Partno XXXX;
> Date Apr 2007;
> Revision 0.0 GEAT Floor Display Decoder;
> Designer mf;
> Company c companyname snc, 2007;
> Assembly Custom;
> Location Naples;
> Device v750c;
>
>
> /* Input pins */
> PIN [1..11] = [in1, in2, in3, in4, in5, in6, in7, in8, in9, in10,
> in11];
> PIN 13 = in12;
>
> /* Output pins */
> PIN [14..23] = [o1, o2, o3, o4, o5, o6, o7, o8, o9, o10];
>
> FIELD input = [in4, in3, in2, in1] ;
>
> FIELD output = [o7, o8, o9, o10] ;
> FIELD output2 = [o3, o4, o5, o6] ;
>
> /* Basically the output is a copy of the input */
> TABLE input => output {
> 'b'0000 => 'b'0000;
> 'b'0001 => 'b'0001;
> 'b'0010 => 'b'0010;
> 'b'0011 => 'b'0011;
> 'b'0100 => 'b'0100;
> 'b'0101 => 'b'0101;
> 'b'0110 => 'b'0110;
> 'b'0111 => 'b'0111;
> 'b'1000 => 'b'1000;
> 'b'1001 => 'b'1001;
> 'b'1010 => 'b'1010;
> 'b'1011 => 'b'1011;
> 'b'1100 => 'b'1100;
> 'b'1101 => 'b'1101;
> 'b'1110 => 'b'1110;
> 'b'1111 => 'b'1111;
> }
>
> /* And this also, but on different output pins */
> output2 = input;
>
> Well, 'output2' behaves correctly, while 'output' pins are always at 0
> level.
>
> Do you know why?!?!?!?!?!
Yes.
This is a result of CUPLs internal handling of numeric suffixes.
In Cupl IF the VALUE of the suffix is NUMERIC, it matters in TABLE
statements. That value is used for the COLUMN alignment
( In most languages, once a variable is named, usage does not care how
it is composed. )
So, you have two choices :
Choice A:
Remove the trailing numeric, for example, by using an underscore, or a
letter.
CUPL now uses the Field order, to assign the Table mapping
FIELD input = [in4_..in1_] ;
FIELD output = [o10_..o7_] ;
Choice B:
Keep the trailing numeric, but align the Table to column match.
Note, CUPL starts Table indexes from Zero, and allows X padding, so
the column aligned table, for 4..1 and 10..7 suffixes, looks like the
one below.
PIN = [in4..in1] ;
FIELD input = [in4..in1] ;
FIELD output = [o10..o7] ;
FIELD output2 = [o6..o3] ;
TABLE input => output {
/* 43210 A9876543210 */
'b'0000x => 'b'0000xxxxxxx;
'b'0001x => 'b'0001xxxxxxx;
'b'0010x => 'b'0010xxxxxxx;
'b'0011x => 'b'0011xxxxxxx;
'b'0100x => 'b'0100xxxxxxx;
'b'0101x => 'b'0101xxxxxxx;
'b'0110x => 'b'0110xxxxxxx;
'b'0111x => 'b'0111xxxxxxx;
'b'1000x => 'b'1000xxxxxxx;
'b'1001x => 'b'1001xxxxxxx;
'b'1010x => 'b'1010xxxxxxx;
'b'1011x => 'b'1011xxxxxxx;
'b'1100x => 'b'1100xxxxxxx;
'b'1101x => 'b'1101xxxxxxx;
'b'1110x => 'b'1110xxxxxxx;
'b'1111x => 'b'1111xxxxxxx;
}
Compiles to what you are seeking,
o7 =>in1 o8 =>in2 o9 =>in3 o10 =>in4
Article: 118942I am totally new to all this, so please forgive my naive questions. I have a quartus project that runs on a development kit. All the pins are assigned and it works correctly. I wish to add an evaluation IP core, for which I have an .edif file (targeted for my fpga). How can I import this into my verilog project, and wont it potentially cause conflict with my existing pin assignments? What steps are generally taken to use an IP (edif) file? There are also other (vhdl) files*, which I'm not sure why they were included, or if they should be added to my project. I know its impossible to tell with just a filename, so in general, what other files are normally needed to instantiate an IP core? Can VHDL files be added to a pure verilog project, or will this cause the instantiation to be troublesome? 220model.vhd 220pack.vhd altera_mf.vhd altera_mf_components.vhd file.txt stratixii_atoms.vhd stratixii_components.vhd B_limited.vhd cpu_bfm_sital_ofer_hofman1.vhd executer_simple.vhd receiver_simple.vhd bus_tester.vhd textio.vhd textio_body.vhd tb_b_limited.vhd transceiver.vhd transmitter.vhd Thanks!Article: 118943
Peter Alfke wrote: > On May 7, 12:54 pm, Test01 <cpan...@yahoo.com> wrote: > >>Further reading of the data sheet suggested that the part has a separate pin to control the Vcm from 1.8v to 3.3V. >> >>For 1.8V Vcm, the High voltage will be 2.075V and the low voltage will be 1.525V. >> >>Can the Xilinx LVPECL input take this ampitude of Vcm = 1.8V and 1100 mV differential voltage (Vhigh = 2.075V, Vcm = 1.8V and Vlow = 1.525V)? > > > The Vityex-5 data book (page 35) calls out: > Input common mode voltage between 0.6 V and 2.2 V > Differential Input voltahe: 0.1 V to 1.5 V > > But input max voltage not to exceed Vccaux by more than 200 mV, > and input min voltage not to go below minus 500 mV. > > So the answer to your question in: YES, it's ok. > Peter Alfke I think this has come up before, and the Diff Comparator is actually rail-rail capable, relative to VccAux - correct ? ISTR it is spec'd for speed over a narrower range, but can operate ok within the rails ? (which is what Peter is saying ) -jgArticle: 118944
For what it is worth, my experience so far with ISE9.1 has been good, which was a pleasant surprise after my transitions to previous major releases. For the most part, my stuff (almost all pushing the envelope) has turned in pretty much the same timing as it got with 7.1sp4 but in a fraction of the run time, and most importantly without choking on my extensive use of RPMs and RLOCs. I can't point at any examples where timing got worse under 9.1, but on the other hand, I also can't point at any where timing got noticibly better either. The only choke points to date have been ucf issues (mostly things with differential pins that are unused in the design but called out in the UCF with iostandard set). Certainly nothing that isn't easy to work around.Article: 118945
Hi Steve, I'll add some comments. First, the suggestion is not to fully open source, but to be more 'open source friendly' in portions of the systems. Mike said this "Open-sourcing XST and the various GUI apps does not mean that map/par need to be fully open-source. Providing map and par as libraries that user-written apps could call would be perfectly acceptable, given the level of trade- secrecy involved." A good example of an opposite [user unfriendly] trend is the binary Project file. What was Xilinx thinking ? [I think that's now resolved ?] You'll see from the postings that the "work around" is alive and well in FPGA development, and is is IMPORTANT to not close any "work around" pathways'. Programming has been mentioned as one area that benefits. steve.lass@xilinx.com wrote: > Mike, > > I'm probably the one you were looking for at ESC. I am not an expert on > open source software, but will give you my thoughts on why it won't > work for FPGAs: > - We have a fair amount of 3rd party software that we ship with ours > and we have no rights to distribute that source. > - We have about 250 people writing software. While I'm sure there are > 20 or 30 people that think FPGAs are cool enough to want to help out, I > doubt there are enough. > - Most of our time is spent doing new device support (and this in not just > within the map and par groups). How do we get these "volunteers" to > deliver new devices when we need them? > - We start the software for new devices about 2 years before the software > for that family is released. Making the details of a new architecture public > at that time is not an option. > - Going open source is like handing our source code over to our > competitors. Yes, but these are back-end issues, not front end ones. See Antti's post about how he had to patch the ISE design flow, in order to get a build. That's not a P&R bug, but shell/test coverage issue. > - I'm not exactly clear on who would support our customers as they run > into bugs, but I guess it would be us meaning we would have to have > people ready to fix someone else's code. > - The only other open source program for FPGAs failed: > http://www.pldesignline.com/news/164900514 Yes, I'm not sure what ST were trying to do ? An end-end open source is plainly not going to fly, on anything like leading edge FPGA designs. As run-times get faster, and incremental flows are better supported, it opens more tool-chain options to users. eg All Xilinx needs to do is define the reports well, and define the project files, tool chain scripts, seeds, and batch operations so users can control (and fix) things. None of that is releasing trade secrets, but it allows developers to push areas Xilinx cannot afford to. -jgArticle: 118946
On May 7, 5:12 pm, berton <werbu...@gmx.de> wrote: > On 7 Mai, 22:12, idp2 <ian.pei...@gmail.com> wrote: > > > > > On May 7, 1:10 pm, berton <werbu...@gmx.de> wrote: > > > > Hi! > > > > For a small project running Linux on a Virtex2pro, I need to write an > > > IP-component, that recive data from portpins and can transfer data to > > > RAM directly. > > > I'm tring to understand DMA, generated by Xilinx EDK (8.2) wizzard. > > > I think, I've understand some basics. Afer writing the datalength in > > > the register, the transfer will begin. Correct? > > > Writing datalength, source- and destinationaddress is done by the > > > driver? > > > But how cat I write data from the user_logic to the memory? > > > Hi, > > > What kind of developement board are you working with? Are you working > > with a PCI-based dev board? I've worked with a Spartan3 dev board in > > Linux and have managed to successfully achieve DMA transfers. > > > Best, > > Ian > > thanks for answering! > We are working with the xilinx xup v2p with a patched linux 2.6 kernel. Have you looked at this yet? It has a pretty good section on reading and writing to RAM that should answer most of your questions. IanArticle: 118947
On May 7, 2:05 pm, <steve.l...@xilinx.com> wrote: > - We have a fair amount of 3rd party software that we ship with ours > and we have no rights to distribute that source. The same thing was said about Netscape, and now Mozilla/Firefox is a big Open Source success story. The 3rd party software is gone, along with the licensing fees. > - We have about 250 people writing software. While I'm sure there are > 20 or 30 people that think FPGAs are cool enough to want to help out, I > doubt there are enough. There certainly aren't enough to replace your in-house team. That is not realistic. But I think you are missing one of the biggest benefits of Open Source. It is not just about writing software. It is also about helping your customers use and understand your software. There have been many times I have run into some cryptic error message, or a program that aborts for some unknown reason. If it is an Open Source package, I can grep the source for the error message, or pop it into a debugger to see why it is aborting. But if it is closed source, I often have to resort to hours or days of random fiddling with the input till I get past the problem. > - Most of our time is spent doing new device support (and this in not just > within the map and par groups). How do we get these "volunteers" to > deliver new devices when we need them? > - We start the software for new devices about 2 years before the software > for that family is released. Making the details of a new architecture public > at that time is not an option. > - Going open source is like handing our source code over to our > competitors. Most companies have "strategic" software that contains valuable IP, and encapsulate the core competencies that make that company successful. Then they have lots of "non-strategic" software that sucks up resources, but provides little or no competitive advantage. Open Sourcing your PAR software would be reckless. But Open Sourcing GUI code or device drivers may make sense. > - I'm not exactly clear on who would support our customers as they run > into bugs, but I guess it would be us meaning we would have to have > people ready to fix someone else's code. This is a known problem with a known solution. You have a "stable track", that you support, and a "development track" that is only supported by the OSS community. You only move code from the dev track to the stable track when you have reviewed the code and decided that it is good quality and has worthwhile new features. Most big Open Source projects work this way. > - The only other open source program for FPGAs failed: > http://www.pldesignline.com/news/164900514 This failed for some obvious reasons. A company can't just "stone soup" an Open Source project without putting something into the pot. It also wasn't really open. If it was, then ST wouldn't be able to just cancel it unilaterally. > There are some applications, like the schematic editor, that I would be > willing to consider going to open source if someone could show me > how that would benefit us and our customers. Well, I think the schematic editor would be a poor choice for testing the waters. I know no one that uses it. The customers who do use it are probably those most uncomfortable doing programming, and so would be the least qualified to contribute or benefit. I think a better choice would be to open source iMPACT. I doubt if it contains any strategic IP. There are six computers in the office suite where I work, including Win-XP, Linux, and FreeBSD on x86_64; and Win-XP and Linux on x86_32. ISE runs fine on all of them. iMPACT runs on precisely one (Win-XP on x86_32). It fails on all the others for various reasons. It also fails to work on VMware. These sorts of driver and OS compatibility issues are something the OSS community is quite good at fixing. > Regarless of the negative comments we receive on this newsgroup, most > customer comments on ISE 9.1i have been extremely positive. My experience with ISE 9.1i has been almost entirely positive. It is a solid improvement over 8.2. But don't get too defensive about the negative comments. Positive comments are worth little. It is the negative feedback that helps us improve and progress. If no one ever complained, we would still be living in caves.Article: 118948
mans (myname_here) wrote:
> I decided to test UltraEdit to see how good is it in reformatting
> a VHDL code and indenting smartly. To do this I installed ultraedit
> and I did a test by asking UE to reformat this code for me:
I'm not sure about UltraEdit but I do know the Zeus IDE can be
configured to do a limited amount of VHDL auto-indenting.
http://www.zeusedit.com
With a VHDL file opened in Zeus, if you use the Options, Templates
Options menu and add these to string to the template dialog:
Brace Prefix String: begin;then
Brace Postfix String: end;end if
Then assuming the | character represents the cursor, if you have
this code:
begin| <Hit enter key here>
hitting the enter key makes will result in this code:
begin
| <Cursor goes here>
end
or if you had this code:
if Rst = '1' then| <Hit enter key here>
hitting the enter key makes will result in this code:
if Rst = '1' then
| <Cursor goes here>
end if
Also FWIW the next version of Zeus will also do VHDL code folding.
Jussi Jumppanen
Author: Zeus for Windows IDE
Article: 118949On May 7, 8:45 pm, Chris <c@c> wrote: > Gordon Freeman wrote: > > I'm working with DDR SDRAM but I don't know how to choose row address > > and column address. > > Can you help me, please? > > I'm only familiar with SDRAM, DDR should be somewhat similar wrt/ > the commands you must issue (PRECHARGE, ACTIVATE, etc.) > > To get started on the basics: > > http://en.wikipedia.org/wiki/SDRAMhttp://download.micron.com/pdf/datasheets/dram/sdram/512MbSDRAM.pdfhttp://www.maxwell.com/pdf/me/app_notes/Intro_to_SDRAM.pdf > > Some technical notes worth reading: > > http://download.micron.com/pdf/technotes/ZT05.pdfhttp://download.micron.com/pdf/technotes/ZT01.pdfhttp://download.micron.com/pdf/technotes/TN4801.pdf > > An interesting article from Ars Technica: > > http://arstechnica.com/paedia/r/ram_guide/ram_guide.part2-4.html > > Hope that helps Thank you for all!
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