Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi groups, Hi Xilinx folks, For edu., I am doing some test with DRAM access with xilinx starter kit (3E/3A). I use xilinx mig 1.7 tool and I found some reference design in E. Crabill s3ak_test But it is a little bit too hard for beginners like me and I wonder if someone could post a simplistic implementation of memory access (DDR with spartan 3E and/or DDR2 with spartan 3A starter kit) . I am looking for something like a picoblaze soft proc accessing the DDR/DDR2, writing some data then reading back for control ... regards, raphArticle: 118451
not exactly the same question : is there a picoblaze assembler for linux ? wine & kcpsm3 fails with recent versions...Article: 118452
Francesco - who's the new provider you're moving too. I'd like to compare them with a couple of others. Hul Francesco <francesco_poderico@yahoo.com> wrote: > On 13 Apr, 23:35, Eric Smith <e...@brouhaha.com> wrote: > > I was hoping to download Francesco Poderico's Picoblaze C compiler > > today, but unfortunately his domain is expired. Google didn't > > turn up any other sites from which I can download it; does anyone > > know of such a location, or would anyone be willing to make it > > available online or send me a copy? (Provided that doing so > > doesn't violate any license terms.) > > > > Thanks! > > Eric > Hi, > I'm Francesco Poderico. > I'm trying to move my domain from my old provider to a newone (cheap) > Don't know why ... but this operation seems impossible because my > hosting has expired before I ask to transfer my domain??? > So if you need any help/latest version of the compiler please contact > me at francesco_poderico@yahoo.com > If in one week time from today (26/4/2007) I still did not manage ro > transfer my domain then I will create a new domain. > Regards, > FrancescoArticle: 118453
Hello, can anyone comment on setting the "Seed" value in the Fitter group under Setting? How does increasing the value produce a better fit? thanks, joeArticle: 118454
Yeah, I never could get that EDK wizard to work either. Don't know if this will help, but I compiled the non-EDK libraries in the ISE and that worked. I then used the command line to compile the EDK libraries for a particular project. Then everything was happy.Article: 118455
I had similar problem in my project. I found that if you will not use autoreload option of the PIT and reset timer inside the interrupt handler, it's work fine. I saw this "autoreloadenable" is commented out inXilinx reference code. Probably for the same reason. On Apr 26, 1:56 am, Matthew Hicks <mdhic...@uiuc.edu> wrote: > Well, I found the solution. When I regenerate the linker script the program > works 100% correctly. Forgive my newness to things like this (I come from > the high-level land of windows application programming not embedded programming), > but is this something that I should have done from the start? > > ---Matthew Hicks >Article: 118456
Yes, and it's "almost" confirmed by Xilinx. This bug is from the very begining. I was hoping that latest MPMC2 release fixes it, but it is not. We are force to use PLB2OPB bridge for now. On Apr 24, 10:12 am, js <johnsu...@gmail.com> wrote: > It seems there is problem with OPB in MPMC2 core. PPC will dead when 2 > PPC share OPB peripherals in MPMC2 coreArticle: 118457
Please tell us why this information is important to you. Most people do not care. Performance, price, and availability are sufficient. Peter Alfke ============ Pasacco wrote: > Dear > > I am looking at data book of Xilinx Virtex-II Pro > > to find ACTUAL CHIP SIZE. > > So far, I could not find yet -: > > (as an example, 900 um X 1.5 cm) > > I need a DIE (that we see in FPGA editor) size for V2P30-ff896 and > V2Pro100-ff1704. > > Can anyone help me, where I can find? Should I ask Xilinx?Article: 118458
Can i programme non-xilinx fpga through xilinx impact tool & by using xilinx parrellel four cable?Article: 118459
I have a Spartan3E Starter Kit, and I am trying to
figure out how to use the DCM to double the freq
from 50MHz to 100MHz.
I wrote a small verilog program to blink LEDs 0-3
based on the 50MHz clock, and LEDs 4-7 based on the
100MHz clock, so if it works properly, the second
group of LEDs should blink twice as fast. But it
doesn't work. LEDs 4-7 don't blink at all.
How do I specify (in verilog or UCF?) that the
"clk_100mhz" is supposed to be the CLK2X output from
the DCM? How do I specify which DCM to use, or does
the compiler figure that out for itself?
Thanks for any help.
-------------------------------------------------------------
// blink.v
module blink (
input wire clk_50mhz,
input wire clk_100mhz,
output reg[7:0] leds
);
reg [20:0] cnt50; // Counter @ 50MHz
reg [20:0] cnt100; // Counter @ 100MHz
initial begin
cnt50 <= 0;
cnt100 <= 0;
leds <= 0;
end
always @(posedge clk_50mhz) begin
cnt50 <= cnt50 + 1; // Increment counter @ 50 MHz
if (cnt50 == 0) begin
leds[3:0] <= leds[3:0] + 1; // Increment LEDs when counter
overlows
end
end
always @(posedge clk_100mhz) begin
cnt100 <= cnt100 + 1; // Increment counter @ 100 MHz
if (cnt100 == 0) begin
leds[7:4] <= leds[7:4] + 1; // Increment LEDs when counter
overlows
end
end
endmodule
-------------------------------------------------------------
# blink.ucf
NET "leds<0>" LOC = "F12" | IOSTANDARD = LVCMOS33 | SLEW = FAST |
DRIVE = 8 ;
NET "leds<1>" LOC = "E12" | IOSTANDARD = LVCMOS33 | SLEW = FAST |
DRIVE = 8 ;
NET "leds<2>" LOC = "E11" | IOSTANDARD = LVCMOS33 | SLEW = FAST |
DRIVE = 8 ;
NET "leds<3>" LOC = "F11" | IOSTANDARD = LVCMOS33 | SLEW = FAST |
DRIVE = 8 ;
NET "leds<4>" LOC = "C11" | IOSTANDARD = LVCMOS33 | SLEW = FAST |
DRIVE = 8 ;
NET "leds<5>" LOC = "D11" | IOSTANDARD = LVCMOS33 | SLEW = FAST |
DRIVE = 8 ;
NET "leds<6>" LOC = "E9" | IOSTANDARD = LVCMOS33 | SLEW = FAST |
DRIVE = 8 ;
NET "leds<7>" LOC = "F9" | IOSTANDARD = LVCMOS33 | SLEW = FAST |
DRIVE = 8 ;
NET "clk_50mhz" LOC = "C9" | IOSTANDARD = LVCMOS33;
NET "clk_50mhz" PERIOD=20.0ns HIGH 40%;
NET "clk_100mhz" PERIOD=10.0ns HIGH 50%;
-------------------------------------------------------------
Article: 118460jjlindula@hotmail.com wrote: > Hello, can anyone comment on setting the "Seed" value in the Fitter > group under Setting? How does increasing the value produce a better > fit? The seed value only initializes a random number generator that is used by the fitter algorithm to reshuffle the placement every once in a while. Thus, setting the seed value may or may not improve fitter results - it completely depends on the netlist, constraints, and of course the state of the random number generator. You should only use the seed variable to try to shave those last few nanoseconds off your critical path - and every time you change something in your design you may get either better or worse results with a given seed value. Best regards, BenArticle: 118461
Hey all, I still have one more slipway board left over to give away; email me if you want it and I'll mail it to you. If you don't know what I'm talking about, this might help: http://research.cs.berkeley.edu/project/slipway/ Please don't laugh at my pathetic PCB design skills. I also have two bare PCB's if anybody wants those. The components to populate them run about $40 from DigiKey+Mouser and it's all easy through-hole stuff. Thanks again to everybody who provided feedback and input at the conference! Next year's project is well on its way... - aArticle: 118462
It is my own design. The SPI flash is connected as in Xilinx XPAPP445 page 6 with the JTAG connected to the FPGA. But then I had to solder an extra connection as on page 11 to be able to program the SPI flash using DOS program xspi.exe. I don't want to redesign the PCB. So I hope it is programmable direct via the JTAG connector (I don't want to use the DOS-program). "Eric Crabill" <eric.crabill@xilinx.com> wrote in message news:f0qrhe$hgd1@cnn.xsj.xilinx.com... > Hi, > > The ISE iMPACT 9.1i does offer some expanded capability in this regard. > You didn't specify if your "system" is the Spartan-3E Starter Kit or if > it's another prototype/development board, or something of your own design. > If you clarify what you are working with I can then attempt to describe > your options. > > Thanks, > Eric > > "Sven" <sven@is.com> wrote in message > news:463077c7$0$90273$14726298@news.sunsite.dk... >>I have a system with a Spartan-3E with an SPI flash. I have been using the >>xspi.exe DOS program to configure the SPI flash. But now I'm wondering if >>the new ISE IMPACT 9.1 or later is able to configure the SPI flash though >>JTAG? >> >> >> >> I saw in XAPP974 for the Spartan-3A that it was possible at least for >> that device. But is the same possible for Spartan-3E? >> >> >> >> >> >> >> > >Article: 118463
Bob wrote: > I have a Spartan3E Starter Kit, and I am trying to > figure out how to use the DCM to double the freq > from 50MHz to 100MHz. > > I wrote a small verilog program to blink LEDs 0-3 > based on the 50MHz clock, and LEDs 4-7 based on the > 100MHz clock, so if it works properly, the second > group of LEDs should blink twice as fast. But it > doesn't work. LEDs 4-7 don't blink at all. > > How do I specify (in verilog or UCF?) that the > "clk_100mhz" is supposed to be the CLK2X output from > the DCM? How do I specify which DCM to use, or does > the compiler figure that out for itself? ... There are _no_ DCM instance in your code ... how do you expect it to work ? Saying in the ucf one clock is 50 and the other 100 will _NOT_ make the tools instanciate a DCM for you. Go for the easy way and use coregen to setup your DCM then instanciate it in your code. SylvainArticle: 118464
On Apr 26, 3:55 pm, "Ben Jones" <ben.jo...@xilinx.com> wrote: > "Pablo" <pbantu...@gmail.com> wrote in message > > news:1177589968.992704.94060@t39g2000prd.googlegroups.com... > > > Hi, I have written in this chat a pair of threads about Sdram and > > heap_size. I want to say that I think that heap_size cannot be changed > > with Microblaze. I need to do "xil_malloc(16*4096), but in SDRAM > > (32MB) I only can do "xil_malloc(15*4096)". Then I have increased > > "heap_size" in Linker Script since 0x400 to 0x1400000. I have put 24Mb > > for "heap_size" but it seems heap_size keeps as same as 0x400. > > Forget about xil_malloc() and just use malloc(). > > -Ben- But malloc doesn't work in Microblaze. Could you help me?. How can I do it?Article: 118465
Pablo wrote: >>> I have incresed heap_size, but it seems like sdram cannot use more >>> than 60 kbytes. >> That's no SDRAM problem. As the Xilinx EDK documentation states: >> >> "The xil_* functions operate on a 64 kilobyte buffer, and allocate >> memory from that. The size of this buffer is fixed and cannot be changed >> currently. This is a limitation of the xil_* dynamic memory allocation >> routines." [oslib_rm.pdf/EDK 8.1] >> >> I don't know if this has changed in subsequent EDK versions. The PPC405 >> malloc/calloc does not suffer from this limitation. > > Thanks. I think so. Any idea? Maybe. It depends on your application and the FPGA you use. There are a lot of details that are missing in your posts: 1. What CPU do you use, PPC405 or MicroBlaze? 2. Can you switch to PPC if you use MicroBlaze? 3. Does your application require dynamic memory allocation? 4. Can you use static memory allocation instead? 5. Do you have to use xilkernel? 6. Where do you store your application code? 7. How much memory does your application need? 8. How much is available? Depending on the answers to these questions you can: 0. Allocate your memory statically. 1. Use PPC405 + external SDRAM + malloc. 2. Implement a malloc which handles more than 64 KB. It's not complicated but memory fragmentation can become an issue on MicroBlaze as there's no MMU. 3. Use an operating system like uClinux. 4. Search for an C-based malloc library. See http://www.cyberguard.info/snapgear/tb20020530.html for a discussion of possible malloc implementations on MMU-less systems. Best regards, AndreasArticle: 118466
Je, I have fixed the problem. The software program is 100% correct. No errors. The problem is with the hardware design. When the new bitstream is generated after the hardware design is changed, I update the bitstream with software design, download, debug and then it runs. But why earlier, I changed the hardware design without generating the bitstream, XPS just pops no error? That makes me struggle with the Xilkernel coding. Thanks for reading!Article: 118467
No.Article: 118468
Dear All, Many tanks for your input. You all have been really helpful. My special tanks to Zoltan. Your function is now working like a charm in my system. Best Regards, Jos=E9 MarianoArticle: 118469
On Apr 27, 1:44 am, Adam Megacz <meg...@cs.berkeley.edu> wrote: > Hey all, > > I still have one more slipway board left over to give away; email me > if you want it and I'll mail it to you. > > If you don't know what I'm talking about, this might help: > > http://research.cs.berkeley.edu/project/slipway/ > > Please don't laugh at my pathetic PCB design skills. > > I also have two bare PCB's if anybody wants those. The components to > populate them run about $40 from DigiKey+Mouser and it's all easy > through-hole stuff. > > Thanks again to everybody who provided feedback and input at the > conference! Next year's project is well on its way... > > - a Perhaps I didn't see them, but where are the bypass caps? -Dave PollumArticle: 118470
"Pablo" <pbantunez@gmail.com> wrote in message
news:1177660639.155725.195000@t38g2000prd.googlegroups.com...
>>
>> Forget about xil_malloc() and just use malloc().
>
> But malloc doesn't work in Microblaze.
Since when? I have never had any problems with it.
>From the "LibXil Standard C Libraries" documentation:
The MicroBlaze and PPC405 C libraries support all the standard memory
management functions such as malloc(), calloc(), free()
There is nothing magical about malloc(). It's just an interface to a
dynamically-allocatable wodge of memory. It doesn't have any dependencies on
special processor features; in some environments it can make a system call
to request more memory from the underlying OS, but with an embedded system
it's more common just to have a fixed heap size.
-Ben-
Article: 118471Hi. I'm working on a V4 project, but I struggle with the timing constraints. The design has one 125MHz oscillator. In an EDK submodule, this clock is divided to 62.5MHz for the bus clock (system generator did this for me). I use the 62.5MHz clock for many of my own modules, too (at the ISE level). Until now, I only had one single timing constraint. I specified the 125MHz input as 8ns with 0.5ns jitter. I had the impression that the toolchain automatically detects that everything else is derived from it, and "does the right thing". However, I noticed that there is a problem with an external chip. The chip is a kind of FIFO memory with asynchronous OE and synchronous RD pin (and corresponding CLKIN). It has a bi-directional databus. In a clocked process (at 62.5MHz from the EDK submodule) I toggle CLKIN for the external chip (resulting in a 31.25MHz clock seen by it). In a similar clocked process, I set OE and RD as required for the bus protocol. I told ISE to register outputs directly in the IO- blocks, so I assume the external chip sees CLKIN, OE and RD change almost simultanously. To read the FIFO databus in my design, I instantiate IOBUFs. The pin data is sampled in a clocked statemachine (again, at 62.5MHz). This happens one clock cycle after having updated the OE pin, ie after 16ns. The external chip is specified to output data 10.5ns after OE. This works most of the time, but sometimes it does not. I think I need to put a timing constraint on the pins to make the flakey behaviour go away. I assume that the tools think that they have the full 16ns clock cycle for routing and logic from the I/O pin to the register. But in fact the external chip is eating 10.5ns of this budget, leaving only 5.5ns for the FPGA. I figured that I have to tell this to the tools, somehow. So I read on timing constraints and found "pad to setup", which seemed to be the most appropriate one. However, this constraint expects me to specify a clock as well and I don't have that clock. Because the clock is not an external clock (it is generated within the EDK submodule), the constraint editor won't offer it for selection. It offers my external 125MHz, but not the 62.5MHz. What is the proper way to define the timing constraint for my databus? Is "pad to setup" really what I should use, and if yes, how do I get ISE to offer the divided 62.5MHz clock in the timing constraint editor? And once I get 62.5MHz offered, what value do I have to enter for the constraint, 10.5ns (budget for external chip) or 5.5ns (budget for FPGA routing and logic)? Kind regards, MarcArticle: 118472
You make a rough guestimate yourself. The largest FPGA in a given technology will be the size of one reticle (500mm^2 to 900mm^2 depending on technology). From there the size should scale down roughly linearly in the number of CLBs. Kolja Sulimma On 25 Apr., 12:22, Pasacco <pasa...@gmail.com> wrote: > Dear > > I am looking at data book of Xilinx Virtex-II Pro > > to find ACTUAL CHIP SIZE. > > So far, I could not find yet -: > > (as an example, 900 um X 1.5 cm) > > I need a DIE (that we see in FPGA editor) size for V2P30-ff896 and > V2Pro100-ff1704. > > Can anyone help me, where I can find? Should I ask Xilinx?Article: 118473
On Apr 27, 12:47 am, Ben Twijnstra <ben.twijns...@gmail.com> wrote: > jjlind...@hotmail.com wrote: > > Hello, can anyone comment on setting the "Seed" value in the Fitter > > group under Setting? How does increasing the value produce a better > > fit? > > The seed value only initializes a random number generator that is used by > the fitter algorithm to reshuffle the placement every once in a while. > > Thus, setting the seed value may or may not improve fitter results - it > completely depends on the netlist, constraints, and of course the state of > the random number generator. You should only use the seed variable to try > to shave those last few nanoseconds off your critical path - and every time > you change something in your design you may get either better or worse > results with a given seed value. > > Best regards, > > Ben Ben's reply is correct -- the fitter seed randomly perturbs the fitting algorithms in order to generate a different result. Since no placement or routing algorithm can guarantee an optimal result (these are NP-complete problems), trying again from a different starting point can produce a slightly better or worse fit. Hence by running multiple seeds and taking the best result you can get a better answer. The average design improves by about 5% if you run several seeds rather than just taking the result of the first (default) seed. Running multiple seeds, and trying different optimization options in Quartus (there are lots), and taking the best result is automated by the Design Space Explorer (DSE) script that ships with Quartus. See http://www.altera.com/literature/hb/qts/qts_qii52008.pdf for details on how to use it. Regards, Vaughn Betz AlteraArticle: 118474
Hi,
I am implementing a direct digital frequency synthesizer in FPGA. It
follows the equation
Fo = N * Fs / (2^M)
The implementastion is done by an M-bit phase accumulator. My question
is: if 2^M cannot be divided by N, should the accumulator be cleared
to zero when wrapping around?
The VHDL code for automatical wrap-around is:
process(clk, reset)
begin
if reset='1' then
q<=(others=>'0');
elsif rising_edge(clk) then
q <= q + N;
end if;
end process;
The VHDL code for clear-to-zero wrap-around is:
process(clk, reset)
varaible:tmp: ...
begin
tmp := q + N;
if reset='1' then
q<=(others=>'0');
elsif rising_edge(clk) then
if (q > tmp) then --reach 2^M-1 and wrap around
q <= (others=>'0')
else
q<= tmp;
end if;
end if;
end process;
Which method is better ane why? Thanks in advance.
S. C.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z