Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
petrus bitbyter wrote: (snip) > All possible (eight) states have been accounted for. As you need only s= ix=20 > states, you can combine state 000 with state 100 and state 110 with sta= te=20 > 010. The leftmost bit of the state code is your output signal. See stat= e=20 > diagram below. >=20 > +--+ > 0| | > | v > .------. > | 000 |----------+ > +--------->| 100 | | > | | |<------+ | > |0 '------' | |1 > | ^ 0| | > | | | v > .------. |0 .------. > | | | | | > | 101 | | | 001 | > | |---------+ | | | > '------' | | '------' > ^ | | | > | | | |1 > |0 | | | > | | | v > .------. | | .------. > | | | +-------| | > | 111 | | | 011 | > | | | | | > '------' 1| '------' > ^ | | | > | | v | > 0| |1 .------. |1 > | +-------->| | | > | | 110 |<------+ > +------------| 010 | > '------' > | ^ > 1| | > +--+ > created by Andy=B4s ASCII-Circuit v1.24.140803 Beta www.tech-chat.de >=20 > petrus bitbyter This is exactly the state diagram I drew before answering=20 the post. Nice work.Article: 118601
Xesium wrote: > I forgot to mention that I'm using ISE foundation 8.2i. > > On Mar 17, 11:35 am, "Xesium" <amirhossein.gholamip...@gmail.com> > wrote: >> Hi, >> I do a post place and route simulation using modelsim. To estimate the >> power I generate dump.vcd file during simulation so that I can get the >> power numbers using XPower. The problem is that XPower at the very end >> of its execution crashes and it aborts, giving me this message: >> >> FATAL_ERROR:Power:vcdParser.y:815: - PowerVcd_Parser: line 669374017: >> No valid identifier code was specified for scalar value change. >> Identifier provided was jL:0nL: Process will terminate. >> To resolve this error, please consult the Answers Database and other >> online resources athttp://support.xilinx.com. >> >> The size of the vcd file is about 5GB. So there is no way that I can >> open it to get a better idea of the problem. >> Do you have any idea why I get this error message? Can it be a problem >> of my design size? or can it be a problem with the design itself? >> Because the simulation works just fine so I don't know why XPower >> should crash. >> My design is roughly about 8000-9000 slices. >> >> Thanks, > > File sizes over 4 GB are not supported on 32 bit platforms -- are you running XPower on a 64 bit platform? Cheers, RussArticle: 118602
Peter Alfke wrote: > I think 5 mA is an unnecessaily low limit. 10 mA is pefectly safe, > even if it lasts forever. OK. I suppose the official Xilinx documents (including answer records) have to be written conservatively. > Don't forget, there is also a diode drop between the input and Vcco. I was already taking that into account in my calculation. Thanks for the advice! EricArticle: 118603
John Popelish wrote: > This is exactly the state diagram I drew before answering > the post. Nice work. This has nothing to do with comp.lang.c. Please remove that newsgroup from your distribution. BrianArticle: 118604
Default User wrote: > John Popelish wrote: > >> This is exactly the state diagram I drew before answering >> the post. Nice work. > > This has nothing to do with comp.lang.c. Please remove that newsgroup > from your distribution. I don't know where the original poster is reading this thread. You could make this discussion relevant by translating the algorithm into C.Article: 118605
Hi Peter, Peter Alfke wrote: > Do not cascade the DCMs. Drive both in parallel from the 100 MHz > oscillator. Any qualifications on this statement? "don't cascade DCMs, full stop"? Or "don't do it if you don't have to, at high clock frequencies"? The reason I ask is that almost every design generated by the EDK Base System Builder tool cascade DCMs, in the same basic structure: 1. input DCM to up/down sample board clock 2. DCM to generate phases of DDR clock 3. DCM to generate phase shifted DDR feedback clock (2) is always cascaded directly from (1), with the lock -> reset lines hooked up directly (inverted). Only time this has ever given me problems is in simulation, due to a hardcoded requirement in the simlibs DCM model for 3 input clock cycles before releasing DCM reset. Never had any problems on actual boards, up to about 125 MHz. Regards, JohnArticle: 118606
petrus bitbyter wrote:
>
... snip ...
> +--+
> 0| |
> | v
> .------.
> | 000 |----------+
> +--------->| 100 | |
> | | |<------+ |
> |0 '------' | |1
> | ^ 0| |
> | | | v
> .------. |0 .------.
> | | | | |
> | 101 | | | 001 |
> | |---------+ | | |
> '------' | | '------'
> ^ | | |
> | | | |1
> |0 | | |
> | | | v
> .------. | | .------.
> | | | +-------| |
> | 111 | | | 011 |
> | | | | |
> '------' 1| '------'
> ^ | | |
> | | v |
> 0| |1 .------. |1
> | +-------->| | |
> | | 110 |<------+
> +------------| 010 |
> '------'
> | ^
> 1| |
> +--+
Obviously wrong.
--
<http://www.cs.auckland.ac.nz/~pgut001/pubs/vista_cost.txt>
<http://www.securityfocus.com/columnists/423>
<http://www.aaxnet.com/editor/edit043.html>
<http://kadaitcha.cx/vista/dogsbreakfast/index.html>
cbfalconer at maineline dot net
--
Posted via a free Usenet account from http://www.teranews.com
Article: 118607What has this newsgroup come to? A series of 31 postings about a trivial design that (in Xilinx parlance) fits into half a CLB. There may be a dozen different implementations, but they are all equally trivial. Is there nothing better to discuss? Peter Alfke On Apr 30, 4:18 pm, John Popelish <jpopel...@rica.net> wrote: > Default User wrote: > > John Popelish wrote: > > >> This is exactly the state diagram I drew before answering > >> the post. Nice work. > > > This has nothing to do with comp.lang.c. Please remove that newsgroup > > from your distribution. > > I don't know where the original poster is reading this thread. > > You could make this discussion relevant by translating the > algorithm into C.Article: 118608
tersono wrote:
> Mit der Dummheit kämpfen Götter selbst vergebens.
Ja, Ja, ... Schiller also noticed that
"It does not prove a thing to be right
because the majority say it is so."
-- Mike Treseler
Article: 118609Peter Alfke wrote: > What has this newsgroup come to? > A series of 31 postings about a trivial design that (in Xilinx > parlance) fits into half a CLB. > There may be a dozen different implementations, but they are all > equally trivial. > Is there nothing better to discuss? > Peter Alfke Well, since you ask, there IS another thread on Xilinx Software Quality, that could use some more postings, - no comment from Xilinx yet :) ? -jgArticle: 118610
Sorry to waste everyone's bandwidth, but it needs to be said (in good fun because I may want to work for Xilinx someday) Oh, BURN! ---Matthew Hicks > Peter Alfke wrote: > >> What has this newsgroup come to? >> A series of 31 postings about a trivial design that (in Xilinx >> parlance) fits into half a CLB. >> There may be a dozen different implementations, but they are all >> equally trivial. >> Is there nothing better to discuss? >> Peter Alfke > Well, since you ask, there IS another thread on Xilinx Software > Quality, that could use some more postings, - no comment from Xilinx > yet :) ? > > -jg >Article: 118611
On 30 Apr., 22:09, rpons...@gmail.com wrote: > there is one example in sdram directory of s3ask_test design (follow > 3A reference design in xilinx web site), but this is only an > implementation of the DDR2 testbench ; the one that is generated with > mig 1.7. (a led blink if memory fails) hi thanks.. I looked at the website and from the descriptions did not identify any designs for DDR2, i will look again.. but the MIG "led blink" is no what I look for actually.. AnttiArticle: 118612
On 30 Apr., 16:56, Martin Thompson <martin.j.thomp...@trw.com> wrote: > Antti <Antti.Luk...@xilant.com> writes: > > Hi > > > I really dont understand why Xilinx isnt hiring people who can develop > > and test software? > > Is the world-wide shortage of engineers really that bad? > > > Latest example: > > MicroBlaze Working Design with EDK 8.1 > > Update to EDK 8.2 -> DDR Memory failing (was working with 8.1) > > Update to EDK 9.1 -> : > > > ./synthesis.sh: line 2: $'\r': command not found > > I had that one too - I faffed around for a bit to sort it. I can;t > find my notes, but I think I had to downgrade my cygwin bash IIRC, much like > we had to do with make in a previous incarnation. To be fair, it > broke on my own .bashrc as well - I may have ticked the wrong box on > the Cygwin install for DOS/Unix file formats... > > I currently have: > $ bash --version > GNU bash, version 2.05.0(1)-release (i686-pc-cygwin) > Copyright 2000 Free Software Foundation, Inc. > > Cheers, > Martin > > -- > martin.j.thomp...@trw.com > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://www.conekt.net/electronics.html I have messed with my cygwin at all... still same issue. wrote some .bat file to start synthesis where EDK stops build. annoying but useable workaround.. AnttiArticle: 118613
On May 1, 12:28 am, Mike Treseler <mike_trese...@comcast.net> wrote: > axr0284 wrote: > > My question is, > > is it worth using these expensive tools when there are also synthesis > > tools created by the manufacturers of the FPGAs such as xilinx ISE > > which is free. > > I would not buy special synthesis tools > until I found a problem with the vendor tools. > I find that good simulation tools get the > most use and provide the most value during design. > I need synthesis to check fit and fmax, > but edit, sim, edit, sim,... is the tight loop. > > > Secondly are the first tools much much more efficient than the > > ones xilinx offers such that the gain obtained from them offsets the > > cost of the tool. Thirdly which one is better for Xilinx FPGAs. > > I know of one case where a Mentor tool > fit a design that wouldn't fit with ise. > I know of no such cases with quartus, > but I don't doubt that they exist. > > -- Mike Treseler Hi, For FPGA's I'd rate Synopsys DC -FPGA/ Synopsys FPGA compiler and Synplify Pro. These tools are really goor and provide excellent synthesis results. The Vendor provided tools are also okay, in terms of the IP cores supplied and other P&R options. Synopsys DC has built- in Design Ware products that are good when implementing complex designs. In terms of compilation time and speed, both these tools are equally good. I've used the Mentor Graphics tools for FPGA, namely, Precision Synthesis, Leonardo Spectrum. They're okay, but I didnt get good synthesis results from them. Regarding Xilinx and Altera, I prefer Xilinx coz the ISE pack is good in terms of features. Regards, AbrahamArticle: 118614
On Apr 30, 9:35 pm, "Ron Huizen" <rhui...@bittware.com> wrote: > As far as I know, VMetro does not have any TS201 based boards. > > However, you will find ones atwww.bittware.comwith TS201s and PCI > interfaces. > > ----- > Ron Huizen > BittWare > > "colin" <colin_toog...@yahoo.com> wrote in message > > news:1177922732.403279.153230@u30g2000hsc.googlegroups.com... > > > On 28 Apr, 09:24, eapen.abra...@gmail.com wrote: > >> Hi, > > >> Has anyone tried bridging the TS201 TigerSHARC with the PLX 9656 > >> device? I'm trying to implement this in a current project and need > >> details. The bridging is done via an Altera FPGA which also has to > >> have custom logic for other functions such as Ethernet, sFPDP,etc. > > >> I know that the TS201 core runs at 600 MHz and the I/O bus at around > >> 83.5 MHz. But at what speed does the PLX 9656 local bus run? Can the > >> TS201 be connected directly to the PLX chip? Are there anyother > >> alternatives to the PLX chip? > > > If your budget can cope, I suggestwww.vmetro.comfor both of your > > threads roday Thx for the replies. Well, I do know bout Vmetro and Bittware. But my client does not want to use these chips. I dont know why they don't want to use the SharcFin chip. So am stuck with the PLX and the FPGA.Article: 118615
"Pablo" <pbantunez@gmail.com> wrote in message
news:1177935760.679134.181020@e65g2000hsc.googlegroups.com...
> Well I have increased heap_size and it seems ok, but when I add more
> code to my project it fails again and I know I have quite a lot memory
> since I have downloaded the app to the sdram with 32MB. I think malloc
> works abnormally. In some cases I have seen it work fine and in
> anothers it doesn`t work.
What evidence do you have that malloc() is not working, vs. something is
your code is not working? Do you know that your code works when compiled for
another system? The standard C library functions in the Xilinx toolchain are
not proprietary. They are basically the same routines you'd get when using
any other GNU-based cross-compiler.
So I would first of all try to isolate the failure in your code and see why
it is failing. The most likely cause in an embedded system is running out of
stack space, rather than heap space. This is particularly true when porting
some software from a PC environment to an embedded system, because most PC
programmers are extremely lazy about memory management and will happily
allocated megabytes of temporary data on the stack without batting an
eyelid...
Heap exhaustion is easy to catch because malloc() returns an error code.
Stack overflows/corruption are much nastier and can have all sorts of
hard-to-track-down side effects.
Cheers,
-Ben-
Article: 118616Guys, I saw this on Slashdot and thought of CAF. The PLAICE is an open source hardware and software project developing a powerful in-circuit development tool that combines in one device the features of a FLASH Programmer, Memory Emulator, and High Speed Multi-Channel Logic Analyzer. It runs uClinux. The logic analyzer features up to 200MHz sampling rates and up to 32 input channels. http://hardware.slashdot.org/hardware/07/05/01/0017244.shtml http://flash-plaice.wikispaces.com/ Cheers, Syms.Article: 118617
On 1 Mai, 11:02, "Symon" <symon_bre...@hotmail.com> wrote: > Guys, > > I saw this on Slashdot and thought of CAF. > > The PLAICE is an open source hardware and software project developing a > powerful in-circuit development tool that combines in one device the > features of a FLASH Programmer, Memory Emulator, and High Speed > Multi-Channel Logic Analyzer. It runs uClinux. The logic analyzer features > up to 200MHz sampling rates and up to 32 input channels. > > http://hardware.slashdot.org/hardware/07/05/01/0017244.shtmlhttp://flash-plaice.wikispaces.com/ > > Cheers, Syms. interesting ;) but currently the project seems to be just another wrapper around the sump project... AnttiArticle: 118618
"Antti" <Antti.Lukats@xilant.com> wrote in message news:1178011164.795509.202820@e65g2000hsc.googlegroups.com... > On 1 Mai, 11:02, "Symon" <symon_bre...@hotmail.com> wrote: >> Guys, >> >> The PLAICE is an open source hardware and software project developing a >> powerful in-circuit development tool that combines in one device the >> features of a FLASH Programmer, Memory Emulator, and High Speed >> Multi-Channel Logic Analyzer. It runs uClinux. The logic analyzer >> features >> up to 200MHz sampling rates and up to 32 input channels. >> > > interesting ;) > > but currently the project seems to be just another wrapper around the > sump project... > > Antti > > Ah, you mean this http://de.sump.org/projects/ ? It would seem that 'open source' hardware is getting more press recently, I think the cheap dev. boards that FPGA vendors are selling may have something to do with this. Syms. p.s. I'm not sure everyone will be totally comfortable with the soggy moggy pictures? http://de.sump.org/projects/waterwall/archive/ :-)Article: 118619
"axr0284" <axr0284@yahoo.com> wrote in message news:1177957376.581213.205820@n59g2000hsh.googlegroups.com... > Hi everybody, > I would like to obtain people's opinion on the use of different > synthesis tools to target FPGA designs. I am thinking of tools from > Synopsys, Mentor graphics and synplicity. If there are others, I would > like to know. These are excellent for targetting ASIC designs where > every little space and power dissipation is critical. My question is, > is it worth using these expensive tools when there are also synthesis > tools created by the manufacturers of the FPGAs such as xilinx ISE > which is free. If you are looking for a synthesis tool to enable ASIC prototyping on an FPGA then you probably have to go for the more expensive tools like Precision and Synplify. Precision (and I assume Synplify) support all sorts of gated clocks/clock muxing/ripple counter, SDC constraints, Synopsys DesignWare and some SystemVerilog. >(I use xilinx exclusively. Sorry to the Altera fans out > there). Secondly are the first tools much much more efficient than the > ones xilinx offers such that the gain obtained from them offsets the > cost of the tool. That all depends on the design but in general you can say that for large designs the more expensive tools have the upper hand. They also provide more control, better inferring capability (memory/DSP) and better debug capability (e.g. analysing critical path). > Thirdly which one is better for Xilinx FPGAs. Impossible to say, simply get as many designs as you can find, evaluation licenses for Precision and Synplicity and try them out. You should also investigate what each tool can do in terms of constraining, language support, inferring capability, ASIC prototyping (if you need it), debugging, level of support (simply log a bug/enhancement and see how quick they responds), number of updates etc etc. Due to the level of R&D invested in these product (including XST/QIS) I suspect that you have to repeat this process every year! I would also suggest you ignore any posting saying that tool A is better than tool B unless the person can back it up with an extensive up2date benchmarks :-) Hans www.ht-lab.com > Thanks > a lot for your time, > Amish >Article: 118620
"Antti" <Antti.Lukats@xilant.com> wrote in message news:1177923346.082624.133910@y80g2000hsf.googlegroups.com... > Hi > > I really dont understand why Xilinx isnt hiring people who can develop > and test software? > Is the world-wide shortage of engineers really that bad? > I don't understand how they manage to write stuff that crashes other apps. I run? And why don't they do regression testing. http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=24066 just bit me. "This problem is a regression from version 8.2i SP2". And why-o-why does the edit block command in FPGA editor always come up sized as if the block is a CLB from a Spartan II. Every time I open a block, I spend 5-10 seconds resizing and zooming. Others apps seem to be able to remember what size I made pop-up windows. Grrr. Syms.Article: 118621
On May 1, 10:28 am, "Ben Jones" <ben.jo...@xilinx.com> wrote: > "Pablo" <pbantu...@gmail.com> wrote in message > > news:1177935760.679134.181020@e65g2000hsc.googlegroups.com... > > > Well I have increased heap_size and it seems ok, but when I add more > > code to my project it fails again and I know I have quite a lot memory > > since I have downloaded the app to the sdram with 32MB. I think malloc > > works abnormally. In some cases I have seen it work fine and in > > anothers it doesn`t work. > > What evidence do you have that malloc() is not working, vs. something is > your code is not working? Do you know that your code works when compiled for > another system? The standard C library functions in the Xilinx toolchain are > not proprietary. They are basically the same routines you'd get when using > any other GNU-based cross-compiler. > > So I would first of all try to isolate the failure in your code and see why > it is failing. The most likely cause in an embedded system is running out of > stack space, rather than heap space. This is particularly true when porting > some software from a PC environment to an embedded system, because most PC > programmers are extremely lazy about memory management and will happily > allocated megabytes of temporary data on the stack without batting an > eyelid... > > Heap exhaustion is easy to catch because malloc() returns an error code. > Stack overflows/corruption are much nastier and can have all sorts of > hard-to-track-down side effects. > > Cheers, > > -Ben- Well, you are ok. I am porting some software from a PC environment to an embedded system. But I don`t understand this: - First I crate a simple main.c with a malloc(128*1024) . That is, I reserve memory for 128k. I edit linker script and program runs OK. - Second I increase my code, adding some lines and four files. But I do ,at the first, the same memory reserve: malloc(128*1024), and I edit the linker script with the same size as the example above. But in this case malloc returns NULL. I suppose I have to learn quite a lot, but I cannot understand how Malloc works with first example and not for the second one. But, I must be thankful for your constructive commentary. Regards, PabloArticle: 118622
Hi,
I want to learn using textio. Here I use Read data from scr.txt to IP
core RAM and Write them to the text1.txt. I wrote the codes here but
it doesn't work. Any suggestions about this is very appreciated.
One more thing, when i use Modelsim to Run by step. It alway gives the
error information and cannot finish the simulation. I don't what it
means.
******************************************************
Trace back: Error opening C:/Documents and Settings/zq500/Local
Settings/Temp/xil_1700_6
# while executing
# "error $winName"
# (procedure "view" line 82)
# invoked from within
# "view source"
# (procedure "vsimcmd::viewProcessSource" line 2)
# invoked from within
# "vsimcmd::viewProcessSource /check/uut/u0/select_outputb"
# ("after" script)
# 2: ::tkerror {Error opening C:/Documents and Settings/zq500/Local
Settings/Temp/xil_1700_6}
# 1: ::bgerror {Error opening C:/Documents and Settings/zq500/Local
Settings/Temp/xil_1700_6}
**************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity check is
end check;
architecture serial of check is
component checkram
port (
addra: IN std_logic_VECTOR(2 downto 0);
addrb: IN std_logic_VECTOR(2 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(7 downto 0);
doutb: OUT std_logic_VECTOR(7 downto 0);
wea: IN std_logic);
end component;
signal addra: std_logic_vector(2 downto 0):=(others=>'0');
signal addrb: std_logic_vector(2 downto 0):=(others=>'0');
signal dina: std_logic_vector(7 downto 0) :=(others=>'0');
signal doutb: std_logic_vector(7 downto 0) :=(others=>'0');
signal wea: std_logic :='1';
signal wrd: std_logic :='0';
signal clk : std_logic :='0';
signal reset: std_logic :='1';
file from_file:text open READ_MODE is "src.txt";
file to_text:text open WRITE_MODE is " text1.txt";
begin
UUT:checkram port map
(
addra => addra,
addrb => addrb,
clka => clk,
clkb => clk,
dina => dina,
doutb => doutb,
wea =>wea
);
clock_process: PROCESS
BEGIN
clk <= NOT (clk);
WAIT FOR 5 ns;
END PROCESS clock_process;
reset <= '0' after 1 ns;
ramRd: process (clk,reset)
variable buf_out,buf_in:line;
variable num: std_logic_vector(7 downto 0):=(others=>'0');
variable iptaddr: std_logic_vector(2 downto 0):=(others=>'0');
begin
if reset='1' then
iptaddr :=(others=>'0');
elsif clk'event and clk='1' then
while not (endfile(from_file))loop
READLINE(from_file,buf_out);
READ(buf_out,num);
WRITE (buf_in,doutb);
WRITELINE(to_text,buf_in);
wea <='1';
addra<=iptaddr;
dina<= num;
iptaddr:=iptaddr+"1";
end loop;
end if;
end process;
---------------------------------------
addPro: process (addra,reset)
begin
if reset='1' then
wea<='1';
wrd<='0';
elsif addra = "111" then
wea<='0';
wrd <='1';
end if;
end process;
----------------------------------------
output: process(clk,wrd,reset)
variable buf_in:line;
variable iptaddr: std_logic_vector(2 downto 0):=(others=>'0');
begin
if reset='1' then
addrb <=(others=>'0');
elsif clk'event and clk ='1' then
if wrd <= '1' then
addrb <= addrb+"001";
end if;
WRITE (buf_in,doutb);
WRITELINE(to_text,buf_in);
end if;
end process;
end serial;
Article: 118623On May 1, 5:02 am, "HT-Lab" <han...@ht-lab.com> wrote: > "axr0284" <axr0...@yahoo.com> wrote in message > > news:1177957376.581213.205820@n59g2000hsh.googlegroups.com... > > > Hi everybody, > > I would like to obtain people's opinion on the use of different > > synthesis tools to target FPGA designs. I am thinking of tools from > > Synopsys, Mentor graphics and synplicity. If there are others, I would > > like to know. These are excellent for targetting ASIC designs where > > every little space and power dissipation is critical. My question is, > > is it worth using these expensive tools when there are also synthesis > > tools created by the manufacturers of the FPGAs such as xilinx ISE > > which is free. > > If you are looking for a synthesis tool to enable ASIC prototyping on an > FPGA then you probably have to go for the more expensive tools like > Precision and Synplify. Precision (and I assume Synplify) support all sorts > of gated clocks/clock muxing/ripple counter, SDC constraints, Synopsys > DesignWare and some SystemVerilog. > > >(I use xilinx exclusively. Sorry to the Altera fans out > > there). Secondly are the first tools much much more efficient than the > > ones xilinx offers such that the gain obtained from them offsets the > > cost of the tool. > > That all depends on the design but in general you can say that for large > designs the more expensive tools have the upper hand. They also provide more > control, better inferring capability (memory/DSP) and better debug > capability (e.g. analysing critical path). > > > Thirdly which one is better for Xilinx FPGAs. > > Impossible to say, simply get as many designs as you can find, evaluation > licenses for Precision and Synplicity and try them out. You should also > investigate what each tool can do in terms of constraining, language > support, inferring capability, ASIC prototyping (if you need it), debugging, > level of support (simply log a bug/enhancement and see how quick they > responds), number of updates etc etc. > > Due to the level of R&D invested in these product (including XST/QIS) I > suspect that you have to repeat this process every year! I would also > suggest you ignore any posting saying that tool A is better than tool B > unless the person can back it up with an extensive up2date benchmarks :-) > > Hanswww.ht-lab.com > > > Thanks > > a lot for your time, > > Amish Unless you are prototyping an ASIC (and want portability of the code to ASIC tools), I would not recommend Synopsys for FPGA synthesis. Their support of VHDL is hideous (they still have bugs handling direct entity instantiations, even in their simulator, and that's a '93 feature, 14 years old!). They cannot infer memory from arrays. So things like records, arrays, integers, booleans, and enumerated state types must be manually converted to SLV before being stored in instantiated RAMs. And just try debugging your design in the simulator when your data is spread out bitwise among a host of memory primitives, instead of neatly stored in an array. Synplify Pro and Precision are very good products that generally give better QOR, and have better VHDL language coverage than the FPGA vendors' synthesis tools. AndyArticle: 118624
Thanks for the insight everybody. I will definitly do a more thorough analysis of all the tools available if needed. For now we use XST where I work and it seems to work fine. But in the future as designs get bigger, you never know, we might need to migrate to a tool that provide better debuggin capabilities. Thanks a lot, Amish
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z