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On 4 Mai, 10:51, mludwig <gye...@gmail.com> wrote: > On May 4, 10:13 am, Antti <Antti.Luk...@xilant.com> wrote: > > > On 4 Mai, 02:37, mludwig <gye...@gmail.com> wrote: > > > > I just wanted to try the JTAG Loader tools provided with PicoBlaze and > > > I cannot run neither hex2svf.exe, nor hex2svfsetup.exe. I get "The > > > system cannot execute the specified program" message in the Windows XP > > > Command Prompt. Am I missing something here? Has anybody been able to > > > run these tools and program the instruction ROM via JTAG? > > > > Thanks, > > > they do work check if maybe some DLL are missing > > > Antti > > Hmmm, no mention of required libraries in the user guide. Do these > tools need Xilinx ISE? I have 9.1SP3 webpack installed. maybe some cygwin libs missing? you can always use "showdep" to see why winxp programs dont start google "windows showdep" .... first hit,or direct http://www.zdnet.de/downloads/prg/k/b/de0AKB-wc.html AnttiArticle: 118826
On Fri, 04 May 2007 03:20:18 GMT, Phil Hays <invalid@dont.spam> wrote:
>Udo wrote:
>> I'm using XP and paths are separated with backslashes. But Tcl uses
>> slashes.
Indeed it does.
>Yes, I suggest you use "file join". This standard Tcl command creates an
>OS correct path for any OS.
Not quite. [file join] constructs Tcl-style (/-separated)
pathnames from components. The really nice thing about [file join]
is that it's very tolerant of all sorts of input. But it does NOT
fix-up the backslashes for Windows.
For example:
% file join /home work play
/home/work/play
% file join /home/ work/ play/
/home/work/play
% file join /home// work play///
/home/work/play
These /-style names work just fine within Tcl, and as
arguments to any Tcl-aware program. But of course they
won't work as input to an ordinary Windows program.
If you really, really need a Win32 filename (for example,
because you're trying to set an environment variable,
or any other situation where the filename will be
processed by a non-Tcl-aware program) you can always
use [file nativename]:
% file nativename /home/work
\home\work
(of course, on *nix it would give you a /-separated
name).
Be very careful, though, because backslash has special
meaning to Tcl. if you type a backslash-separated
name interactively, you'll need to double-up the
backslashes:
% file nativename \home\work
homework
% file nativename \\home\\work
\home\work
or alternatively, enclose the offending string in
curly brackets:
% file nativename {\home\work}
\home\work
Generally, as long as you are working entirely within the
Tcl environment the best advice is...
- in your own scripts and commands, use /-style names
- if you get a \-style name from somewhere else (e.g. an
environment variable, or from the contents of another file)
then you can use it, but DON'T type such names interactively
- if you need to generate a \-style name for use by non-Tcl
programs or to put into Win environment variables, use
Tcl /-style names but use [file nativename] to do a final
conversion to \-style before you make external use of the name.
hth
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 118827Hi, I am looking for a new powerful FPGA board for video processing algorithm development. My work will focue on the architecture design of video signal processing algorithms. I hope the other parts are ready and convinient to use. It should have video input/output and big FPGA chip and big memory. It also will be better if there is a procesor on it. I should appreaciate any helpful commonts and information. Thanks MichaelArticle: 118828
HT-Lab wrote: > "Johannes Hausensteiner" <johannes.hausensteiner@pcl.at> wrote in message > news:1178119117.891772@news.aic.at... >> Tom Dillon wrote: >>> Johannes Hausensteiner wrote: >>>> I have a state machine design with big case statments (VHDL). When >>>> I compile with Precision RTL it infers block ROM, which exceeds the >>>> actual number of EBR blocks in my FPGA. I am using a Lattice LFECP10 >>>> chip. How can I tell Precision not to infer ROM but implement in >>>> logic? >>>> >>> This how-to addresses this issue in Verilog, should be similar in >>> VHDL. >>> >>> http://decass.dilloneng.com/documents/howto/ram_inference/ >>> >>> Tom >>> >> Thanks for the link, but I ended up with the same code as given in the >> Precision user manual, which I tried before and which does not what I >> want. I think this article focuses on block RAM vs. distributed RAM. I >> want Precision to implement no RAM at all but normal logic (LUTs). >> >> Johannes > > Hi Johannes, > > Have a look at the use_resource attribute, this might enable you to force > Precision into using LUTs, alternatively, sign up for the beta release which > has a very nice graphical resource manager. Just select the instance, click > on the pulldown button and change the ram to LUTs. > > Hans > www.ht-lab.com > Thanks a lot for the hint; this is the right path. When doing this from within the Precision IDE it seems to work (the value of the use_resource property is "LOGIC", not "LUT"). But I cannot make this work from within ispLEVER. Obviously there are two other ways to specify an attribute: one is inside the VHDL source file with a special "attribute" statement, the other is via the precision command line. I was not successful to put it into the VHDL source. No matter what I type there is always a syntax error. From what I read from the Precision Reference Manual (precisionsn_ref.pdf, Precision Synthesis Reference Manual, 2005c February 2006, page 2-30 = page 50 of 404 in the .PDF) it should be: attribute USE_RESOURCE : string; attribute USE_RESOURCE of <signal name> : instance is LOGIC; I put this into the "global section" of my VHDL source file (between "architecture" and "begin"). I always get >Syntax error at or near "instance"< When trying to set it on the command line I was not yet successful either. There are TCL scripts generated on the fly and other TCL scripts included - I could not yet find the place where the actual command line is put together. JohannesArticle: 118829
Gabor <gabor@alacron.com> writes: > > In my experience (using XST) if I assign Z to a pad, the net is > stripped from > the design and then anything attached to the net in the UCF file goes > away, too. How do you keep your "dummy_net" from being > removed? > Can you instantiate OBUFTs and wire the tristate input to an input pin that you know is static GND (or VCC via an inverter)? Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 118830
Andy <jonesandy@comcast.net> writes: > On May 3, 7:22 am, Antti <Antti.Luk...@xilant.com> wrote: >> YOU CAN NOT USE "wait" statement for FPGA design. >> YOU CAN NOT USE "wait" statement for FPGA design. >> YOU CAN NOT USE "wait" statement for FPGA design. >> YOU CAN NOT USE "wait" statement for FPGA design. >> YOU CAN NOT USE "wait" statement for FPGA design. >> >> read the above 5 times, and try again. >> >> Antti > > WRONG! > > You cannot wait for TIME in synthesizable code. You can wait until > rising_edge(clk)! Not usually the best coding style, but it can be > done and is accepted by most synthesis tools. Question: Why is it not the best coding style? I've always been told that and have always stuck to if rising_edge(clk) then end if; but you save a level of indent if you just put a wait until rising_edge(clk) at the top of your process. You can even put an if reset='1' at the end for you sync resets. I assume it comes from the fact that in the old days synth tools didn't like it? Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 118831
"Michael" <hm512@york.ac.uk> wrote in message news:f1euoa$5ie$1@netty.york.ac.uk... > Hi, > I am looking for a new powerful FPGA board for video processing algorithm development. My work will focue on the architecture > design of video signal processing algorithms. I hope the other parts are ready and convinient to use. It should have video > input/output and big FPGA chip and big memory. It also will be better if there is a procesor on it. I should appreaciate any > helpful commonts and information. > Thanks > Michael http://www.imageproc.com/xilinx.php MH.Article: 118832
On 4 Mai, 10:01, "Ken Soon" <c...@xilinx.com> wrote: > "Paul" <pauljbenn...@gmail.com> wrote in message > Input & output resolutions and frame rates? I would like to start with > 640x480 and 60Hz since it seems basic enough to start with this (though i > would like to cater to lower resolution with progress) > Gabor mentioned that he did it with Spartan 2e 400 which took in two 640 x > 480 inputs, stores them in single-data-rate SDRAM and then combines them > into a scaled 1024 by 768 output at 60 fps. As another poster mentioned: If input and output run at the same resolution and frame rate you only need to store a small number of video lines. You can do that in internal memory. Start with a project that samples the video input and directly outputs it in the desired format. Than do the same with one video line delay. Once you have that working your scaler is more or less done. Kolja SulimmaArticle: 118833
On Fri, 4 May 2007 10:35:07 +0100, "Michael" <hm512@york.ac.uk> wrote: >Hi, >I am looking for a new powerful FPGA board for video processing algorithm >development. My work will focue on the architecture design of video signal >processing algorithms. I hope the other parts are ready and convinient to >use. It should have video input/output and big FPGA chip and big memory. It >also will be better if there is a procesor on it. I should appreaciate any >helpful commonts and information. >Thanks >Michael > http://www.microtronix.com/products/?product_id=96Article: 118834
On 4 May, 01:31, Patrick Dubois <prdub...@gmail.com> wrote: > What are people doing when using temac on the V4? Is everyone > using lwIP in sockets mode? I use sockets. Cheers, JonArticle: 118835
OK... think time domain signal... say your signal x = [1 10 5 3] and
you want to upsample this to twice the sampling frequency.... if you
did a simple linear interpolation you'd get x_upsampled = [1 5.5 10
7.5 5 4 3 ?] that last datapoint{?} is kinda arbitrary, presumably
you'd just set it to 3. However, signals are defined as a sum of
sinusoids, and generally they fit that model fairly well - when you
have something that doesn't, it takes more sinusoids to fit it.. thats
the general theory behind a fourier transform, right? So linear
interpolation isn't really you're best solution. You can
mathematically prove that if you had an infinitely long signal, and an
infinitely perfect low pass filter, the "perfect" upsampling is done
by inserting zeros x_zero = [1 0 10 0 5 0 3 0], and low pass
fitlering it. Obviously, neither the infinite sequence or the perfect
LPF is realistic. If you do the math (or plug it into matlab), the
FFT of x (shfited to place zero frequency in the center), X=[-7 -4+7j
19 -4-7j] If you take the FFT of x_zero, X_ZERO = [19 -4-7j -7
-4+7j 19 -4-7j -7 -4+7j] Note, this is simply X repeated.
So how do you get back your correct frequency spectrum? An ideal LPF
returns X_UPSAMPLE=[0 0 -7 -4+7j 19 -4-7j 0 0]. Now note
this... if you use matlab and take the inverse FFT of this (the
shifted version of this actually) you get [1.0000 5.8107
10.0000 8.6391 5.0000 3.6893 3.0000 0.8609]
Actually... you get this divided by 2 (you need to multiply by your
upsampling facor, that comes out in the math) with a risidual
imaginary part due to the fact that it's an even length sequence, so
you just look at the real part. Point being however, note that the
interpolated values are NOT what you get using straight linear
interpolation. this is because this method takes into account the
curvature of the rest of the sequence and stuff.
That being said.... for this project, I would imagine that simple
linear interpolation is plenty adequate! A 2 dimensional version of
this example above would be quite tricky and take a lot of processing
power. But read the chapter in your DSP book on upsampling - it will
cover all this :-) Actually, not positive, but the stock, every
college in the world uses, oppenheim & shaeffer signals & systems book
MIGHT even go into it in one of the later chapters.
> > How accurate do your interpolations need to be? Think basic 1-
> > dimensional DSP.. how do you upsample a signal? insert zeros between
> > samples and LPF, right? Or do the same thing in the F-domain by zero
> > padding the ends of the FFT and inverse-FFT'ing. Either of these
> > methods in 2 dimensions is going to be a lot of computation and a lot
> > of taking stuff in and out of memory in different orders. DDR
> > memories like you to take stuff out in the same order you put them
> > in... they slow down big time when you try to jump around.. So if you
> > do this, you will need to some up with some clever methods of read out
> > pieces from DDR in the incorrect order, and then re-reading from a
> > local, smaller, block ram in the order you actually want. This will
> > take careful planning and a lot of simulation, even an experienced
> > designer would have a tricky time with this and probably get it wrong
> > in simulation the first shot.
>
> Woah, ok I'm totally lost in here. But no problem, I will take note of these
> points and consult my profs or someone
Article: 118836http://www.fpga-faq.com/FPGA_Boards.shtml "Michael" <hm512@york.ac.uk> wrote in message news:f1euoa$5ie$1@netty.york.ac.uk... > Hi, > I am looking for a new powerful FPGA board for video processing algorithm > development. My work will focue on the architecture design of video signal > processing algorithms. I hope the other parts are ready and convinient to > use. It should have video input/output and big FPGA chip and big memory. > It also will be better if there is a procesor on it. I should appreaciate > any helpful commonts and information. > Thanks > Michael > > >Article: 118837
On 3 May, 23:54, austin <aus...@xilinx.com> wrote: > OK, > > If they want to do this using the internal logic, then Antti is correct: > they would have to use ICAP, and partial active reconfiguration. > > Austin Would love an easier way here too. As per original poster, makes ASIC prototyping that little bit easier. Cheers, JonArticle: 118838
On 3 May, 23:54, austin <aus...@xilinx.com> wrote: > OK, > > If they want to do this using the internal logic, then Antti is correct: > they would have to use ICAP, and partial active reconfiguration. > > Austin Come to think of it, would be quite useful for lots of EDK type apps too. Cheers, JonArticle: 118839
On May 3, 12:57 pm, davew <David.Wo...@gmail.com> wrote: > I'm a fairly experienced user of Quartus but I've never considered > using "blocks" in block design files i.e. my design hierarchy consists > of only symbols with a mixture of Verilog and graphic design modules > "underneath" each symbol. I have never seen a need to use them. > > My question is: does anyone routinely use blocks in their designs and > what are the advantages/disadvantages of doing so? > > It seems to me that they must be there for a good reason. I just > can't see what that reason is and i think I may be missing out on > something potentially useful. > > When I say block I mean using the "block" tool not the "symbol" tool. > Blocks are or can be connected together with "conduits" whereas I > think symbols can only be connected with "bus" and "node" connections. I happen to be using blocks at the top level entity in my current design because it allows quick and dirty connections with conduits. It has a "rapid-prototyping" feel. A right-click on the conduit lets me see all the mappings Quartus did for me between the blocks. Everything below that is done in canned symbols or VHDL rendered into symbols. Note that (manual) conduit mappings are easily wiped out, and beg the use of symbols and nodes/buses.Article: 118840
On May 4, 11:58 am, Antti <Antti.Luk...@xilant.com> wrote: > On 4 Mai, 10:51, mludwig <gye...@gmail.com> wrote: > > > > > On May 4, 10:13 am, Antti <Antti.Luk...@xilant.com> wrote: > > > > On 4 Mai, 02:37, mludwig <gye...@gmail.com> wrote: > > > > > I just wanted to try the JTAG Loader tools provided with PicoBlaze and > > > > I cannot run neither hex2svf.exe, nor hex2svfsetup.exe. I get "The > > > > system cannot execute the specified program" message in the Windows XP > > > > Command Prompt. Am I missing something here? Has anybody been able to > > > > run these tools and program the instruction ROM via JTAG? > > > > > Thanks, > > > > they do work check if maybe some DLL are missing > > > > Antti > > > Hmmm, no mention of required libraries in the user guide. Do these > > tools need Xilinx ISE? I have 9.1SP3 webpack installed. > > maybe some cygwin libs missing? > you can always use "showdep" to see why winxp programs dont start > > google "windows showdep" .... first hit,or directhttp://www.zdnet.de/downloads/prg/k/b/de0AKB-wc.html > > Antti Thanks for your help. In the mean time I discovered that the long directory path of the executable was the culprit. Relocated it closer to the root and voila, it works.Article: 118841
I'm using the Quartus 2 canned i2c flash memory megafunction in a Max2 (EPM24T100C5). This is connected to a well-characterized i2c bus and is supposed to replace a 24c01 (known to work). It doesn't respond to the master. Everything sims great. After a 2-month support ticket (megatroubleshooting), Altera is stumped. I'm casting about for simple "yes" responses from anyone who has used this function (1k, 2k, 4k, or 8k) and seen it work on a real i2c bus. TIA, bb.Article: 118842
Jon, Why? Why bother with pull ups, pull downs on a bi-directional bus? Doesn't such bus have signals that tell it when to "ignore" data? On an input, why would you have to turn the pull ups on and off? Having intermediate logic levels on an input pin is of no consequence to a FPGA device (we just design it so that there are no EM, SI, or other issues). Because an ASIC requires tricks to "prevent" intermediate voltages on pins is a fault of the ASIC cell performing that function, not a function we need to provide! Designing for extremely low power, and requiring inputs to have no contention would be best done by always having an active CMOS driver to the pin (always): adding pullups and pull downs wastes power, too. Austin Jon Beniston wrote: > On 3 May, 23:54, austin <aus...@xilinx.com> wrote: >> OK, >> >> If they want to do this using the internal logic, then Antti is correct: >> they would have to use ICAP, and partial active reconfiguration. >> >> Austin > > Come to think of it, would be quite useful for lots of EDK type apps > too. > > Cheers, > Jon >Article: 118843
"austin" <austin@xilinx.com> wrote in message news:f1fg9d$t23@cnn.xsj.xilinx.com... > Jon, > > Why? > > Why bother with pull ups, pull downs on a bi-directional bus? > > Doesn't such bus have signals that tell it when to "ignore" data? > > On an input, why would you have to turn the pull ups on and off? > > Having intermediate logic levels on an input pin is of no consequence to > a FPGA device (we just design it so that there are no EM, SI, or other > issues). Because an ASIC requires tricks to "prevent" intermediate > voltages on pins is a fault of the ASIC cell performing that function, > not a function we need to provide! > > Designing for extremely low power, and requiring inputs to have no > contention would be best done by always having an active CMOS driver to > the pin (always): adding pullups and pull downs wastes power, too. > > Austin > >> Why? .. so you don't have to have pullup/pulldown on the board. Also you may want to change between having a pullup or pulldown or none. Much easier to do by controlling the PAD rather than controlling additional circuitry on the board. Much less board space too. MikeArticle: 118844
Thanks for the input so far. I did have a quick go at using blocks and conduits but I thought the mapping of I/O to signals in the conduit was quite cumbersome and confusing so I'm leaning away from the idea now. I'm not sure I would actually gain that much other than a nice looking top-level diagram (although that is one of my aims from a maintenance point of view).Article: 118845
Mike, I got that. But why must this be done dynamically, by the logic, while it is working? Why not just do this when you configure the part? AustinArticle: 118846
On May 4, 11:58 am, Antti <Antti.Luk...@xilant.com> wrote: > On 4 Mai, 10:51, mludwig <gye...@gmail.com> wrote: > > > > > On May 4, 10:13 am, Antti <Antti.Luk...@xilant.com> wrote: > > > > On 4 Mai, 02:37, mludwig <gye...@gmail.com> wrote: > > > > > I just wanted to try the JTAG Loader tools provided with PicoBlaze and > > > > I cannot run neither hex2svf.exe, nor hex2svfsetup.exe. I get "The > > > > system cannot execute the specified program" message in the Windows XP > > > > Command Prompt. Am I missing something here? Has anybody been able to > > > > run these tools and program the instruction ROM via JTAG? > > > > > Thanks, > > > > they do work check if maybe some DLL are missing > > > > Antti > > > Hmmm, no mention of required libraries in the user guide. Do these > > tools need Xilinx ISE? I have 9.1SP3 webpack installed. > > maybe some cygwin libs missing? > you can always use "showdep" to see why winxp programs dont start > > google "windows showdep" .... first hit,or directhttp://www.zdnet.de/downloads/prg/k/b/de0AKB-wc.html > > Antti Sorry, I have one more question. Have you used pBlazIDE to write the code for PicoBlaze and, if yes, have you been able to get pBlazIDE to generate the hex file you need for JTAG Loader?Article: 118847
davew wrote:
> Thanks for the input so far. I did have a quick go at using blocks
> and conduits but I thought the mapping of I/O to signals in the
> conduit was quite cumbersome and confusing so I'm leaning away from
> the idea now. I'm not sure I would actually gain that much other than
> a nice looking top-level diagram (although that is one of my aims from
> a maintenance point of view).
>
The other way to get that diagram
is let the Quartus rtl viewer draw
it for you from the source code.
See the "object" links here:
http://home.comcast.net/~mike_treseler/
-- Mike Treseler
Article: 118848> We are using an FPGA (Xilinx Spartan 3) as a delevlopment platform, > and we would like the same functionality. For your prototype you might want to consider my favourite solution: Use two I/O pins instead of one. Consider one of them as "data" pin and route it to your peripherial. Consider the other one as "pull" pin, and connect it with a 20K resistor to the data pin. For "input", put both pins in tristate. For "pullup", put the data pin in tristate, and the pull pin in output-high (the peripherial sees 20K pullup). Etc. Kind regards, MarcArticle: 118849
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 austin wrote: > Mike, > > I got that. > > But why must this be done dynamically, by the logic, while it is working? > > Why not just do this when you configure the part? > > Austin The MMC standard expects that the CMD signal to a memory card have a pullup in some modes, and no pullup in other modes. I think real-world implementations might just pick a pullup that is a compromise, though. - -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.2 (GNU/Linux) Comment: Using GnuPG with SUSE - http://enigmail.mozdev.org iD8DBQFGO2pmrPt1Sc2b3ikRAuW9AKDdKkK7tELdcEHfuBCxZBr0HquUcwCeLQgy /6/Rkdz5SAnbC+EDjW6KhOI= =M7SR -----END PGP SIGNATURE-----
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