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Thomas Something in this vein is our Broaddown2 product which we have been using with a high performance Linear Tech ADC eval module recently. The eval module we have been playing with nearly straight plugs into our edge connector on this poduct. Details of BD2 here http://www.enterpoint.co.uk/moelbryn/broaddown2.html. With some lashing up quite of a number of our products could used with eval modules from the likes of Linear Tech. We have lots of uncommitted pins and bank voltage selection in various of our products. Longer term we may have a product, maybe more, that meets your entire requirements but I can't possibly talk about these quite yet. John Adair Enterpoint Ltd. On 20 Apr, 19:40, Thomas Heller <thel...@python.net> wrote: > Gabor schrieb: > > > > > On Apr 20, 12:00 pm, Thomas Heller <thel...@python.net> wrote: > >> I'm looking for a (low-cost) spartan 3 based board, containing a > >> low to medium sized spartan 3 fpga, two 100 MSPS 12 bit AD converters, > >> and ideally also one or two 8-12 bit DA converters, but I didn't find any. > > >> Does someone know of such a board? > > >> Thanks, > >> Thomas > > > 100 MSPS @ 12 bits is a little out of the ordinary for a low-cost FPGA > > board. I'd suggest looking for an FPGA board with sufficient I/O > > connections and cobble the system together with an A/D converter > > board (if you can find that - perhaps an evaluation module from the > > converter manufacturer?). > > I came to the same conclusion by now. I found a 'piggy back' module > carrying two A/D and two D/A converters 12 bit@200MSPS [1], maybe I can > combine this with an FPGA board type that you mention. > > The system does not really not to be low cost (I'm not a student), > but I assume a board with a Virtex II device [2] with 1 million gates is too large for me. > > [1]http://www.iaf-bs.de/products/add-on-boards/adda.de.html > [2]http://www.hunteng.co.uk/products/fpga/heron-io2.htm > > Thanks, > Thomas- Hide quoted text - > > - Show quoted text -Article: 118276
The biggest issue with wire wrap is the time to do it reliably. The on- board regulators and decoupling make the board less prone to poor performance of input power supply. It most commercial applications it is probably cheaper and quicker to knock up a low tech pcb to support the module if you need a large percentage of the I/O. But for those that like wire wrapping or don't have an easy path to making a pcb wire wrap is a possibility. I have seen some very complex boards made in wire wrap but not in recent years due to the economics. John Adair Enterpoint Ltd. On 20 Apr, 21:40, Dave Pollum <vze24...@verizon.net> wrote: > On Apr 20, 8:31 am, John Adair <g...@enterpoint.co.uk> wrote: > I don't know about wirewrap boards with ground availability but one > of > our thoughts with this product was the user that likes 2-4 layer low > technology pcb boards they can assemble themselves. With this product > we allow them to stay with the board technology they like but they > can > have a high performance bga based FPGA in their system. I have seen > wirewrap sockets I believe from Mill-Max or Precidip if someone wants > to do that. > > John > I've used wire-wrap boards that had plated-thru holes and copper > planes on each side. They're made by Twin Industries and I bought > them from DigiKey. I use the bottom plane for ground and the top > plane for VCC. On the bottom I solder a 1206 cap from the power pin > of a chip's socket to the gound plane. I run my wires between pins as > if I was laying out a PCB and I DO NOT bundle the wire-wrap wires! I > also make sure that I run the wires up against the ground plane to > reduce wire inductance and ringing. I've had no problems running > 40MHz clocks with 74HCT logic and Xilinx CPLDs (on home-made adapters) > with this method. But I think that wire-wrapping a PGA device would > be pushing it. > > -Dave PollumArticle: 118277
Matt Sorrensen wrote: > That was another of my concerns, so the memory on the xilinx xc2s50e is > volatile? > > The main reason I was considering using an FPGA was that I have access > through uni to the development boards - which mind you are a pain to set up > as well as lecturers/students who have done the courses. Plus I already have > the code written for what I require. :-) and 'hopefully' it works > > I will check out the CPLD's however If you have code (even nearly OK), most vendors tools allow re-target to different devices, so you can check the CPLD size needed quite quickly. -jgArticle: 118278
On Fri, 20 Apr 2007 17:55:54 +0100, "Icky Thwacket" <it@it.it> wrote: > >"Matt Sorrensen" <mafroew@optusnet.com.au> wrote in message >news:132hkt62dc1a9a9@corp.supernews.com... >> Hey Guys/Gals, >> >> I'm only fairly new to FPGA's, I've used the xilinx xc2s400e, but this was >> on a digilent board and the whole environment was set up for me. >> >> I'm doing my final year thesis for engineering and am highly interested in >> using an FPGA as the IC's I am after, well, dont exist. >> >> The main purpose of the FPGA is to replace a 32input or gate (which is >> made out of 4-8input or gates and 1x4 input), 32 bit mux (made out of >> 2x16 bit muxes and 1x2bit mux) and 32 d-latches (each latch also has to >> have logic on its input - ie. an extremely simple finite state machine (2 >> states)) >> >> I am considering using the xilinx xc2s50e... however I do have a couple of >> concerns... >> >> Do I actually have to 'clock' the chip? or can I have it run >> asynchronously like most logic gates?? >> >> I do have a few other questions, but thats the main one. >> >> Cheers >> Matt >> > >For the simple functions you are trying to implement I would recommend a >CPLD over an FPGA. Either Altera MaxII or Xilinx equivalent. >These will be much cheaper ($2 or $3) and are standalone non volatile >instant boot devices, as opposed to an FPGA which will need some separate >boot flash and a loader. And are available in much 'easier' packages like PLCCs, and use a single supply voltage. The fact that they are much simpler devices probably also reduces the likelihood of glitches in asynchronous logic.Article: 118279
On Apr 20, 6:32 pm, "Eric Crabill" <eric.crab...@xilinx.com> wrote: > Hi, > > Dave Pollum wrote: > > But I think that wire-wrapping a PGA device would be pushing it. > > http://www.fpga-games.com/images/game_top.jpghttp://www.fpga-games.com/images/game_bot.jpg > > The Xilinx FPGA is a PG191. Some of us just don't know when to stop! > Eric Eric; I'm impressed. -Dave PollumArticle: 118280
You should have more thoroughly read the datasheet. Yes, you will need external pull-down resistors. I'm sure the V4 uses a weak-pull up (specified in the datasheet) during this time so you won't need a strong pull-down. I think you'll have to re-work your board. "Ed" <RobotBuilder@charter.net> wrote in message news:1177111861.217085.11500@e65g2000hsc.googlegroups.com... > Hi, > > I have designed a motor controller with the Virtex 4 FX-12 Mini-Module > and I of course would like the PWM output pins to never go high during > startup or programming. They do go high during this time like I don't > have control over this. Do I need external circuitry to prevent > this? I have already fabricated a board and it would be nice if this > could be handled without doing something like that. I am using ISE/ > EDK 8.2. In my system.ucf file I specify the pins to be outputs. Run > away motors are not acceptable at startup or during programming. > Thanks for any help. > > -Ed >Article: 118281
Hello, I am new in FPGA. I am using ISE 9.1.3 on windows. I wrote some VHDL codes and when I run the simulation ( from process window) the result that I am getting is correct but when I restart simulation ( using toolbar and re run it, I am getting a different result . Is it a bug in ISE or I am doing something wrong? Best regardsArticle: 118282
The cleanest solution is to change the external logic from active High to active Low. Or to insert simple CMOS inverters to achieve the same result. Peter Alfke On Apr 21, 7:42 am, "Rob" <robns...@frontiernet.net> wrote: > You should have more thoroughly read the datasheet. Yes, you will need > external pull-down resistors. I'm sure the V4 uses a weak-pull up > (specified in the datasheet) during this time so you won't need a strong > pull-down. I think you'll have to re-work your board. > > "Ed" <RobotBuil...@charter.net> wrote in message > > news:1177111861.217085.11500@e65g2000hsc.googlegroups.com... > > > Hi, > > > I have designed a motor controller with the Virtex 4 FX-12 Mini-Module > > and I of course would like the PWM output pins to never go high during > > startup or programming. They do go high during this time like I don't > > have control over this. Do I need external circuitry to prevent > > this? I have already fabricated a board and it would be nice if this > > could be handled without doing something like that. I am using ISE/ > > EDK 8.2. In my system.ucf file I specify the pins to be outputs. Run > > away motors are not acceptable at startup or during programming. > > Thanks for any help. > > > -EdArticle: 118283
For those of you that have been waiting for this module the LVDS oscillator module for our low cost Spartan-3 Raggedstone1 development board is now available. Details here http://www.enterpoint.co.uk/moelbryn/modules/ics8442.html. It is capable of generating 31.25MHz to 700MHz and can be programmed serially from the FPGA. We are fitting a 25MHz crystal currently but the module can use a clock provided from the FPGA in the range 10-25MHz to generate those more unusual frequencies. It's not on the shop of our website yet but should appear this coming week or next after that. John Adair Enterpoint Ltd.Article: 118284
On 4=A4=EB13=A4=E9, =A4W=A4=C82=AE=C917=A4=C0, "H. Peter Anvin" <h...@zytor=
.com> wrote:
> -jg wrote:
>
> > You need to define just how much theCPLDportion needs to DO.
> > - ie how many macrocells are needed
> > How much memory is shared, and what bandwdith is needed ?
>
> > It is quite easy to set up shared memory access on a Microcontroller,
> > with external RAM and aCPLD- choose a fast SRAM, and lock the
> >CPLDaccess to the idle periods in the uC bus - that way,
> > you emulate dual-port memory with cheap SRAM.
>
> Yes, I've pretty much independently come to the same conclusion. This
> is most likely the sanest option.
>
> The next step is to prototype theCPLDcode and see what kind ofCPLDit
> can fit into.
>
> The only potential concern with having theCPLDdo the arbitration of
> the SRAM bus is needing too many I/O pins on theCPLD, but I'm sure that
> can be dealt with, too.
>
> -hpa
regards:
good answer
Article: 118285I am trying to analyze amount of the FPGA (V4) resources used by each of my hierarchical blocks. I am not sure if there is a better way, but I am trying to use the information available in the Floorplanner Design Hierarchy Window. However, I am having difficulty in understanding some of the symbols, which seem to be undocumented, such as MEM16, DPRAM, ISERDES (in this context). I figured that FG probably maps on a LUT, but what about FG5, FG6, etc?...Is there a document available explaining all of these? Thanks, /MikhailArticle: 118286
On 2007-04-23, MM <mbmsv@yahoo.com> wrote: > I am trying to analyze amount of the FPGA (V4) resources used by each of my > hierarchical blocks. I am not sure if there is a better way, but I am trying > to use the information available in the Floorplanner Design Hierarchy > Window. However, I am having difficulty in understanding some of the > symbols, which seem to be undocumented, such as MEM16, DPRAM, ISERDES (in > this context). I figured that FG probably maps on a LUT, but what about FG5, > FG6, etc?...Is there a document available explaining all of these? I wrote a perl script named xdlanalyze.pl which can analyze the amount of resources used by each hierarchical block. You can find it on my homepage at http://www.da.isy.liu.se/~ehliar/stuff/ . As for your question, I assume that FG5 is a function generator with five inputs which maps to 2 LUTs (and one MUXF5) and FG6 is a function generator with 6 inputs which will map to 4 LUTs (and two MUXF5 and one MUXF6). /AndreasArticle: 118287
On 20 apr, 16:09, vhdldesigner.patr...@gmail.com wrote: > Hi, > > Is there an Altera application to count the number of equivalent gates > for Logic Elements, Memory, DSP blocks, PLL etc... ? > > Thanks... > > I don't find this information.. Here is the PR-article where they announce to stop comparing to gates... Altera: Out with Gate Counts, In with Logic Elements http://www.altera.com/corporate/news_room/releases/releases_archive/2001/products/pr-logic_measurement.html Altera devices are Macrocells, Logic Elements or Adaptive Logic Modules. The combinatorial complexity of the primitive elements vary and they hold 1, 1 or 2 bits in the register. So depending on your register count or combinatorial complexity you end up with a specific device, where from my experience the I/O pin, OnChip memory or DSP Block count is leading the device choiche. Greatings, Karl.Article: 118288
Hello, One other solution is to use the HSWAP_EN pin of your FPGA... This pin control the behavior of the user I/O pins (i.e internal pull-ups activated or not) when the FPGA configures itself... You may apply a high level on the HSWAP pin to disable pull ups, and, on the other hand, connect pull-down resistors on the PWM outputs. Hope this helps. With best regards David Oriot Peter Alfke wrote: > The cleanest solution is to change the external logic from active High > to active Low. > Or to insert simple CMOS inverters to achieve the same result. > Peter Alfke > > > On Apr 21, 7:42 am, "Rob" <robns...@frontiernet.net> wrote: >> You should have more thoroughly read the datasheet. Yes, you will need >> external pull-down resistors. I'm sure the V4 uses a weak-pull up >> (specified in the datasheet) during this time so you won't need a strong >> pull-down. I think you'll have to re-work your board. >> >> "Ed" <RobotBuil...@charter.net> wrote in message >> >> news:1177111861.217085.11500@e65g2000hsc.googlegroups.com... >> >>> Hi, >>> I have designed a motor controller with the Virtex 4 FX-12 Mini-Module >>> and I of course would like the PWM output pins to never go high during >>> startup or programming. They do go high during this time like I don't >>> have control over this. Do I need external circuitry to prevent >>> this? I have already fabricated a board and it would be nice if this >>> could be handled without doing something like that. I am using ISE/ >>> EDK 8.2. In my system.ucf file I specify the pins to be outputs. Run >>> away motors are not acceptable at startup or during programming. >>> Thanks for any help. >>> -Ed > >Article: 118289
Good morning (o; Lattice Semiconductor has given up their website' (o; Anyway...I just wanted to ask what are the approx. prices for their new ECP2 devices in quantities up to 100? Strange that Lattice distributors don't have such a nice inventory and price/on-stock tool like EBV does (o; Also local distributor doesn't want to give out prices upfront of the ECP2 devices until he knows exactly what I want to do with them (o; cheers rickArticle: 118290
Colin Paul Gloster posted: "On 2000 March 8th Richard M. Stallman has made a presentation in Trinity College Dublin. Near the end, a member of the audience has asked a question re the GPL and hardware. Richard M. Stallman has responded appreciating no relevance of freedom to hardware. Perhaps he had not been aware of code written in hardware description languages which had already been licensed according to the second version of the GPL by that time, and perhaps he has revised his opinion." In news:xn7is7dqij.fsf@localhost.localdomain timestamped 20 Apr 2007 11:17:24 -0400, DJ Delorie <dj@Delorie.com> of DJGPP responded: "The key word here is "code". IMHO RMS's point is that the types of freedoms that the GPL provides (use, change, share) do not apply to physical objects, because the cost of copying physical objects is non-trivial. So, you can GPL the code *in* an FPGA (software), but you can't GPL the FPGA itself (hardware). How could you copy a chip and share it with your friends? "Hey Colin, could you email me a Spartan 3?"" DJ's point may be completely true. I can not remember word for word what the hardware question slightly over seven years and one month ago was, and I do not remember word for word what Stallman's answer was then, but Stallman definitely did not demonstrate any awareness of HDLs at the time. He did not answer then by saying "We encourage the idea of free hardware designs", in contrast to HTTP://Lists.DuskGlow.com/open-graphics/2007-January/008663.htmlArticle: 118291
Richard Klingler wrote: > Good morning (o; > > > Lattice Semiconductor has given up their website' (o; Strange, seems to be a 'empty' placekeeper page ? Still, it is their nightime... > > Anyway...I just wanted to ask what are the approx. prices > for their new ECP2 devices in quantities up to 100? > > > Strange that Lattice distributors don't have such a nice > inventory and price/on-stock tool like EBV does (o; try findchips.com, or mouser ? > Also local distributor doesn't want to give out prices > upfront of the ECP2 devices until he knows exactly what > I want to do with them (o; Just make something up then :) Normally this type of info-trawling, is just them trying to 'register' your design win, then if you hit large volumes, they claim a % of sales, even if produciton goes elsewhere. -jgArticle: 118292
Hi Pasacco I was confronted with similar issues while using ISE-6.3 for Virtex-2 Family and the problems persisted for ISE-7.1. Recently I tried with Xiinx early access partial reconfiguration tools; which requires registration to that lounge and things actually worked for me. I suggest you to use early access tools with Xilinx PlanAhead and things would get better. Hope it works /MH Pasacco wrote: > Hi > > I am experimenting on module-based partial reconfiguration for > Virtex-4 (LX25-ff668). > > Intended functionality is that > > After full bitstream download on the board, LED blinks. > After partial bitstream download, LED blinks with different frequency. > > Intended chip floorplan is that > > Left half is is 'reconfigurable' region and right half is 'fixed' > region. > I intend to generate partial bitstream for the "left half". > > I made 1-bit slice-based bus macro for both of Virtex-2 Pro and > Virtex-4. > > When I tried module-based flow (xapp290) for Virtex-2 Pro on ISE > 8.2.03, > it works on the board, for both of full bitstream (with size of 1.4MB) > and partial bitstream (with size of 50KB). > > I tried on Virtex-4 with ISE 8.2.03. > Module based tool flow does not create any error. > I checked two NCD files for partial / full bitstream on the FPGA > editor. > Everything seems okay. > When I download full bitstream (with size of 955 KB), it works on the > board. > It means that the bus macro functions correctly as a wire. > > Problem is that > > -------------------- > Partial bitstream size is same as full bitstream size (with 955 KB) > Also when I download partial bitstream, it does not work on the board. > > It implies that the chip is NOT partitioned as described in UCF file > and the generated partial bitstream is not PARTIAL --: > -------------------- > > I wonder if we can generate partial bitstream using xapp290 flow for > Virtex-4 ? > Does anyone have these experiences? > > Thank you for any comment.Article: 118293
cs_posting@hotmail.com wrote: > On Apr 19, 12:44 pm, Austin Lesea <aus...@xilinx.com> wrote: >> Kunal, >> >> The "Spartan 3E Starter Board" from digilentinc.com is used by quite a >> number of schools and universities. >> >> As such, 'google' for this shows 131 hits, with complete courses with >> labs from University of Arizona, etc. etc. >> >> $149. >> >> http://www.digilentinc.com/Products/Detail.cfm?Prod=S3EBOARD&Nav1=Pro... >> >> Austin > > > Unless someone really needs an S3E chip, I might stay away from that > board, as part of its schematics (around the USB chip) are withheld, > limiting your options for programming and communicating with it to > what is officially supported or laboriously reverse engineered. > IMHO this argument for a student using the kit is somewhat absurd. I work at a Government lab tied to a University and see Undergrad and Grad students all the time (we provide a great deal of funding for them). The USB interfaces is for JTAG download (probably the guts to the Xilinx USB cable). If they are just learning about FPGAs, the last thing they are going to worry about is the mechanism the USB cable uses to download the bitstream. To make the argument that you options for communicating and configuring are limiting to student the board is just plain wrong. There is spot for a normal JTAG header on the PCB to use the VIII and IV cables. Trust me, most don't really care about how the USB download circuit operates. People just care that they can get the code in the chip. A student learning about this is not going to spend their first three months learning about how to design a USB interface. They should be spending their time learning about HDL, logic design, simulation, etc. When it comes to production design, the one would worry about the configuration options. Even then, this board provides you with just about all you need (JTAG, PROM, SPI) to get the device configured.Article: 118294
Hello,
I decided to test UltraEdit to see how good is it in reformatting a
VHDL code and indenting smartly. To do this I installed ultraedit and I did
a test by asking UE to reformat this code for me:
process (Rst)
begin
if clk='1' then
if Rst='1' then system_state <= wait_for_input;
end if;
end if;
end process;
and I got this:
process (Rst) begin if clk='1' then
if Rst='1' then system_state <= wait_for_input;
end if; end if; end process;
which I think is not a good reformatting.
My question is:
Can UE reformat VHDL code and doing the smart indentation on it?
Is the result that I am getting correct?
Am I missing anything?
My search on the web showed that I should get a new file for this, Am I
right? Where can I get it?
Regards
Article: 118295"Andreas Ehliar" <ehliar@lysator.liu.se> wrote in message news:f0h8um$eu9$1@news.lysator.liu.se... > > I wrote a perl script named xdlanalyze.pl which can analyze the amount of > resources used by each hierarchical block. You can find it on my homepage > at http://www.da.isy.liu.se/~ehliar/stuff/ . > Thanks a lot Andreas, seems to be exactly what I need! /MikhailArticle: 118296
Matt Sorrensen wrote: > > The main reason I was considering using an FPGA was that I have access > through uni to the development boards - which mind you are a pain to set up > as well as lecturers/students who have done the courses. Plus I already have > the code written for what I require. :-) and 'hopefully' it works > > I will check out the CPLD's however After all your project is a thesis, so including discussion of alternatives is just as important as the solution. "While a satisfactory solution could have been produced using many discrete logic ICs, or one or more CPLDs, the selection of an FPGA solution was heavily influenced by time limits and presence of appropriate hardware and software in the school laboratory."Article: 118297
On Apr 23, 8:45 am, Eli Hughes <emh...@psu.edu> wrote: > > Unless someone really needs an S3E chip, I might stay away from that > > board, as part of its schematics (around the USB chip) are withheld, > > limiting your options for programming and communicating with it to > > what is officially supported or laboriously reverse engineered. > > IMHO this argument for a student using the kit is somewhat absurd. I > work at a Government lab tied to a University and see Undergrad and Grad > students all the time (we provide a great deal of funding for them). > > The USB interfaces is for JTAG download (probably the guts to the Xilinx > USB cable). If they are just learning about FPGAs, the last thing they > are going to worry about is the mechanism the USB cable uses to download > the bitstream. The poster is not a student using a school supplied board, he's someone with the personal funding to buy one board and one board only. So it should be something that he can get long term varied use out of. Something that might not be limiting to a studnet who will soon move on to other platforms or courses could be a real limitation in this case. And one of the long term issues with FPGAs is what do you want to do with them - if it involves quantities of data, getting that into and out of the board becomes a challenge. USB is a great interface for that - but if its not documented, it becomes even harder than it needs to be. > To make the argument that you options for communicating and configuring > are limiting to student the board is just plain wrong. There is spot > for a normal JTAG header on the PCB to use the VIII and IV cables. > Trust me, most don't really care about how the USB download circuit > operates. People just care that they can get the code in the chip. Great, another cable to buy. Hopefully it at least can accomodate the $12 digilent cable as supplied with the S3Kit (I know nexys can, but that's a digilent-unique product rather than one done for xilinx)Article: 118298
On Apr 20, 3:08 pm, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > > For the simple functions you are trying to implement I would recommend a > > CPLD over an FPGA. Either Altera MaxII or Xilinx equivalent. > > These will be much cheaper ($2 or $3) and are standalone non volatile > > instant boot devices, as opposed to an FPGA which will need some separate > > boot flash and a loader. > > Good advice - CPLDs are easier to learn. > Most vendors also support simpler language flows, for CPLDs Very true, alas I suspect CPLD's are to blame for the present lack of gals...Article: 118299
Hi, I am having a problem with a design. When DONE cycle is set to 5 or 6 DONE pin never goes high. I have confirmed that the part is configuring by scoping the output from the DCM. The part is a 2S300E. When I scope out the INIT line I find that after 280mS the INIT line returns to a High-Z state - I believe that this is interupting the state machine so causing the DONE pin not to go high. If I set the DONE cycle to 1, 2, 3 or 4 - DONE goes high and INIT stays high. Any help would be appreciated Dave
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