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On Apr 17, 11:02 pm, Peter Alfke <a...@sbcglobal.net> wrote: > A few ideas: > Are you sure about the content of the various locations? > Could the error have happened when you wrote data into the BRAM? > > When reading, read twicein sequence from the same address. Then you > will see whether this is a read pipelining problem, or whether you > really are always reading the wrong information. > The error has to somewhere in your timing. > > Be a sleuth! > Peter Alfke > > On Apr 17, 7:12 pm, Gabor <g...@alacron.com> wrote: > > > > > On Apr 17, 8:13 pm, "M. Hamed" <mhs...@gmail.com> wrote: > > > > I am getting a strange error with Block RAM on a Spartan 3 FPGA. Every > > > time I issue a read, the word at the location previous to the given > > > address is read. For example if I'm reading from address 5, the word > > > at address 4 is output instead. The data written to the block seems > > > correct when I view it in ModelSim so I assume it's something with the > > > read. > > > This does seem strange. Are your writes and reads always made to > > sequential memory locations (i.e. 1, 2, 3, ... in order)? Perhaps the > > error is in cycle timing and not address? > > > > Viewing signals at the BRAM input in ModelSim shows the correct > > > address at the input of port A and the read clock signal goes high but > > > the wrong word appear at the output. ENA is always 1 and WEA is always > > > 0. The very most recent Write to this same address (from a different > > > port) also shows the correct value being written. > > > > The design works correctly in RTL but this problem only occurs with > > > the post-route netlist. > > > > Did anyone encounter a similar problem like this before and can give > > > me a hint on what's going on. > > > The only time I've seen something similar was with an old version of > > the > > BRAM simulation models that needed a slight positive hold time in the > > address. In effect it was the behavioral simulation that incorrectly > > gave > > the read data on the same clock that the address was presented. In > > fact > > BRAM's are registered in the Spartan 3 (and Virtex 2) series, so the > > output data should have changed on the following clock cycle. In the > > post-PAR timing simulation, the output changed on the following clock > > cycle as expected. > > > > Thank you.- Hide quoted text - > > - Show quoted text - If you generated the block RAM with coregen, there is an option to preload the RAM with a coe file. You can then simulate the block RAM both at the RTL and post P&R level, disable the writes in the code and see if you read the expected data designated by the coe file at the desired addresses. There are some instances when the RTL does not match the post P&R simulation. i.e. (sensitivity list is incomplete in a combinatorial process, improper use of blocking assignments and variables) I don't use the later two items in synthesizable code, so I don't have much experience with them, but then again, I never get an RTL vs post P&R simulation mismatch because of them. Hope this helps, NewmanArticle: 118126
What sorts of frequencies can currently-available analog FPGAs run at? (Either pure analog, or mixed such as the Actel Fusion.) For example, if I wanted a gated integrator with a sub-microsecond gating windows, what product lines, if any, can handle that? I know e.g. that the Fusion has a 600 ksample/s ADC with a multiplexer, but I don't know the bandwidth of the amplifiers etc. in the analog blocks. Thanks. -- David M. Palmer dmpalmer@email.com (formerly @clark.net, @ematic.com)Article: 118127
Hello,
First of all I will make my question: Could you please say me how
many Masters can be connected to the Bus when the BFM simulation is
been used?
I created a coprocessor for the embedded PowerPC, and two files to
implement a bridge between the PLB Bus and the Bus of my coprocessor
( small bus called On Chip Bus).
I have a Master which is able to read all the operations from a txt
file. this is my sistem
BFM Bus
file.txt --> Master_1 -->|
|
|-->bridge_plb2ocb
|
coprocessor(bus on chip bus ocb)
|-->bridge_ocb2plb
|
Register<--|
I am using the BFM simulation because I got always problems with the
behavioural simulation( i have a problem that i posted here and i do
not have the solution yet(
http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/c4be67a12afae957/1098d98a5af6caf8?lnk=gst&q=ferorcue&rnum=2&hl=en#1098d98a5af6caf8
))
The point is that Master_1 and bridge_ocb2plb are both masters and the
system it is not working. Only the master that is mapped in the memory
address 0x00000000 it is working. I checked first with Master_1 mapped
in 0x0, and later with bridge_ocb2plb mapped in 0x0, and the bus of
the BFM simulation only answer or hear the request of one of both
masters, the one which is mapped in the 0x0.
I think that you have more experience with embedded systems, do you
think that what i am writing here make sense? It is possible that the
BFM simulation only allow to have one Master in our systems? Is there
another possibility to simulate a system with 2,3 or more masters?
Thank you very much for your answers.
Note: if the solution it is to use the behaviural simulation, could
you please help my with my problem using this simulation, i have post
it here with the Subject:
XPS behavioral simulation fails: the design is not loaded
Article: 118128motty schrieb: > I am using ModelSim SE and was wondering if there is a way to make a > waveform display mnemonics. I am simulating a state machine and it > would be convenient to have the waveform display the state name > instead of the binary/hex of the state. I looked all over the > documentation and didn't find anything. > > The module is written in verilog and the states are parameterized. NC- > Sim had an easy way to map numerical values to text. You create the > mapping and then can apply it to any waveform. I just haven't found > an easy way to do this in ModelSim. It is probably staring me in the > face! > Hi motty do you have enumerated types in verilog? e.g. type fsm_state_type is (start, action1, action2,...,end); If so, you could use (or assign ) these to a signal that corresponds to the state of your FSM. This signal can be displayed in the modelsim wave window as readable text. have a nice simulation EilertArticle: 118129
Hi Farhan,
Here's how I wired the wishbone ATA controller to the OPB IPIF. I
hope it helps.
--- OPB2IPIF
signal sig_o2i_Clk_o : std_logic; -- opb2ipif_0
signal sig_o2i_Reset_o : std_logic;
signal sig_o2i_Freeze_o : std_logic;
signal sig_o2i_AddrValid_o : std_logic;
signal sig_o2i_Burst_o : std_logic;
signal sig_o2i_RNW_o : std_logic;
signal sig_o2i_CS_o : std_logic_vector(0 to 0);
signal sig_o2i_CE_o : std_logic_vector(0 to 0);
signal sig_o2i_RdCE_o : std_logic_vector(0 to 0);
signal sig_o2i_WrCE_o : std_logic_vector(0 to 0);
signal sig_o2i_Ack_i : std_logic;
signal sig_o2i_Retry_i : std_logic;
signal sig_o2i_Error_i : std_logic;
signal sig_o2i_ToutSup_i : std_logic;
signal sig_o2i_PostedWrInh_i : std_logic;
signal sig_o2i_AddrAck_i : std_logic;
signal sig_o2i_Addr_o_xil : std_logic_vector(0 to 31);
signal sig_o2i_Data_o_xil : std_logic_vector(0 to 31);
signal sig_o2i_BE_o_xil : std_logic_vector(0 to 3);
signal sig_o2i_Data_i_xil : std_logic_vector(0 to 31);
signal sig_o2i_Addr_o : std_logic_vector(31 downto 0);
signal sig_o2i_Data_o : std_logic_vector(31 downto 0);
signal sig_o2i_BE_o : std_logic_vector( 3 downto 0);
signal sig_o2i_Data_i : std_logic_vector(31 downto 0);
--- WISHBONE bus
signal sig_wb_data_o : std_logic_vector (31 downto 0);
signal sig_wb_data_i : std_logic_vector (31 downto 0);
-- signal sig_wb_addr_o : std_logic_vector (31 downto 0);
signal sig_wb_cyc_o : std_logic;
signal sig_wb_stb_o : std_logic;
signal sig_wb_sel_o : std_logic_vector ( 3 downto 0);
signal sig_wb_we_o : std_logic;
signal sig_wb_ack_i : std_logic;
signal sig_wb_err_i : std_logic;
signal sig_wb_rty_i : std_logic;
--- Components
component edk
port (
...
o2i_Clk_o_pin : out std_logic; -- opb2ipif_0 (for ATAHOST)
o2i_Reset_o_pin : out std_logic;
o2i_Freeze_o_pin : out std_logic;
o2i_Addr_o_pin : out std_logic_vector(0 to 31);
o2i_AddrValid_o_pin : out std_logic;
o2i_Data_o_pin : out std_logic_vector(0 to 31);
o2i_BE_o_pin : out std_logic_vector(0 to 3);
o2i_Burst_o_pin : out std_logic;
o2i_RNW_o_pin : out std_logic;
o2i_CS_o_pin : out std_logic_vector(0 to 0);
o2i_CE_o_pin : out std_logic_vector(0 to 0);
o2i_RdCE_o_pin : out std_logic_vector(0 to 0);
o2i_WrCE_o_pin : out std_logic_vector(0 to 0);
o2i_Data_i_pin : in std_logic_vector(0 to 31);
o2i_Ack_i_pin : in std_logic;
o2i_Retry_i_pin : in std_logic;
o2i_Error_i_pin : in std_logic;
o2i_ToutSup_i_pin : in std_logic;
o2i_PostedWrInh_i_pin : in std_logic;
o2i_AddrAck_i_pin : in std_logic;
...
);
end component;
-------------------------------------------------------------------
--- DISK ---
-------------------------------------------------------------------
--- signals
signal sig_disk_irq : std_logic; -- disk module requests
INTERRUPT
signal sig_disk_dma_req : std_logic; -- disk module requests
DMA
signal sig_disk_dma_ack : std_logic;
--- external pin glue
signal sig_disk_reset_n : std_logic;
signal sig_disk_dd_i : std_logic_vector (15 downto 0);
signal sig_disk_dd_o : std_logic_vector (15 downto 0);
signal sig_disk_dd_t : std_logic;
signal sig_disk_dd_oe : std_logic;
signal sig_disk_da : std_logic_vector ( 2 downto 0);
signal sig_disk_cs0_n : std_logic;
signal sig_disk_cs1_n : std_logic;
signal sig_disk_dior_n : std_logic;
signal sig_disk_diow_n : std_logic;
signal sig_disk_iordy : std_logic;
signal sig_disk_intrq : std_logic;
signal sig_disk_dmarq : std_logic;
signal sig_disk_dmack_n : std_logic;
signal sig_disk_dasp_n : std_logic; -- not used
signal sig_disk_pdiag_n : std_logic; -- not used
--- core glue
signal sig_disk_da_u : unsigned(2 downto 0);
signal sig_wb_addr_disk_u : unsigned(6 downto 2);
signal sig_wb_cs_disk : std_logic;
--- OCIDEC3 core
component atahost_top
generic (
ARST_LVL : std_logic := '0'; -- asynchronous reset level
TWIDTH : natural := 8; -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 =
600 - 70 - 290 = 240
-- Multiword DMA mode 0 settings (@100MHz clock)
DMA_mode0_Tm : natural := 4; -- 50ns
DMA_mode0_Td : natural := 21; -- 215ns
DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm =
480 - 50 - 215 = 215
);
port(
-- WISHBONE SYSCON signals
wb_clk_i : in std_logic; -- master clock in
arst_i : in std_logic := '1'; -- asynchronous active low reset
wb_rst_i : in std_logic := '0'; -- synchronous active high
reset
-- WISHBONE SLAVE signals
wb_cyc_i : in std_logic; -- valid bus cycle input
wb_stb_i : in std_logic; -- strobe/core select input
wb_ack_o : out std_logic; -- strobe acknowledge output
wb_rty_o : out std_logic; -- retry output
wb_err_o : out std_logic; -- error output
wb_adr_i : in unsigned(6 downto 2); -- A6 = '1' ATA devices
selected
-- A5 =
'1' CS1- asserted, '0' CS0- asserted
-- A4..A2
ATA address lines
-- A6 = '0' ATA
controller selected
wb_dat_i : in std_logic_vector(31 downto 0); -- Databus in
wb_dat_o : out std_logic_vector(31 downto 0); -- Databus out
wb_sel_i : in std_logic_vector(3 downto 0); -- Byte select
signals
wb_we_i : in std_logic; -- Write enable input
wb_inta_o : out std_logic; -- interrupt request signal IDE0
-- DMA engine signals
DMA_req : out std_logic; -- DMA request
DMA_Ack : in std_logic; -- DMA acknowledge
-- ATA signals
resetn_pad_o : out std_logic;
dd_pad_i : in std_logic_vector(15 downto 0);
dd_pad_o : out std_logic_vector(15 downto 0);
dd_padoe_o : out std_logic;
da_pad_o : out unsigned(2 downto 0);
cs0n_pad_o : out std_logic;
cs1n_pad_o : out std_logic;
diorn_pad_o : out std_logic;
diown_pad_o : out std_logic;
iordy_pad_i : in std_logic;
intrq_pad_i : in std_logic;
dmarq_pad_i : in std_logic;
dmackn_pad_o : out std_logic;
debug_pio_sample_indata : out std_logic
);
end component;
signal sig_pio_sample : std_logic;
---------------------------------------------------------------------------------------------------
--- ---
--- EDK - Embedded Submodule ---
--- ---
---------------------------------------------------------------------------------------------------
edk_inst : edk
port map (
...
--- OPB2IPIF
o2i_Clk_o_pin => sig_o2i_Clk_o,
o2i_Reset_o_pin => sig_o2i_Reset_o,
o2i_Freeze_o_pin => sig_o2i_Freeze_o,
o2i_Addr_o_pin => sig_o2i_Addr_o_xil,
o2i_AddrValid_o_pin => sig_o2i_AddrValid_o,
o2i_Data_o_pin => sig_o2i_Data_o_xil,
o2i_BE_o_pin => sig_o2i_BE_o_xil,
o2i_Burst_o_pin => sig_o2i_Burst_o,
o2i_RNW_o_pin => sig_o2i_RNW_o,
o2i_CS_o_pin => sig_o2i_CS_o,
o2i_CE_o_pin => sig_o2i_CE_o,
o2i_RdCE_o_pin => sig_o2i_RdCE_o,
o2i_WrCE_o_pin => sig_o2i_WrCE_o,
o2i_Data_i_pin => sig_o2i_Data_i_xil,
o2i_Ack_i_pin => sig_o2i_Ack_i,
o2i_Retry_i_pin => sig_o2i_Retry_i,
o2i_Error_i_pin => sig_o2i_Error_i,
o2i_ToutSup_i_pin => sig_o2i_ToutSup_i,
o2i_PostedWrInh_i_pin => sig_o2i_PostedWrInh_i,
o2i_AddrAck_i_pin => sig_o2i_AddrAck_i,
...
);
---------------------------------------------------------------------------------------------------
--- ---
--- ---
--- OPB IPIF to WB ---
--- ---
--- ---
---------------------------------------------------------------------------------------------------
--- Reverse stupid xilinx "big endian" addressing
o2i_xil1 : for i in 0 to 31 generate
sig_o2i_Data_i_xil (31-i) <= sig_o2i_Data_i (i);
sig_o2i_Data_o (i) <= sig_o2i_Data_o_xil (31-i);
sig_o2i_Addr_o (i) <= sig_o2i_Addr_o_xil (31-i);
end generate;
o2i_xil2 : for i in 0 to 3 generate
sig_o2i_BE_o (i) <= sig_o2i_BE_o_xil (3-i);
end generate;
---------------------------------------------------------------------------------------------------
--- ---
--- ---
--- HARDDISK - OCIDEC3 from OpenCores ---
--- ---
--- ---
---------------------------------------------------------------------------------------------------
sig_disk_dma_ack <= '0';
--- OPB2IPIF -> ATAHOST WISHBONE glue
sig_wb_cs_disk <= '1' when sig_o2i_CS_o(0)='1' AND sig_o2i_Addr_o
(15 downto 8) = x"00" else '0';
sig_wb_addr_disk_u <= unsigned(sig_o2i_Addr_o(6 downto 2)); -- A6
= '1' ATA devices selected
-- A5 = '1' CS1- asserted, '0' CS0- asserted
-- A4..A2 ATA address lines
-- A6 = '0' ATA controller selected
sig_wb_cyc_o <= sig_wb_cs_disk; -- valid bus cycle
sig_wb_stb_o <= sig_wb_cs_disk; -- strobe/core select
sig_wb_we_o <= NOT(sig_o2i_RNW_o); -- Write enable
sig_wb_sel_o <= (others=>'1'); -- Byte select signals
sig_wb_data_o <= sig_o2i_Data_o; -- Databus
sig_o2i_Data_i <= sig_wb_data_i; -- Databus
sig_o2i_Ack_i <= sig_wb_ack_i; -- strobe ack
sig_o2i_Retry_i <= sig_wb_rty_i; -- retry
sig_o2i_Error_i <= sig_wb_err_i; -- error
sig_o2i_PostedWrInh_i <= '1';
sig_o2i_ToutSup_i <= '1';
--- ATAHOST -> I/O pads glue
sig_disk_da <= std_logic_vector(sig_disk_da_u);
sig_disk_dd_t <= NOT(sig_disk_dd_oe);
--- Instantiate OCIDEC3 ATAHOST core
disk_inst : atahost_top
generic map (
ARST_LVL => '0', -- we're going to invert reset
TWIDTH => 8, -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 => 6, -- 70ns
PIO_mode0_T2 => 28, -- 290ns
PIO_mode0_T4 => 2, -- 30ns
PIO_mode0_Teoc => 23, -- 240ns ==> T0 - T1 - T2 = 600 - 70 -
290 = 240
-- Multiword DMA mode 0 settings (@100MHz clock)
DMA_mode0_Tm => 4, -- 50ns
DMA_mode0_Td => 21, -- 215ns
DMA_mode0_Teoc => 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 -
215 = 215
)
port map (
-- WISHBONE SYSCON signals
wb_clk_i => CLK_OPB, -- master clock in
arst_i => NOT(RST), -- asynchronous active low reset
wb_rst_i => '0', -- synchronous active high reset
-- WISHBONE SLAVE signals
wb_cyc_i => sig_wb_cyc_o, -- valid bus cycle input
wb_stb_i => sig_wb_stb_o, -- strobe/core select input
wb_ack_o => sig_wb_ack_i, -- strobe acknowledge output
wb_rty_o => sig_wb_rty_i, -- retry output
wb_err_o => sig_wb_err_i, -- error output
wb_adr_i => sig_wb_addr_disk_u, -- A6 = '1' ATA devices
selected
-- A5 = '1' CS1- asserted, '0' CS0- asserted
-- A4..A2 ATA address lines
-- A6 = '0' ATA controller selected
wb_dat_i => sig_wb_data_o, -- Databus in
wb_dat_o => sig_wb_data_i, -- Databus out
wb_sel_i => sig_wb_sel_o, -- Byte select signals
wb_we_i => sig_wb_we_o, -- Write enable input
wb_inta_o => sig_disk_irq, -- interrupt request signal IDE0
-- DMA engine signals
DMA_req => sig_disk_dma_req, -- DMA request
DMA_Ack => sig_disk_dma_ack, -- DMA acknowledge
-- ATA signals
resetn_pad_o => sig_disk_reset_n,
dd_pad_i => sig_disk_dd_i,
dd_pad_o => sig_disk_dd_o,
dd_padoe_o => sig_disk_dd_oe,
da_pad_o => sig_disk_da_u,
cs0n_pad_o => sig_disk_cs0_n,
cs1n_pad_o => sig_disk_cs1_n,
diorn_pad_o => sig_disk_dior_n,
diown_pad_o => sig_disk_diow_n,
iordy_pad_i => sig_disk_iordy,
intrq_pad_i => sig_disk_intrq,
dmarq_pad_i => sig_disk_dmarq,
dmackn_pad_o => sig_disk_dmack_n,
debug_pio_sample_indata => sig_pio_sample
);
--- Instantiate external pins
disk_obuf_reset_n : OBUF
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "FAST"
)
port map (
I => sig_disk_reset_n,
O => FPGA_DD_RESET_N
);
disk_obuf_cs0_n : OBUF
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "FAST"
)
port map (
I => sig_disk_cs0_n,
O => FPGA_CS0_N
);
disk_obuf_cs1_n : OBUF
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "FAST"
)
port map (
I => sig_disk_cs1_n,
O => FPGA_CS1_N
);
disk_obuf_da0_n : OBUF
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "FAST"
)
port map (
I => sig_disk_da (0),
O => FPGA_DA0
);
disk_obuf_da1_n : OBUF
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "FAST"
)
port map (
I => sig_disk_da (1),
O => FPGA_DA1
);
disk_obuf_da2_n : OBUF
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "FAST"
)
port map (
I => sig_disk_da (2),
O => FPGA_DA2
);
disk_iobuf_dd : for i in 0 to 15 generate U1 : IOBUF
generic map (
CAPACITANCE => "NORMAL",
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "FAST"
)
port map (
I => sig_disk_dd_o (i),
O => sig_disk_dd_i (i),
T => sig_disk_dd_t,
IO => FPGA_DD_DD (i)
);
end generate;
disk_obuf_dior_n : OBUF
generic map (
DRIVE => 16,
IOSTANDARD => "DEFAULT",
SLEW => "FAST"
)
port map (
I => sig_disk_dior_n,
O => FPGA_DIOR_HDMARDY_HSTB
);
disk_obuf_diow_n : OBUF
generic map (
DRIVE => 16,
IOSTANDARD => "DEFAULT",
SLEW => "FAST"
)
port map (
I => sig_disk_diow_n,
O => FPGA_DIOW_STOP
);
disk_obuf_dmack_n : OBUF
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "FAST"
)
port map (
I => sig_disk_dmack_n,
O => FPGA_DMACK_N
);
disk_iobuf_dmarq : IOBUF
generic map (
CAPACITANCE => "NORMAL",
DRIVE => 4,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW"
)
port map (
I => '0',
O => sig_disk_dmarq,
T => '1',
IO => FPGA_DMARQ
);
disk_iobuf_intrq : IOBUF
generic map (
CAPACITANCE => "NORMAL",
DRIVE => 4,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW"
)
port map (
I => '0',
O => sig_disk_intrq,
T => '1',
IO => FPGA_INTRQ
);
disk_iobuf_iordy : IOBUF
generic map (
CAPACITANCE => "NORMAL",
DRIVE => 4,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW"
)
port map (
I => '0',
O => sig_disk_iordy,
T => '1',
IO => FPGA_IORDY_DDMARDY_DSTB
);
--- Pins outside of the scope of the core
disk_obuf_csel : OBUF
generic map (
DRIVE => 4,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW"
)
port map (
I => '0',
O => FPGA_CSEL
);
--- Pins that are not used at all
disk_ibuf_dasp_n : IBUF
generic map (
CAPACITANCE => "LOW",
IOSTANDARD => "DEFAULT"
)
port map (
I => FPGA_DASP_N,
O => sig_disk_dasp_n
);
disk_ibuf_pdiag_n : IBUF
generic map (
CAPACITANCE => "LOW",
IOSTANDARD => "DEFAULT"
)
port map (
I => FPGA_PDIAG_N,
O => sig_disk_pdiag_n
);
disk_obuf_sp1 : OBUF
generic map (
DRIVE => 4,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW"
)
port map (
I => '0',
O => DD_SP1
);
--- Pullup/pulldown resistors
disk_pulldown_dd7 : PULLDOWN
port map (
O => FPGA_DD_DD (7) -- ATA7 pg.38: 10k pulldown on DD7 to
detect absence of a device
);
disk_pulldown_dmarq : PULLDOWN
port map (
O => FPGA_DMARQ -- ATA7 pg.38: 5k6 pulldown
);
disk_pullup_iordy : PULLUP
port map (
O => FPGA_IORDY_DDMARDY_DSTB -- ATA7 pg.38: 4k7 pullup
);
disk_pulldown_intrq : PULLDOWN
port map (
O => FPGA_INTRQ -- ATA7 pg.38: 6k2 pulldown -> selects
active-high
);
Article: 118130
Hello,
Is there any facility in ISE to automatically indent source code? The
similar technique is available in C/C++ editors and I it is very simple to
add it to ISE for indenting smartly VHDL and Verilog source codes.
Regards
Article: 118131mans schrieb: > Hello, > Is there any facility in ISE to automatically indent source code? The > similar technique is available in C/C++ editors and I it is very simple to > add it to ISE for indenting smartly VHDL and Verilog source codes. Not as far as I know. But you can tell ISE to use an external editor like Xemcas, Notepad++, Eclipse with the VHDL-plugin... they all have indentation, syntax highlighting, templates, code folding... -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 118132
Hi all, I'm using Ise 9.1.03i. when I try to print a code written in Ise text editor, I get this error: "Print fails because the default printer has not been selected", and when the design summary is opened I can see the window "steup printer" and my default printer is automatically selected. How to configure printer for ise text editor? thanks.Article: 118133
Hello, I am trying to simulate a VHDL code (using ISE 9) and I am getting the following error: ERROR:Simulator:235 - Package XXX_pkg has not been compiled properly. Please recompile package XXX_pkg. How can I compile a package? RegardsArticle: 118134
On 2007-04-18, Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> wrote:
> On 17 Apr 2007 22:13:52 -0700, motty <mottoblatto@yahoo.com> wrote:
>
>>I am using ModelSim SE and was wondering if there is a way to make a
>>waveform display mnemonics. I am simulating a state machine and it
>>would be convenient to have the waveform display the state name
>>instead of the binary/hex of the state. I looked all over the
>>documentation and didn't find anything.
>>
>>The module is written in verilog and the states are parameterized. NC-
>>Sim had an easy way to map numerical values to text. You create the
>>mapping and then can apply it to any waveform. I just haven't found
>>an easy way to do this in ModelSim. It is probably staring me in the
>>face!
>
> It's not staring you in the face at all - it's a little tricky
> to find - but check out the online help for the "virtual type"
> and "virtual function" commands, and you'll get what you need.
>
> To answer backhus: no, you don't have enumerations in Verilog
> (although they do exist in SystemVerilog).
Another possibility that I've seen in some situations is to
set a signal to a certain string in the state machine as in:
always @(posedge clk)
if(rst) begin
state_r <= IDLE;
state_str <= "STATE1";
end else begin
case(state_r)
IDLE: begin
state_r <= STATE1;
state_str <= "STATE1";
end
STATE1: begin
// and so on...
end
endcase
end
Emacs verilog mode seems to have something that does this automatically
for you. See http://www.veripool.com/verilog-mode_veritedium.html#SEC23
/Andreas
Article: 118135On 17 Apr 2007 22:13:52 -0700, motty <mottoblatto@yahoo.com> wrote: >I am using ModelSim SE and was wondering if there is a way to make a >waveform display mnemonics. I am simulating a state machine and it >would be convenient to have the waveform display the state name >instead of the binary/hex of the state. I looked all over the >documentation and didn't find anything. > >The module is written in verilog and the states are parameterized. NC- >Sim had an easy way to map numerical values to text. You create the >mapping and then can apply it to any waveform. I just haven't found >an easy way to do this in ModelSim. It is probably staring me in the >face! It's not staring you in the face at all - it's a little tricky to find - but check out the online help for the "virtual type" and "virtual function" commands, and you'll get what you need. To answer backhus: no, you don't have enumerations in Verilog (although they do exist in SystemVerilog). -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 118136
On Apr 18, 2:27 pm, jetm...@hotmail.com wrote:
> Hi Farhan,
>
> Here's how I wired the wishbone ATA controller to the OPB IPIF. I
> hope it helps.
>
> --- OPB2IPIF
>
> signal sig_o2i_Clk_o : std_log=
ic; -- opb2ipif_0
> signal sig_o2i_Reset_o : std_log=
ic;
> signal sig_o2i_Freeze_o : std_log=
ic;
> signal sig_o2i_AddrValid_o : std_log=
ic;
> signal sig_o2i_Burst_o : std_log=
ic;
> signal sig_o2i_RNW_o : std_log=
ic;
> signal sig_o2i_CS_o : std_log=
ic_vector(0 to 0);
> signal sig_o2i_CE_o : std_log=
ic_vector(0 to 0);
> signal sig_o2i_RdCE_o : std_log=
ic_vector(0 to 0);
> signal sig_o2i_WrCE_o : std_log=
ic_vector(0 to 0);
> signal sig_o2i_Ack_i : std_log=
ic;
> signal sig_o2i_Retry_i : std_log=
ic;
> signal sig_o2i_Error_i : std_log=
ic;
> signal sig_o2i_ToutSup_i : std_log=
ic;
> signal sig_o2i_PostedWrInh_i : std_log=
ic;
> signal sig_o2i_AddrAck_i : std_log=
ic;
>
> signal sig_o2i_Addr_o_xil : std_log=
ic_vector(0 to 31);
> signal sig_o2i_Data_o_xil : std_log=
ic_vector(0 to 31);
> signal sig_o2i_BE_o_xil : std_log=
ic_vector(0 to 3);
> signal sig_o2i_Data_i_xil : std_log=
ic_vector(0 to 31);
>
> signal sig_o2i_Addr_o : std_log=
ic_vector(31 downto 0);
> signal sig_o2i_Data_o : std_log=
ic_vector(31 downto 0);
> signal sig_o2i_BE_o : std_log=
ic_vector( 3 downto 0);
> signal sig_o2i_Data_i : std_log=
ic_vector(31 downto 0);
>
> --- WISHBONE bus
>
> signal sig_wb_data_o : std_log=
ic_vector (31 downto 0);
> signal sig_wb_data_i : std_log=
ic_vector (31 downto 0);
> -- signal sig_wb_addr_o : std_log=
ic_vector (31 downto 0);
> signal sig_wb_cyc_o : std_log=
ic;
> signal sig_wb_stb_o : std_log=
ic;
> signal sig_wb_sel_o : std_log=
ic_vector ( 3 downto 0);
> signal sig_wb_we_o : std_log=
ic;
> signal sig_wb_ack_i : std_log=
ic;
> signal sig_wb_err_i : std_log=
ic;
> signal sig_wb_rty_i : std_log=
ic;
>
> --- Components
>
> component edk
> port (
>
> ...
>
> o2i_Clk_o_pin :=
out std_logic; -- opb2ipif_0 (for ATAHOST)
> o2i_Reset_o_pin :=
out std_logic;
> o2i_Freeze_o_pin :=
out std_logic;
> o2i_Addr_o_pin :=
out std_logic_vector(0 to 31);
> o2i_AddrValid_o_pin :=
out std_logic;
> o2i_Data_o_pin :=
out std_logic_vector(0 to 31);
> o2i_BE_o_pin :=
out std_logic_vector(0 to 3);
> o2i_Burst_o_pin :=
out std_logic;
> o2i_RNW_o_pin :=
out std_logic;
> o2i_CS_o_pin :=
out std_logic_vector(0 to 0);
> o2i_CE_o_pin :=
out std_logic_vector(0 to 0);
> o2i_RdCE_o_pin :=
out std_logic_vector(0 to 0);
> o2i_WrCE_o_pin :=
out std_logic_vector(0 to 0);
> o2i_Data_i_pin :=
in std_logic_vector(0 to 31);
> o2i_Ack_i_pin :=
in std_logic;
> o2i_Retry_i_pin :=
in std_logic;
> o2i_Error_i_pin :=
in std_logic;
> o2i_ToutSup_i_pin :=
in std_logic;
> o2i_PostedWrInh_i_pin :=
in std_logic;
> o2i_AddrAck_i_pin :=
in std_logic;
>
> ...
>
> );
> end component;
>
> ---------------------------------------------------------=
----------
> --- DISK =
---
> ---------------------------------------------------------=
----------
>
> --- signals
>
> signal sig_disk_irq : std_log=
ic; -- disk module requests
> INTERRUPT
> signal sig_disk_dma_req : std_log=
ic; -- disk module requests
> DMA
> signal sig_disk_dma_ack : std_log=
ic;
>
> --- external pin glue
>
> signal sig_disk_reset_n : std_log=
ic;
> signal sig_disk_dd_i : std_log=
ic_vector (15 downto 0);
> signal sig_disk_dd_o : std_log=
ic_vector (15 downto 0);
> signal sig_disk_dd_t : std_log=
ic;
> signal sig_disk_dd_oe : std_log=
ic;
> signal sig_disk_da : std_log=
ic_vector ( 2 downto 0);
> signal sig_disk_cs0_n : std_log=
ic;
> signal sig_disk_cs1_n : std_log=
ic;
> signal sig_disk_dior_n : std_log=
ic;
> signal sig_disk_diow_n : std_log=
ic;
> signal sig_disk_iordy : std_log=
ic;
> signal sig_disk_intrq : std_log=
ic;
> signal sig_disk_dmarq : std_log=
ic;
> signal sig_disk_dmack_n : std_log=
ic;
>
> signal sig_disk_dasp_n : std_log=
ic; -- not used
> signal sig_disk_pdiag_n : std_log=
ic; -- not used
>
> --- core glue
>
> signal sig_disk_da_u : unsigne=
d(2 downto 0);
>
> signal sig_wb_addr_disk_u : unsigne=
d(6 downto 2);
> signal sig_wb_cs_disk : std_log=
ic;
>
> --- OCIDEC3 core
>
> component atahost_top
>
> generic (
> ARST_LVL : std_log=
ic :=3D '0'; -- asynchronous reset level
>
> TWIDTH : natural=
:=3D 8; -- counter width
>
> -- PIO mode 0 settings (@100MHz clock)
> PIO_mode0_T1 : natural=
:=3D 6; -- 70ns
> PIO_mode0_T2 : natural=
:=3D 28; -- 290ns
> PIO_mode0_T4 : natural=
:=3D 2; -- 30ns
> PIO_mode0_Teoc : natural=
:=3D 23; -- 240ns =3D=3D> T0 - T1 - T2 =3D
> 600 - 70 - 290 =3D 240
>
> -- Multiword DMA mode 0 settings (@100MHz=
clock)
> DMA_mode0_Tm : natural=
:=3D 4; -- 50ns
> DMA_mode0_Td : natural=
:=3D 21; -- 215ns
> DMA_mode0_Teoc : natural=
:=3D 21 -- 215ns =3D=3D> T0 - Td - Tm =3D
> 480 - 50 - 215 =3D 215
> );
>
> port(
>
> -- WISHBONE SYSCON signals
>
> wb_clk_i : in s=
td_logic; -- master clock in
> arst_i : in s=
td_logic :=3D '1'; -- asynchronous active low reset
> wb_rst_i : in s=
td_logic :=3D '0'; -- synchronous active high
> reset
>
> -- WISHBONE SLAVE signals
>
> wb_cyc_i : in s=
td_logic; -- valid bus cycle input
> wb_stb_i : in s=
td_logic; -- strobe/core select input
> wb_ack_o : out s=
td_logic; -- strobe acknowledge output
> wb_rty_o : out s=
td_logic; -- retry output
> wb_err_o : out s=
td_logic; -- error output
> wb_adr_i : in u=
nsigned(6 downto 2); -- A6 =3D '1' ATA devices
> selected
> =
-- A5 =3D
> '1' CS1- asserted, '0' CS0- asserted
> =
-- A4..A2
> ATA address lines
> =
-- A6 =3D '0' ATA
> controller selected
> wb_dat_i : in s=
td_logic_vector(31 downto 0); -- Databus in
> wb_dat_o : out s=
td_logic_vector(31 downto 0); -- Databus out
> wb_sel_i : in s=
td_logic_vector(3 downto 0); -- Byte select
> signals
> wb_we_i : in s=
td_logic; -- Write enable input
> wb_inta_o : out s=
td_logic; -- interrupt request signal IDE0
>
> -- DMA engine signals
>
> DMA_req : out s=
td_logic; -- DMA request
> DMA_Ack : in s=
td_logic; -- DMA acknowledge
>
> -- ATA signals
>
> resetn_pad_o : out s=
td_logic;
> dd_pad_i : in s=
td_logic_vector(15 downto 0);
> dd_pad_o : out s=
td_logic_vector(15 downto 0);
> dd_padoe_o : out s=
td_logic;
> da_pad_o : out u=
nsigned(2 downto 0);
> cs0n_pad_o : out s=
td_logic;
> cs1n_pad_o : out s=
td_logic;
>
> diorn_pad_o : out s=
td_logic;
> diown_pad_o : out s=
td_logic;
> iordy_pad_i : in s=
td_logic;
> intrq_pad_i : in s=
td_logic;
>
> dmarq_pad_i : in s=
td_logic;
> dmackn_pad_o : out s=
td_logic;
>
> debug_pio_sample_indata : out s=
td_logic
> );
> end component;
>
> signal sig_pio_sample : std_log=
ic;
>
> -----------------------------------------------------------------=
----------=AD------------------------
> --- =
---
> --- EDK - Embedded Submodule =
---
> --- =
---
> -----------------------------------------------------------------=
----------=AD------------------------
>
> edk_inst : edk
>
> port map (
>
> ...
>
> --- OPB2IPIF
>
> o2i_Clk_o_pin =
=3D> sig_o2i_Clk_o,
> o2i_Reset_o_pin =
=3D> sig_o2i_Reset_o,
> o2i_Freeze_o_pin =
=3D> sig_o2i_Freeze_o,
> o2i_Addr_o_pin =
=3D> sig_o2i_Addr_o_xil,
> o2i_AddrValid_o_pin =
=3D> sig_o2i_AddrValid_o,
> o2i_Data_o_pin =
=3D> sig_o2i_Data_o_xil,
> o2i_BE_o_pin =
=3D> sig_o2i_BE_o_xil,
> o2i_Burst_o_pin =
=3D> sig_o2i_Burst_o,
> o2i_RNW_o_pin =
=3D> sig_o2i_RNW_o,
> o2i_CS_o_pin =
=3D> sig_o2i_CS_o,
> o2i_CE_o_pin =
=3D> sig_o2i_CE_o,
> o2i_RdCE_o_pin =
=3D> sig_o2i_RdCE_o,
> o2i_WrCE_o_pin =
=3D> sig_o2i_WrCE_o,
> o2i_Data_i_pin =
=3D> sig_o2i_Data_i_xil,
> o2i_Ack_i_pin =
=3D> sig_o2i_Ack_i,
> o2i_Retry_i_pin =
=3D> sig_o2i_Retry_i,
> o2i_Error_i_pin =
=3D> sig_o2i_Error_i,
> o2i_ToutSup_i_pin =
=3D> sig_o2i_ToutSup_i,
> o2i_PostedWrInh_i_pin =
=3D> sig_o2i_PostedWrInh_i,
> o2i_AddrAck_i_pin =
=3D> sig_o2i_AddrAck_i,
>
> ...
>
> );
>
> -----------------------------------------------------------------=
----------=AD------------------------
> --- =
---
> --- =
---
> --- OPB IPIF to WB =
---
> --- =
---
> --- =
---
> -----------------------------------------------------------------=
----------=AD------------------------
>
> --- Reverse stupid xilinx "big endian" addressing
>
> o2i_xil1 : for i in 0 to 31 generate
> sig_o2i_Data_i_xil (31-i) =
<=3D sig_o2i_Data_i (i);
> sig_o2i_Data_o (i) =
<=3D sig_o2i_Data_o_xil (31-i);
> sig_o2i_Addr_o (i) =
<=3D sig_o2i_Addr_o_xil (31-i);
> end generate;
>
> o2i_xil2 : for i in 0 to 3 generate
> sig_o2i_BE_o (i) =
<=3D sig_o2i_BE_o_xil (3-i);
> end generate;
>
> -----------------------------------------------------------------=
----------=AD------------------------
> --- =
---
> --- =
---
> --- HARDDISK - OCIDEC3 from O=
penCores ---
> --- =
---
> --- =
---
> -----------------------------------------------------------------=
----------=AD------------------------
>
> sig_disk_dma_ack <=3D '0';
>
> --- OPB2IPIF -> ATAHOST WISHBONE glue
>
> sig_wb_cs_disk <=3D '1' when sig_o2i_CS_o(=
0)=3D'1' AND sig_o2i_Addr_o
> (15 downto 8) =3D x"00" else '0';
>
> sig_wb_addr_disk_u <=3D unsigned(sig_o2i_Addr_o(6 do=
wnto 2)); -- A6
> =3D '1' ATA devices selected
> =
-- A5 =3D '1' CS1- asserted, '0' CS0- =
asserted
> =
-- A4..A2 ATA address lines
> =
-- A6 =3D '0' ATA controller selected
>
> sig_wb_cyc_o <=3D sig_wb_cs_disk; =
-- valid bus cycle
> sig_wb_stb_o <=3D sig_wb_cs_disk; =
-- strobe/core select
> sig_wb_we_o <=3D NOT(sig_o2i_RNW_o); =
-- Write enable
> sig_wb_sel_o <=3D (others=3D>'1'); =
-- Byte select signals
>
> sig_wb_data_o <=3D sig_o2i_Data_o; =
-- Databus
>
> sig_o2i_Data_i <=3D sig_wb_data_i; =
-- Databus
>
> sig_o2i_Ack_i <=3D sig_wb_ack_i; =
-- strobe ack
> sig_o2i_Retry_i <=3D sig_wb_rty_i; =
-- retry
> sig_o2i_Error_i <=3D sig_wb_err_i; =
-- error
>
> sig_o2i_PostedWrInh_i <=3D '1';
> sig_o2i_ToutSup_i <=3D '1';
>
> --- ATAHOST -> I/O pads glue
>
> sig_disk_da <=3D std_logic_vector(sig_disk_da=
_u);
> sig_disk_dd_t <=3D NOT(sig_disk_dd_oe);
>
> --- Instantiate OCIDEC3 ATAHOST core
>
> disk_inst : atahost_top
>
> generic map (
> ARST_LVL =3D> '0',=
-- we're going to invert reset
>
> TWIDTH =3D> 8, =
-- counter width
>
> -- PIO mode 0 settings (@100MHz c=
lock)
>
> PIO_mode0_T1 =3D> 6, =
-- 70ns
> PIO_mode0_T2 =3D> 28, =
-- 290ns
> PIO_mode0_T4 =3D> 2, =
-- 30ns
> PIO_mode0_Teoc =3D> 23, =
-- 240ns =3D=3D> T0 - T1 - T2 =3D 600=
- 70 -
> 290 =3D 240
>
> -- Multiword DMA mode 0 settings =
(@100MHz clock)
>
> DMA_mode0_Tm =3D> 4, =
-- 50ns
> DMA_mode0_Td =3D> 21, =
-- 215ns
> DMA_mode0_Teoc =3D> 21 =
-- 215ns =3D=3D> T0 - Td - Tm =3D 480=
- 50 -
> 215 =3D 215
> )
>
> port map (
>
> -- WISHBONE SYSCON signals
>
> wb_clk_i =3D> CLK_=
OPB, -- master clock in
> arst_i =3D> NOT(=
RST), -- asynchronous active low reset
> wb_rst_i =3D> '0',=
-- synchronous active high reset
>
> -- WISHBONE SLAVE signals
>
> wb_cyc_i =3D> sig_=
wb_cyc_o, -- valid bus cycle input
> wb_stb_i =3D> sig_=
wb_stb_o, -- strobe/core select input
> wb_ack_o =3D> sig_=
wb_ack_i, -- strobe acknowledge output
> wb_rty_o =3D> sig_=
wb_rty_i, -- retry output
> wb_err_o =3D> sig_=
wb_err_i, -- error output
>
> wb_adr_i =3D> sig_=
wb_addr_disk_u, -- A6 =3D '1' ATA devices
> selected
> =
-- A5 =3D '1' CS1- asserted, '0' CS0- =
asserted
> =
-- A4..A2 ATA address lines
> =
-- A6 =3D '0' ATA controller selected
> wb_dat_i =3D> sig_=
wb_data_o, -- Databus in
> wb_dat_o =3D> sig_=
wb_data_i, -- Databus out
> wb_sel_i =3D> sig_=
wb_sel_o, -- Byte select signals
> wb_we_i =3D> sig_=
wb_we_o, -- Write enable input
>
> wb_inta_o =3D> sig_=
disk_irq, -- interrupt request signal IDE0
>
> -- DMA engine signals
>
> DMA_req =3D> sig_=
disk_dma_req, -- DMA request
> DMA_Ack =3D> sig_=
disk_dma_ack, -- DMA acknowledge
>
> -- ATA signals
>
> resetn_pad_o =3D> sig_=
disk_reset_n,
> dd_pad_i =3D> sig_=
disk_dd_i,
> dd_pad_o =3D> sig_=
disk_dd_o,
> dd_padoe_o =3D> sig_=
disk_dd_oe,
> da_pad_o =3D> sig_=
disk_da_u,
> cs0n_pad_o =3D> sig_=
disk_cs0_n,
> cs1n_pad_o =3D> sig_=
disk_cs1_n,
>
> diorn_pad_o =3D> sig_=
disk_dior_n,
> diown_pad_o =3D> sig_=
disk_diow_n,
> iordy_pad_i =3D> sig_=
disk_iordy,
> intrq_pad_i =3D> sig_=
disk_intrq,
>
> dmarq_pad_i =3D> sig_=
disk_dmarq,
> dmackn_pad_o =3D> sig_=
disk_dmack_n,
>
> debug_pio_sample_indata =3D> sig_=
pio_sample
> );
>
> --- Instantiate external pins
>
> disk_obuf_reset_n : OBUF
>
> generic map (
> DRIVE =3D> 12,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "FAS=
T"
> )
>
> port map (
> I =3D> sig_=
disk_reset_n,
> O =3D> FPGA=
_DD_RESET_N
> );
>
> disk_obuf_cs0_n : OBUF
>
> generic map (
> DRIVE =3D> 12,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "FAS=
T"
> )
>
> port map (
> I =3D> sig_=
disk_cs0_n,
> O =3D> FPGA=
_CS0_N
> );
>
> disk_obuf_cs1_n : OBUF
>
> generic map (
> DRIVE =3D> 12,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "FAS=
T"
> )
>
> port map (
> I =3D> sig_=
disk_cs1_n,
> O =3D> FPGA=
_CS1_N
> );
>
> disk_obuf_da0_n : OBUF
>
> generic map (
> DRIVE =3D> 12,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "FAS=
T"
> )
>
> port map (
> I =3D> sig_=
disk_da (0),
> O =3D> FPGA=
_DA0
> );
>
> disk_obuf_da1_n : OBUF
>
> generic map (
> DRIVE =3D> 12,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "FAS=
T"
> )
>
> port map (
> I =3D> sig_=
disk_da (1),
> O =3D> FPGA=
_DA1
> );
>
> disk_obuf_da2_n : OBUF
>
> generic map (
> DRIVE =3D> 12,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "FAS=
T"
> )
>
> port map (
> I =3D> sig_=
disk_da (2),
> O =3D> FPGA=
_DA2
> );
>
> disk_iobuf_dd : for i in 0 to 15 generate U1 : IOBUF
>
> generic map (
> CAPACITANCE =3D> "NOR=
MAL",
> DRIVE =3D> 12,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "FAS=
T"
> )
>
> port map (
> I =3D> sig_=
disk_dd_o (i),
> O =3D> sig_=
disk_dd_i (i),
> T =3D> sig_=
disk_dd_t,
> IO =3D> FPGA=
_DD_DD (i)
> );
>
> end generate;
>
> disk_obuf_dior_n : OBUF
>
> generic map (
> DRIVE =3D> 16,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "FAS=
T"
> )
>
> port map (
> I =3D> sig_=
disk_dior_n,
> O =3D> FPGA=
_DIOR_HDMARDY_HSTB
> );
>
> disk_obuf_diow_n : OBUF
>
> generic map (
> DRIVE =3D> 16,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "FAS=
T"
> )
>
> port map (
> I =3D> sig_=
disk_diow_n,
> O =3D> FPGA=
_DIOW_STOP
> );
>
> disk_obuf_dmack_n : OBUF
>
> generic map (
> DRIVE =3D> 12,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "FAS=
T"
> )
>
> port map (
> I =3D> sig_=
disk_dmack_n,
> O =3D> FPGA=
_DMACK_N
> );
>
> disk_iobuf_dmarq : IOBUF
>
> generic map (
> CAPACITANCE =3D> "NOR=
MAL",
> DRIVE =3D> 4,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "SLO=
W"
> )
>
> port map (
> I =3D> '0',
> O =3D> sig_=
disk_dmarq,
> T =3D> '1',
> IO =3D> FPGA=
_DMARQ
> );
>
> disk_iobuf_intrq : IOBUF
>
> generic map (
> CAPACITANCE =3D> "NOR=
MAL",
> DRIVE =3D> 4,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "SLO=
W"
> )
>
> port map (
> I =3D> '0',
> O =3D> sig_=
disk_intrq,
> T =3D> '1',
> IO =3D> FPGA=
_INTRQ
> );
>
> disk_iobuf_iordy : IOBUF
>
> generic map (
> CAPACITANCE =3D> "NOR=
MAL",
> DRIVE =3D> 4,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "SLO=
W"
> )
>
> port map (
> I =3D> '0',
> O =3D> sig_=
disk_iordy,
> T =3D> '1',
> IO =3D> FPGA=
_IORDY_DDMARDY_DSTB
> );
>
> --- Pins outside of the scope of the core
>
> disk_obuf_csel : OBUF
>
> generic map (
> DRIVE =3D> 4,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "SLO=
W"
> )
>
> port map (
> I =3D> '0',
> O =3D> FPGA=
_CSEL
> );
>
> --- Pins that are not used at all
>
> disk_ibuf_dasp_n : IBUF
>
> generic map (
> CAPACITANCE =3D> "LOW=
",
> IOSTANDARD =3D> "DEF=
AULT"
> )
>
> port map (
> I =3D> FPGA=
_DASP_N,
> O =3D> sig_=
disk_dasp_n
> );
>
> disk_ibuf_pdiag_n : IBUF
>
> generic map (
> CAPACITANCE =3D> "LOW=
",
> IOSTANDARD =3D> "DEF=
AULT"
> )
>
> port map (
> I =3D> FPGA=
_PDIAG_N,
> O =3D> sig_=
disk_pdiag_n
> );
>
> disk_obuf_sp1 : OBUF
>
> generic map (
> DRIVE =3D> 4,
> IOSTANDARD =3D> "DEF=
AULT",
> SLEW =3D> "SLO=
W"
> )
>
> port map (
> I =3D> '0',
> O =3D> DD_S=
P1
> );
>
> --- Pullup/pulldown resistors
>
> disk_pulldown_dd7 : PULLDOWN
> port map (
> O =3D> FPGA=
_DD_DD (7) -- ATA7 pg.38: 10k pulldown on DD7 to
> detect absence of a device
> );
>
> disk_pulldown_dmarq : PULLDOWN
> port map (
> O =3D> FPGA=
_DMARQ -- ATA7 pg.38: 5k6 pulldown
> );
>
> disk_pullup_iordy : PULLUP
> port map (
> O =3D> FPGA=
_IORDY_DDMARDY_DSTB -- ATA7 pg.38: 4k7 pullup
> );
>
> disk_pulldown_intrq : PULLDOWN
> port map (
> O =3D> FPGA=
_INTRQ -- ATA7 pg.38: 6k2 pulldown -> selects
> active-high
> );
Thanks Marc,
Well, I am a Verilog guy, will take some time to decipher VHDL code
into Verilog.
Will let you know in case I need more details.
Best Wishes,
Farhan
Article: 118137Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals. We need to connect a CMOS image sensor and a FPGA chip. The distance between them is approximately 1 meter. The output signal of the sensor is 3.3v and 24MHz. However, the length of the original cable of it is only 1 centimeter, so it should be prolonged. If they are connected by a cable directly, the signal would attenuate greatly which will cause the system doesn't work. In my opinion, an interconnecting circuit should be added between the sensor and the FPGA chip to process the signal before and after the transmission. By now, the methods I have found are as follows: 1, Using LVDS signal Transceiver and Receiver The drawback of the method is: there are more than 10 bits signals, which need many of this kind of chips. It will take too much place in PCB and it also cost much. 2, Using chips of Serializer and Deserializer. Both Maxim and National Semiconductor have such chips such as MAX9247 and DS90C241. It is a good method. Unfortunately the solution is fired by my tutor because these chips are expensive. My question is whether there are any other solutions? More cheap will be better. Thanks a lot.Article: 118138
"X.Y." <Xieyu1219@gmail.com> wrote in message news:1176904353.399657.160000@p77g2000hsh.googlegroups.com... > Seeking the solutions of high speed interconnection for the long > distance transmission of 3.3v/24MHz signals. > > We need to connect a CMOS image sensor and a FPGA chip. The distance > between them is approximately 1 meter. The output signal of the sensor > is 3.3v and 24MHz. However, the length of the original cable of it is > only 1 centimeter, so it should be prolonged. If they are connected by > a cable directly, the signal would attenuate greatly which will cause > the system doesn't work. In my opinion, an interconnecting circuit > should be added between the sensor and the FPGA chip to process the > signal before and after the transmission. More cheap will > be better. Thanks a lot. > Hi XY, Use a length of ribbon cable. Make every other conductor ground. Use source termination on your signals to match the cable impedance in the gnd-sig-gnd mode. Make sure you connect all the grounds properly at both ends of the cable. It works well for IDE ATA parallel disks up to 133MBytes/second. HTH, Syms. p.s. BTW., ribbon cable makes great speaker wire. It's flat and fits under the carpet!Article: 118139
Thanks for the replies. Jonathan, that did the trick. Hmmm, seems a bit more involved than with NC-Sim. But ModelSim seems to be the better simulator for us...at least with respects the FPGA/Xilinx simulation.Article: 118140
Here is working (Actually Implement in Silicon) code: module Delay(Clk, DataIn, DataOut); input Clk; input DataIn; output DataOut; reg BitRAM [0:950000]; reg ShiftOutput; reg [24:0] InAddress; reg [24:0] OutAddress; reg [9:0] ClkDiv; reg LocalClk; reg Cycle; always @(posedge Clk) begin ClkDiv<=ClkDiv+1; if(ClkDiv==25) begin LocalClk = ~LocalClk; ClkDiv<=0; end end always @(posedge LocalClk) begin Cycle = ~Cycle; end assign DataOut= ShiftOutput; //Calculate the addresses of the last and first bit of the shift register always @(posedge LocalClk) begin if(Cycle == 1) begin InAddress <= InAddress + 1; if(InAddress == 950000) begin InAddress <=0; end end end always @(posedge LocalClk) begin if(Cycle == 0) begin OutAddress <= InAddress + 1; if(OutAddress == 950000) begin OutAddress <=0; end end end //Implement a Large Circular Buffer always @(posedge LocalClk) begin if(Cycle == 0) ShiftOutput<=BitRAM[OutAddress]; end //Implement a Large Circular Buffer always @(posedge LocalClk) begin if(Cycle == 1) BitRAM[InAddress] <= DataIn; end endmoduleArticle: 118141
"ferorcue" <le_marq@hotmail.com> wrote in message news:1176876732.441142.274040@b75g2000hsg.googlegroups.com... > Hello, > > First of all I will make my question: Could you please say me how > many Masters can be connected to the Bus when the BFM simulation is > been used? > > I created a coprocessor for the embedded PowerPC, and two files to > implement a bridge between the PLB Bus and the Bus of my coprocessor > ( small bus called On Chip Bus). > I have a Master which is able to read all the operations from a txt > file. this is my sistem > > BFM Bus > file.txt --> Master_1 -->| > | > |-->bridge_plb2ocb > | > coprocessor(bus on chip bus ocb) > |-->bridge_ocb2plb > | > Register<--| > > I am using the BFM simulation because I got always problems with the > behavioural simulation( i have a problem that i posted here and i do > not have the solution yet( > http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/c4be67a12afae957/1098d98a5af6caf8?lnk=gst&q=ferorcue&rnum=2&hl=en#1098d98a5af6caf8 > )) > > > The point is that Master_1 and bridge_ocb2plb are both masters and the > system it is not working. Only the master that is mapped in the memory > address 0x00000000 it is working. I checked first with Master_1 mapped > in 0x0, and later with bridge_ocb2plb mapped in 0x0, and the bus of > the BFM simulation only answer or hear the request of one of both > masters, the one which is mapped in the 0x0. > > I think that you have more experience with embedded systems, do you > think that what i am writing here make sense? It is possible that the > BFM simulation only allow to have one Master in our systems? Is there > another possibility to simulate a system with 2,3 or more masters? > > > Thank you very much for your answers. > > Note: if the solution it is to use the behaviural simulation, could > you please help my with my problem using this simulation, i have post > it here with the Subject: > XPS behavioral simulation fails: the design is not loaded > In general, a bus structure will support multiple masters. You will require some arbitration logic and some muxing logic to mux the winning master onto the bus. Does the bus protocol you are using support arbitartion (request/grant sort of thing)? MikeArticle: 118142
Symon wrote: > "X.Y." <Xieyu1219@gmail.com> wrote in message > news:1176904353.399657.160000@p77g2000hsh.googlegroups.com... >> Seeking the solutions of high speed interconnection for the long >> distance transmission of 3.3v/24MHz signals. >> >> We need to connect a CMOS image sensor and a FPGA chip. The distance >> between them is approximately 1 meter. The output signal of the sensor >> is 3.3v and 24MHz. However, the length of the original cable of it is >> only 1 centimeter, so it should be prolonged. If they are connected by >> a cable directly, the signal would attenuate greatly which will cause >> the system doesn't work. In my opinion, an interconnecting circuit >> should be added between the sensor and the FPGA chip to process the >> signal before and after the transmission. More cheap will >> be better. Thanks a lot. >> > Hi XY, > Use a length of ribbon cable. Make every other conductor ground. Use source > termination on your signals to match the cable impedance in the gnd-sig-gnd > mode. Make sure you connect all the grounds properly at both ends of the > cable. It works well for IDE ATA parallel disks up to 133MBytes/second. HTH, > Syms. > p.s. BTW., ribbon cable makes great speaker wire. It's flat and fits under > the carpet! > > Great idea about the speaker wire! I'll have to try that next time -Eli [Someone who hasn't been into that low cost wire adds 'distortion']Article: 118143
X.Y. wrote: > Seeking the solutions of high speed interconnection for the long > distance transmission of 3.3v/24MHz signals. > > We need to connect a CMOS image sensor and a FPGA chip. The distance > between them is approximately 1 meter. The output signal of the sensor > is 3.3v and 24MHz. However, the length of the original cable of it is > only 1 centimeter, so it should be prolonged. If they are connected by > a cable directly, the signal would attenuate greatly which will cause > the system doesn't work. In my opinion, an interconnecting circuit > should be added between the sensor and the FPGA chip to process the > signal before and after the transmission. By now, the methods I have > found are as follows: > 1, Using LVDS signal Transceiver and Receiver > The drawback of the method is: there are more than 10 bits signals, > which need many of this kind of chips. It will take too much place in > PCB and it also cost much. > 2, Using chips of Serializer and Deserializer. > Both Maxim and National Semiconductor have such chips such as MAX9247 > and DS90C241. It is a good method. Unfortunately the solution is fired > by my tutor because these chips are expensive. > > My question is whether there are any other solutions? More cheap will > be better. Thanks a lot. SERDES chips aren't very expensive. And the (12-bit) Fairchild Semi FIN12AC are very cheap - under $2 each and your tutor can probably get a couple of free samples.Article: 118144
http://www.seventech.it/english/prodotti.php Jamma platform for gaming with SDK ThanxArticle: 118145
Thank you for all the suggestions. I am led to suspect it's a timing problem and I will investigate that. The data sheet and the handbook barely mentions anything about Setup/Hold/Cycle time requirements or otherwise I am looking in the wrong places. On Apr 17, 10:21 pm, Newman <newman5...@yahoo.com> wrote: > On Apr 17, 11:02 pm, Peter Alfke <a...@sbcglobal.net> wrote: > > > > > A few ideas: > > Are you sure about the content of the various locations? > > Could the error have happened when you wrote data into the BRAM? > > > When reading, read twicein sequence from the same address. Then you > > will see whether this is a read pipelining problem, or whether you > > really are always reading the wrong information. > > The error has to somewhere in your timing. > > > Be a sleuth! > > Peter Alfke > > > On Apr 17, 7:12 pm, Gabor <g...@alacron.com> wrote: > > > > On Apr 17, 8:13 pm, "M. Hamed" <mhs...@gmail.com> wrote: > > > > > I am getting a strange error with Block RAM on a Spartan 3 FPGA. Every > > > > time I issue a read, the word at the location previous to the given > > > > address is read. For example if I'm reading from address 5, the word > > > > at address 4 is output instead. The data written to the block seems > > > > correct when I view it in ModelSim so I assume it's something with the > > > > read. > > > > This does seem strange. Are your writes and reads always made to > > > sequential memory locations (i.e. 1, 2, 3, ... in order)? Perhaps the > > > error is in cycle timing and not address? > > > > > Viewing signals at the BRAM input in ModelSim shows the correct > > > > address at the input of port A and the read clock signal goes high but > > > > the wrong word appear at the output. ENA is always 1 and WEA is always > > > > 0. The very most recent Write to this same address (from a different > > > > port) also shows the correct value being written. > > > > > The design works correctly in RTL but this problem only occurs with > > > > the post-route netlist. > > > > > Did anyone encounter a similar problem like this before and can give > > > > me a hint on what's going on. > > > > The only time I've seen something similar was with an old version of > > > the > > > BRAM simulation models that needed a slight positive hold time in the > > > address. In effect it was the behavioral simulation that incorrectly > > > gave > > > the read data on the same clock that the address was presented. In > > > fact > > > BRAM's are registered in the Spartan 3 (and Virtex 2) series, so the > > > output data should have changed on the following clock cycle. In the > > > post-PAR timing simulation, the output changed on the following clock > > > cycle as expected. > > > > > Thank you.- Hide quoted text - > > > - Show quoted text - > > If you generated the block RAM with coregen, there is an option to > preload the RAM with a coe file. You can then simulate the block RAM > both at the RTL and post P&R level, disable the writes in the code > and > see if you read the expected data designated by the coe file at the > desired addresses. > > There are some instances when the RTL does not match the post P&R > simulation. i.e. (sensitivity list is incomplete in a combinatorial > process, > improper use of blocking assignments and variables) I don't use the > later two items > in synthesizable code, so I don't have much experience with them, but > then > again, I never get an RTL vs post P&R simulation mismatch because of > them. > > Hope this helps, > NewmanArticle: 118146
I hope you understand that the BRAM is a synchronous device. When you read data, you first must apply the address, then you give it a rising clock edge, and as a result of the clock edge, you get the data that is stored at the above mentioned address location. Some people think that the read operation should be just combinatorial, providing output data when an address is applied. That is NOT the way the BlockRAM works. It does nothing until you apply a rising clock edge. From a timing point of view, it behaves like a flip- flop or register. Peter Alfke, Xilinx Applications On Apr 18, 9:23 am, "M. Hamed" <mhs...@gmail.com> wrote: > Thank you for all the suggestions. I am led to suspect it's a timing > problem and I will investigate that. The data sheet and the handbook > barely mentions anything about Setup/Hold/Cycle time requirements or > otherwise I am looking in the wrong places. > > On Apr 17, 10:21 pm, Newman <newman5...@yahoo.com> wrote: > > > On Apr 17, 11:02 pm, Peter Alfke <a...@sbcglobal.net> wrote: > > > > A few ideas: > > > Are you sure about the content of the various locations? > > > Could the error have happened when you wrote data into the BRAM? > > > > When reading, read twicein sequence from the same address. Then you > > > will see whether this is a read pipelining problem, or whether you > > > really are always reading the wrong information. > > > The error has to somewhere in your timing. > > > > Be a sleuth! > > > Peter Alfke > > > > On Apr 17, 7:12 pm, Gabor <g...@alacron.com> wrote: > > > > > On Apr 17, 8:13 pm, "M. Hamed" <mhs...@gmail.com> wrote: > > > > > > I am getting a strange error with Block RAM on a Spartan 3 FPGA. Every > > > > > time I issue a read, the word at the location previous to the given > > > > > address is read. For example if I'm reading from address 5, the word > > > > > at address 4 is output instead. The data written to the block seems > > > > > correct when I view it in ModelSim so I assume it's something with the > > > > > read. > > > > > This does seem strange. Are your writes and reads always made to > > > > sequential memory locations (i.e. 1, 2, 3, ... in order)? Perhaps the > > > > error is in cycle timing and not address? > > > > > > Viewing signals at the BRAM input in ModelSim shows the correct > > > > > address at the input of port A and the read clock signal goes high but > > > > > the wrong word appear at the output. ENA is always 1 and WEA is always > > > > > 0. The very most recent Write to this same address (from a different > > > > > port) also shows the correct value being written. > > > > > > The design works correctly in RTL but this problem only occurs with > > > > > the post-route netlist. > > > > > > Did anyone encounter a similar problem like this before and can give > > > > > me a hint on what's going on. > > > > > The only time I've seen something similar was with an old version of > > > > the > > > > BRAM simulation models that needed a slight positive hold time in the > > > > address. In effect it was the behavioral simulation that incorrectly > > > > gave > > > > the read data on the same clock that the address was presented. In > > > > fact > > > > BRAM's are registered in the Spartan 3 (and Virtex 2) series, so the > > > > output data should have changed on the following clock cycle. In the > > > > post-PAR timing simulation, the output changed on the following clock > > > > cycle as expected. > > > > > > Thank you.- Hide quoted text - > > > > - Show quoted text - > > > If you generated the block RAM with coregen, there is an option to > > preload the RAM with a coe file. You can then simulate the block RAM > > both at the RTL and post P&R level, disable the writes in the code > > and > > see if you read the expected data designated by the coe file at the > > desired addresses. > > > There are some instances when the RTL does not match the post P&R > > simulation. i.e. (sensitivity list is incomplete in a combinatorial > > process, > > improper use of blocking assignments and variables) I don't use the > > later two items > > in synthesizable code, so I don't have much experience with them, but > > then > > again, I never get an RTL vs post P&R simulation mismatch because of > > them. > > > Hope this helps, > > NewmanArticle: 118147
Hi all, I have a few issues with how to use the BBD file. key words ISE 8.2, XPS 8.2, BBD file, CORE Generator step1. I create a core using coregenerator, generate .ngc (netlist) file out of it. step2. I use the core as a submodule in my design .vhd which is Master/ Slave OPB. step 3. In the system->pcores->mydesign->data/ i create a .bbd file and put the .ngc file name into it step 4 In the system->pcores->mydesign-> i create a netlist folder and put the .ngc (of the generated core) file in it now when i generate bitstream it gives me error in the Ngdbuild ============================================================= here is the error ........................ ERROR:NgdBuild:604 - logical block 'opb_master_ml300_camera_bridge_0/opb_master_ml300_camera_bridge_0/ user_fifo1 /block0' with type 'fifo_generator_v3_2' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'fifo_generator_v3_2' is not supported in target 'virtex2p'. ERROR:NgdBuild:604 - logical block 'opb_master_ml300_camera_bridge_0/opb_master_ml300_camera_bridge_0/ user_fifo1 /block1' with type 'fifo_generator_v3_2' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'fifo_generator_v3_2' is not supported in target 'virtex2p'. ......................... ======================================================== here is the contents of the bbd file ####################### FILES ####################### fifo_generator_v3_2.ngc ========================================================= any ideas where i am going wrong. please ask me for more info if you think the info is not enough. with warm regards to the design community. chakra.Article: 118148
Hi, Just wondering whether somebody could let me know the different between IOB and DIFFM/DIFFS for Xilinx FPGA. The following pin assignment constraints were specified in .ucf for Xilinx XC2V8000 FPGA. NET RAM1_SnWBYTE(0) LOC=AM27; NET RAM1_SnWBYTE(1) LOC=AM26; NET RAM1_SnWBYTE(2) LOC=AP27; NET RAM1_SnWBYTE(3) LOC=AP26; But I got the following error complaining about constaints for RAM0_SnWBYTE[1] and RAM0_SnWBYTE[2] Couldn't pass the place and route process, resolved that DIFFM RAM0_SnWBYTE[1] is restricted such that it may not be placed in a IOB. Couldn't pass the place and route process, resolved that DIFFM RAM0_SnWBYTE[2] is restricted such that it may not be placed in a IOB. Any idea why this happened? Cheers, -WilliamArticle: 118149
Finally I got simulation of logicores in webpack 9.1.03i to work with the ISE simulator. However, these messages appear in the transcript window: Running Fuse ... WARNING:HDLParsers:3583 - File "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" which file "C:/Xilinx91i/theller/mydesign/divider.vhd" depends on is modified, but has not been compiled. You may need to compile "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" first. Compiling vhdl file "C:/Xilinx91i/theller/mydesign/detector.vhd" in Library work. Entity <detector> compiled. Entity <detector> (Architecture <behavioral>) compiled. WARNING:HDLParsers:3583 - File "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" which file "C:/Xilinx91i/theller/mydesign/divider.vhd" depends on is modified, but has not been compiled. You may need to compile "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" first. WARNING:HDLParsers:3583 - File "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" which file "C:/Xilinx91i/vhdl/src/ieee/std_logic_unsigned.vhd" depends on is modified, but has not been compiled. You may need to compile "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" first. WARNING:HDLParsers:3583 - File "C:/Xilinx91i/vhdl/src/ieee/std_logic_unsigned.vhd" which file "C:/Xilinx91i/theller/mydesign/detector.vhd" depends on is modified, but has not been compiled. You may need to compile "C:/Xilinx91i/vhdl/src/ieee/std_logic_unsigned.vhd" first. WARNING:HDLParsers:3583 - File "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" which file "C:/Xilinx91i/theller/mydesign/detector.vhd" depends on is modified, but has not been compiled. You may need to compile "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" first. Compiling vhdl file "C:/Xilinx91i/theller/mydesign/detector_tbw.vhw" in Library work. Entity <detector_tbw> compiled. Entity <detector_tbw> (Architecture <testbench_arch>) compiled. Parsing "detector_tbw_beh.prj": 1.84 Codegen work/detector: 0.00 Codegen work/detector/Behavioral: 0.41 Codegen work/detector_tbw: 0.00 Codegen work/detector_tbw/testbench_arch: 0.34 Building detector_tbw_isim_beh.exe Running ISim simulation engine ... This is a Lite version of ISE Simulator. Simulator is doing circuit initialization process. Finished circuit initialization process. Apparently this file "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" isn't present on my system, it is probably a filename in Xilinx source code. How can I recompile this file??? Other files like these "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" "C:/Xilinx91i/vhdl/src/ieee/std_logic_unsigned.vhd" "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" *are* present on my system, but *I* did not change them. How can it be that they need to be compiled? How would I compile them? Do I have a broken installation? Or should I not be bothered at all by these messages? Thanks for any help, Thomas
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