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On Apr 18, 4:24 am, nezhate <mazouz.nezh...@gmail.com> wrote: > Hi all, > I'm using Ise 9.1.03i. when I try to print a code written in Ise text > editor, I get this error: > "Print fails because the default printer has not been selected", and > when the design summary is opened I can see the window "steup printer" > and my default printer is automatically selected. > How to configure printer for ise text editor? > thanks. Wow...somebody actually uses the ISE text editor? I thought everyone just used emacs. -aArticle: 118151
Thank you Peter for the clarification. I do understand that now. I realized that for a read, I was outputting the clock and address at the same time as if it was combinational. My problem now is to figure out a way to fit an extra cycle in my state machine to issue the clock one cycle after the address is output. /MHS On Apr 18, 9:37 am, Peter Alfke <p...@xilinx.com> wrote: > I hope you understand that the BRAM is a synchronous device. When you > read data, you first must apply the address, then you give it a rising > clock edge, and as a result of the clock edge, you get the data that > is stored at the above mentioned address location. > Some people think that the read operation should be just > combinatorial, providing output data when an address is applied. That > is NOT the way the BlockRAM works. It does nothing until you apply a > rising clock edge. From a timing point of view, it behaves like a flip- > flop or register. > Peter Alfke, Xilinx Applications > > On Apr 18, 9:23 am, "M. Hamed" <mhs...@gmail.com> wrote: > > > Thank you for all the suggestions. I am led to suspect it's a timing > > problem and I will investigate that. The data sheet and the handbook > > barely mentions anything about Setup/Hold/Cycle time requirements or > > otherwise I am looking in the wrong places. > > > On Apr 17, 10:21 pm, Newman <newman5...@yahoo.com> wrote: > > > > On Apr 17, 11:02 pm, Peter Alfke <a...@sbcglobal.net> wrote: > > > > > A few ideas: > > > > Are you sure about the content of the various locations? > > > > Could the error have happened when you wrote data into the BRAM? > > > > > When reading, read twicein sequence from the same address. Then you > > > > will see whether this is a read pipelining problem, or whether you > > > > really are always reading the wrong information. > > > > The error has to somewhere in your timing. > > > > > Be a sleuth! > > > > Peter Alfke > > > > > On Apr 17, 7:12 pm, Gabor <g...@alacron.com> wrote: > > > > > > On Apr 17, 8:13 pm, "M. Hamed" <mhs...@gmail.com> wrote: > > > > > > > I am getting a strange error with Block RAM on a Spartan 3 FPGA. Every > > > > > > time I issue a read, the word at the location previous to the given > > > > > > address is read. For example if I'm reading from address 5, the word > > > > > > at address 4 is output instead. The data written to the block seems > > > > > > correct when I view it in ModelSim so I assume it's something with the > > > > > > read. > > > > > > This does seem strange. Are your writes and reads always made to > > > > > sequential memory locations (i.e. 1, 2, 3, ... in order)? Perhaps the > > > > > error is in cycle timing and not address? > > > > > > > Viewing signals at the BRAM input in ModelSim shows the correct > > > > > > address at the input of port A and the read clock signal goes high but > > > > > > the wrong word appear at the output. ENA is always 1 and WEA is always > > > > > > 0. The very most recent Write to this same address (from a different > > > > > > port) also shows the correct value being written. > > > > > > > The design works correctly in RTL but this problem only occurs with > > > > > > the post-route netlist. > > > > > > > Did anyone encounter a similar problem like this before and can give > > > > > > me a hint on what's going on. > > > > > > The only time I've seen something similar was with an old version of > > > > > the > > > > > BRAM simulation models that needed a slight positive hold time in the > > > > > address. In effect it was the behavioral simulation that incorrectly > > > > > gave > > > > > the read data on the same clock that the address was presented. In > > > > > fact > > > > > BRAM's are registered in the Spartan 3 (and Virtex 2) series, so the > > > > > output data should have changed on the following clock cycle. In the > > > > > post-PAR timing simulation, the output changed on the following clock > > > > > cycle as expected. > > > > > > > Thank you.- Hide quoted text - > > > > > - Show quoted text - > > > > If you generated the block RAM with coregen, there is an option to > > > preload the RAM with a coe file. You can then simulate the block RAM > > > both at the RTL and post P&R level, disable the writes in the code > > > and > > > see if you read the expected data designated by the coe file at the > > > desired addresses. > > > > There are some instances when the RTL does not match the post P&R > > > simulation. i.e. (sensitivity list is incomplete in a combinatorial > > > process, > > > improper use of blocking assignments and variables) I don't use the > > > later two items > > > in synthesizable code, so I don't have much experience with them, but > > > then > > > again, I never get an RTL vs post P&R simulation mismatch because of > > > them. > > > > Hope this helps, > > > NewmanArticle: 118152
On Apr 17, 2:27 pm, "mans" <(myname_here)_123...@yahoo.com> wrote: > Hello, > > I am newbie in VHDL. I want to create a library with several pkg on it so > when I am creating a new library; I could add it to my new project and then > use the pakage. > > What I am doing now is as follow: > > Every time that I create a new project, I am creating a new library in its > library view and then add all of my packages source code to it. > > The main problem in this technique is that I need to create the library > every time that I create a new project. Is there any way that I can create a > library that it is included automatically to all newly generated projects? > > One solution is to create a library in one project and then tell its path to > other projects, but how can I do this? I would use a source-code control system like Subversion. The "libraries" are kept in the repository as their own "project." Then you attach an externals property to your project's source directory and have that externals point to the libraries. So every time you check out a project you also grab the libraries. Works for me. Note that source files are always in a separate directory from the fitter stuff. Never "copy" source files to the "project directory," as that's a recipe for disaster. Note that I don't use any of what Xilinx calls their revision-control stuff. All of the subversion stuff is done either through the command line or with TortoiseSVN. -aArticle: 118153
On Apr 18, 2:38 am, "mans" <(myname_here)_123...@yahoo.com> wrote: > Hello, > Is there any facility in ISE to automatically indent source code? The > similar technique is available in C/C++ editors and I it is very simple to > add it to ISE for indenting smartly VHDL and Verilog source codes. > > Regards Wow, TWO votes for the ISE text editor ... -aArticle: 118154
Hi Edmond, You can add in include Signal Tap II into your first pass compile by directly instantiating it in your code. There is a Signal Tap II megafunction that you can configure in the MegaWizard Plugin Manager (Tools -> MegaWizard Plugin Manager). The config options are relatively straightforward. When you synthesize, Precision will treat the module/entity as a black box. Check out page 24 of http://www.altera.com/literature/hb/qts/qts_qii= 51011.pdf. This describes the flow for black box instantiation with Precision. Also, I guess you want to have signal tap in the first pass because of the long re-compile times. With the Signal Tap GUI flow, you don't have to go through a complete recompile. There is an option to add Signal Tap nodes in post-fit. (i.e. no synthesis of your original design, just an addition of the Signal Tap logic). You can do this by turning on Incremental compile in the settings dialog box (it's defaulted to on) and checking the "Incremental Compilation" in the Signal Tap GUI. Hope this helps, FQ On Apr 16, 5:46 am, "Edmond Cot=E9" <edmond.c...@gmail.com> wrote: > Hi, > > Iamcurrentlyworkingwith alargedesignwithlongsynthesisand > implementation times. Thedesignis synthesized with Precision RTL and > the gate-level netlist is exported manually to Quartus II by means of > an EDIF file. I use a TCL script to automate implementation, mainly to > automatically tweak a few parameters. > > I would like to modify my Quartus II implementation script to add a > SignalTap II component on the *first* implementation pass, and I would > also like to be able to assign which pins and buses I'd like to debug > without having to deal with the GUI. I went through most of the > documentation, and played with the GUI quite a bit, and could not > manage to add the SignalTap II component without first implementing > the entiredesign. I typically receive the > "Compile the project to continue" message. > > Any and all advice is appreciated, thanks for your help! > > EdmondArticle: 118155
Un bel giorno X.Y. digiṭ: > 1, Using LVDS signal Transceiver and Receiver > The drawback of the method is: there are more than 10 bits signals, > which need many of this kind of chips. It will take too much place in > PCB and it also cost much. There are single chip with many channels, for example: http://focus.ti.com/docs/prod/folders/print/sn65mlvd080.html > 2, Using chips of Serializer and Deserializer. > Both Maxim and National Semiconductor have such chips such as MAX9247 > and DS90C241. It is a good method. Unfortunately the solution is fired > by my tutor because these chips are expensive. I don't think so: http://focus.ti.com/docs/prod/folders/print/sn65lv1021.html -- emboliaschizoide.splinder.comArticle: 118156
You don't need a full cycle. You only have to satisfy the set-up time, which is around 1 or 2 ns prior to the clock edge. Maybe you can use the opposite-polarity clock edge. Peter Alfke On Apr 18, 10:44 am, "M. Hamed" <mhs...@gmail.com> wrote: > Thank you Peter for the clarification. I do understand that now. I > realized that for a read, I was outputting the clock and address at > the same time as if it was combinational. My problem now is to figure > out a way to fit an extra cycle in my state machine to issue the clock > one cycle after the address is output. > > /MHS > > On Apr 18, 9:37 am, Peter Alfke <p...@xilinx.com> wrote: > > > I hope you understand that the BRAM is a synchronous device. When you > > read data, you first must apply the address, then you give it a rising > > clock edge, and as a result of the clock edge, you get the data that > > is stored at the above mentioned address location. > > Some people think that the read operation should be just > > combinatorial, providing output data when an address is applied. That > > is NOT the way the BlockRAM works. It does nothing until you apply a > > rising clock edge. From a timing point of view, it behaves like a flip- > > flop or register. > > Peter Alfke, Xilinx Applications > > > On Apr 18, 9:23 am, "M. Hamed" <mhs...@gmail.com> wrote: > > > > Thank you for all the suggestions. I am led to suspect it's a timing > > > problem and I will investigate that. The data sheet and the handbook > > > barely mentions anything about Setup/Hold/Cycle time requirements or > > > otherwise I am looking in the wrong places. > > > > On Apr 17, 10:21 pm, Newman <newman5...@yahoo.com> wrote: > > > > > On Apr 17, 11:02 pm, Peter Alfke <a...@sbcglobal.net> wrote: > > > > > > A few ideas: > > > > > Are you sure about the content of the various locations? > > > > > Could the error have happened when you wrote data into the BRAM? > > > > > > When reading, read twicein sequence from the same address. Then you > > > > > will see whether this is a read pipelining problem, or whether you > > > > > really are always reading the wrong information. > > > > > The error has to somewhere in your timing. > > > > > > Be a sleuth! > > > > > Peter Alfke > > > > > > On Apr 17, 7:12 pm, Gabor <g...@alacron.com> wrote: > > > > > > > On Apr 17, 8:13 pm, "M. Hamed" <mhs...@gmail.com> wrote: > > > > > > > > I am getting a strange error with Block RAM on a Spartan 3 FPGA. Every > > > > > > > time I issue a read, the word at the location previous to the given > > > > > > > address is read. For example if I'm reading from address 5, the word > > > > > > > at address 4 is output instead. The data written to the block seems > > > > > > > correct when I view it in ModelSim so I assume it's something with the > > > > > > > read. > > > > > > > This does seem strange. Are your writes and reads always made to > > > > > > sequential memory locations (i.e. 1, 2, 3, ... in order)? Perhaps the > > > > > > error is in cycle timing and not address? > > > > > > > > Viewing signals at the BRAM input in ModelSim shows the correct > > > > > > > address at the input of port A and the read clock signal goes high but > > > > > > > the wrong word appear at the output. ENA is always 1 and WEA is always > > > > > > > 0. The very most recent Write to this same address (from a different > > > > > > > port) also shows the correct value being written. > > > > > > > > The design works correctly in RTL but this problem only occurs with > > > > > > > the post-route netlist. > > > > > > > > Did anyone encounter a similar problem like this before and can give > > > > > > > me a hint on what's going on. > > > > > > > The only time I've seen something similar was with an old version of > > > > > > the > > > > > > BRAM simulation models that needed a slight positive hold time in the > > > > > > address. In effect it was the behavioral simulation that incorrectly > > > > > > gave > > > > > > the read data on the same clock that the address was presented. In > > > > > > fact > > > > > > BRAM's are registered in the Spartan 3 (and Virtex 2) series, so the > > > > > > output data should have changed on the following clock cycle. In the > > > > > > post-PAR timing simulation, the output changed on the following clock > > > > > > cycle as expected. > > > > > > > > Thank you.- Hide quoted text - > > > > > > - Show quoted text - > > > > > If you generated the block RAM with coregen, there is an option to > > > > preload the RAM with a coe file. You can then simulate the block RAM > > > > both at the RTL and post P&R level, disable the writes in the code > > > > and > > > > see if you read the expected data designated by the coe file at the > > > > desired addresses. > > > > > There are some instances when the RTL does not match the post P&R > > > > simulation. i.e. (sensitivity list is incomplete in a combinatorial > > > > process, > > > > improper use of blocking assignments and variables) I don't use the > > > > later two items > > > > in synthesizable code, so I don't have much experience with them, but > > > > then > > > > again, I never get an RTL vs post P&R simulation mismatch because of > > > > them. > > > > > Hope this helps, > > > > NewmanArticle: 118157
Attenuation over 1 m = 40 inches is not your problem. Reflections from either end of this cable can be a very ugly problem, unless you have some kind of termination. As Symon suggested, the simplest termination is series termination (since you have a "single-source, single-destination" case. So: estimate the cable impedance (probably 100 Ohm) and put a series resistor right at the dricing output, so that the IC sees twice the characteristic impedance. This drives a half-amplitude signal along the cable, but at the far end there is total reflection (since there is no termination), which doubles the amplitude, This wave now travels back to the source, where it is swallowed by the perfect termination. Bingo, no more reflections. If you have a fast scope, you can see the half-amplitude signal driving the cable, and the additional half arriving back at the source after about 10 ns. Peter Alfke On Apr 18, 6:52 am, "X.Y." <Xieyu1...@gmail.com> wrote: > Seeking the solutions of high speed interconnection for the long > distance transmission of 3.3v/24MHz signals. > > We need to connect a CMOS image sensor and a FPGA chip. The distance > between them is approximately 1 meter. The output signal of the sensor > is 3.3v and 24MHz. However, the length of the original cable of it is > only 1 centimeter, so it should be prolonged. If they are connected by > a cable directly, the signal would attenuate greatly which will cause > the system doesn't work. In my opinion, an interconnecting circuit > should be added between the sensor and the FPGA chip to process the > signal before and after the transmission. By now, the methods I have > found are as follows: > 1, Using LVDS signal Transceiver and Receiver > The drawback of the method is: there are more than 10 bits signals, > which need many of this kind of chips. It will take too much place in > PCB and it also cost much. > 2, Using chips of Serializer and Deserializer. > Both Maxim and National Semiconductor have such chips such as MAX9247 > and DS90C241. It is a good method. Unfortunately the solution is fired > by my tutor because these chips are expensive. > > My question is whether there are any other solutions? More cheap will > be better. Thanks a lot.Article: 118158
Actually i got the answer for that problem. There was one such error which was brought to this list some time back and solution was given. use OPTION STYLE = MIX in the .mpd file of the peripheral. with warm regards, chakra.Article: 118159
On 2007-04-18, Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> wrote: > It's not staring you in the face at all - it's a little tricky > to find - but check out the online help for the "virtual type" > and "virtual function" commands, and you'll get what you need. And somewhat cumbersome to use as well, I don't know why they haven't included anything more automatic. Anyway, this thread got me thinking that it shouldn't be that hard to write a TCL script that will automatically add a virtual function and type for you if you just select the state parameters and the state variables. I don't know why I haven't thought about doing it earlier... Anyway, I've just spent the evening writing such a script and it seems to be working quite ok. If anyone is interested they can find it at http://www.da.isy.liu.se/~ehliar/stuff/ (look for stateenumerate.tcl). /AndreasArticle: 118160
On 2007-04-18, Andreas Ehliar <ehliar@lysator.liu.se> wrote: > Another possibility that I've seen in some situations is to > set a signal to a certain string in the state machine as in: > > always @(posedge clk) > if(rst) begin > state_r <= IDLE; > state_str <= "STATE1"; This should of course be "IDLE" and nothing else.Article: 118161
> Thank you Peter for the clarification. I do understand that now. I > realized that for a read, I was outputting the clock and address at > the same time as if it was combinational. My problem now is to figure > out a way to fit an extra cycle in my state machine to issue the clock > one cycle after the address is output. Is the state machine actually issuing the clock to the BRAM? If so, it sounds like it is a gated clock which is to be avoided. NewmanArticle: 118162
Hi everybody, Currently I use www.eurocircuits.com for my standard PCB prototypes. They are cheap and rather good but they have probably too much work these days and I had unexpected delays on several boards. So I'm looking for competitive alternatives. Any PCB shops recommendations for 6 layers boards prototypes in a few days? Any feedback on Sunstone for instance? (The full featured service as their quick turn service has "no electrical test" which seems rather scary for 6 layers with BGAs) Thanks MarcArticle: 118163
On Apr 18, 12:31 pm, Newman <newman5...@yahoo.com> wrote: > Is the state machine actually issuing the clock to the BRAM? If so, it > sounds like it is a gated clock which is to be avoided. > The state machine output changes on a clock edge ( I know some can argue this is bad style). It goes like this: IF RISING_EDGE(clk) THEN CASE state IS <snip> WHEN READ_BKRAM => bram_read <= '1'; state <= WAIT_FOR_DATA; <snip> END CASE; END IF; The BKRAM clock is bram_read, and that should sythesize to the output of a FF. /MHSArticle: 118164
On Apr 18, 4:05 pm, "M. Hamed" <mhs...@gmail.com> wrote: > On Apr 18, 12:31 pm, Newman <newman5...@yahoo.com> wrote: > > > Is the state machine actually issuing the clock to the BRAM? If so, it > > sounds like it is a gated clock which is to be avoided. > > The state machine output changes on a clock edge ( I know some can > argue this is bad style). It goes like this: > > IF RISING_EDGE(clk) THEN > CASE state IS > <snip> > > WHEN READ_BKRAM => > bram_read <= '1'; > state <= WAIT_FOR_DATA; > > <snip> > END CASE; > END IF; > > The BKRAM clock is bram_read, and that should sythesize to the output > of a FF. > > /MHS I assume that clk is the global clock. If you connect bram_read to the BLK RAM clk input, you have created another clock domain and created clock skew issues. It is better to attach the global clock to the BLK RAM clk input and use the enable signals to control the data flow and or pick off valid data via the state machine. Creating another clock domain is generally to be avoided if possible. I hope I have understood the situation and this helps. I suspect it will. NewmanArticle: 118165
Eli Hughes wrote: > Here is working (Actually Implement in Silicon) code: Any comments on relative Simulate and P&R times, for others that may follow ? -jgArticle: 118166
And here is one, more in the original flavor,
that uses inferred shift registers and a little hierarchy
to split things up for physical synthesis.
alan
module shift(Clk, SIn, SOut);
input Clk;
input SIn;
output SOut;
parameter width = 1024 ;
reg [width-1:0] MyShift;
assign SOut = MyShift[width-1];
always @(posedge Clk)
begin
MyShift <= {MyShift[width-2:0],SIn};
end
endmodule // shift
module Bigshift(Clk, SIn, SOut);
input Clk;
input SIn;
output SOut;
parameter width = 80 ;
wire [width-1:0] MyShift;
reg Out;
assign MyShift[0] = SIn ;
assign SOut = MyShift[width-1];
genvar i;
generate
for (i=0; i < width-1 ; i=i+1)
begin: shift_inst
shift #(1024) subshft
(.Clk(Clk), .SIn(MyShift[i]), .SOut(MyShift[i+1]));
end
endgenerate
endmodule // Bigshift
Article: 118167Hello, Where can I find the VHDL ( or verilog) source code for polyphase filter? Is there any free implementation around? RegardsArticle: 118168
Ive got a problem like mentioned, During "map" signals that are used in the design are being trimmed and than I get errors that these signals are missing. Anybody knows how to prevent ISE from trimming my signals? (using the option in map properties doesn't change anything) My ISE version is 9.1 webpack. Looking forward for some help.Article: 118169
On Apr 18, 1:29 pm, Newman <newman5...@yahoo.com> wrote: > I assume that clk is the global clock. If you connect bram_read to > the BLK RAM clk input, you have created another clock domain and > created clock skew issues. It is better to attach the global clock to > the BLK RAM clk input and use the enable signals to control the data > flow and or pick off valid data via the state machine. Creating > another clock domain is generally to be avoided if possible. > > I hope I have understood the situation and this helps. I suspect it > will. > > Newman The clock is the global clock (for this module) but I think the method you suggested is a cleaner way to do it. I am kind of reluctant to change the design now at this stage but I'll try to follow this in the future. Thank you. /MHSArticle: 118170
You don't seem to understand the processing from RTL to gates. When you do the answer will become self-evident. <elshoukry@gmail.com> wrote in message news:1176412116.388134.129630@d57g2000hsg.googlegroups.com... > Tracing timing violations in the post-p&r generated netlist can be > cumbersome with all signal merging/renaming and inserted buffer. I was > wondering if there is a way that I can back annotate the post place > and route delays back to the RTL code? even approximate delays can > reveal some design errors I would think. > > Thank you. >Article: 118171
On Apr 18, 9:40 pm, Andy Peters <goo...@latke.net> wrote: > On Apr 18, 4:24 am, nezhate <mazouz.nezh...@gmail.com> wrote: > > > Hi all, > > I'm using Ise 9.1.03i. when I try to print a code written in Ise text > > editor, I get this error: > > "Print fails because the default printer has not been selected", and > > when the design summary is opened I can see the window "steup printer" > > and my default printer is automatically selected. > > How to configure printer for ise text editor? > > thanks. > > Wow...somebody actually uses the ISE text editor? > > I thought everyone just used emacs. > > -a not everyone works under Linux. At home I have Linux and use emacs but in univ. they have windows and use Ise text editor .... what to do?Article: 118172
Thanks for your reply. Thank you! To Symon and Peter Alfke, using ribbon cable is really a good ideal. It's simple and cheap. However, our CMOS image sensor (OV9655) is from OmniVision and is originally used on a mobile phone. It is very small not only on volume but also on power (90mW). Are you sure the attenuation is not a problem? And besides, I knew a little about the method of source terminators from the book "High Speed Digital Design" of Johnson & Graham. However, I do not understand the means of "Make every other conductor ground" and "in the gnd-sig-gnd mode" as Symon suggested. Sorry for my ignorance, could you tell me more about it? To Tim and dalai lamah, thank you and I will try these chips later.Article: 118173
Ribbon cable: Ideally you would like to use a coaxial cable for each signal, so that there would be a controlled and defined impedance,and no crosstalk between the signals. A ribbon cable is an approximation of that, if you use the even- numbered wires for the various signals, and all the odd-numbered wires together as common ground. The shielding is not perfect, but usually acceptable, and you keep the characteristic impedance fairly high (I assumed 100 Ohm, but it might be 70 Ohm). The asumption is that the output driver has a lower impedance than that. CMOS outputs ar often as low as 10 Ohm. You can measure the output impedance by loading the output with various resistors to ground (try 100, 47, and 22 Ohms or something like it). Never thinkof the cable as a lumped capacitance. It is a transmission line with distributed C and L plus some series resistance causing losses , but I don't believe the losses will bother you much. 1 m should be easy. If you had said 10 or 50 m, it would be another matter... Peter Alfke ========================= On Apr 18, 9:28 pm, "X.Y." <Xieyu1...@gmail.com> wrote: > Thanks for your reply. Thank you! > To Symon and Peter Alfke, using ribbon cable is really a good ideal. > It's simple and cheap. However, our CMOS image sensor (OV9655) is from > OmniVision and is originally used on a mobile phone. It is very small > not only on volume but also on power (90mW). Are you sure the > attenuation is not a problem? And besides, I knew a little about the > method of source terminators from the book "High Speed Digital Design" > of Johnson & Graham. However, I do not understand the means of "Make > every other conductor ground" and "in the gnd-sig-gnd mode" as Symon > suggested. Sorry for my ignorance, could you tell me more about it? > > To Tim and dalai lamah, thank you and I will try these chips later.Article: 118174
On Apr 19, 8:11 am, nezhate <mazouz.nezh...@gmail.com> wrote: > On Apr 18, 9:40 pm, Andy Peters <goo...@latke.net> wrote: > > > > > > > On Apr 18, 4:24 am, nezhate <mazouz.nezh...@gmail.com> wrote: > > > > Hi all, > > > I'm using Ise 9.1.03i. when I try to print a code written in Ise text > > > editor, I get this error: > > > "Print fails because the default printer has not been selected", and > > > when the design summary is opened I can see the window "steup printer" > > > and my default printer is automatically selected. > > > How to configure printer for ise text editor? > > > thanks. > > > Wow...somebody actually uses the ISE text editor? > > > I thought everyone just used emacs. > > > -a > > not everyone works under Linux. > At home I have Linux and use emacs but in univ. they have windows and > use Ise text editor .... what to do? I get the solution: before opening Ise, For Linux in command line, tape: $ sys-config-printer (to know the name of default printer) $ export PRINTER=name_of_default_printer After open Ise and print ! From invalid@dont.spam Wed Apr 18 23:08:49 2007 Path: newsdbm05.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!cyclone1.gnilink.net!spamkiller2.gnilink.net!gnilink.net!trndny01.POSTED!933f7776!not-for-mail From: Phil Hays <invalid@dont.spam> Subject: Re: Printing problem with Ise 9.1.03i User-Agent: Pan/0.14.2.91 (As She Crawled Across the Table) Message-Id: <pan.2007.04.19.06.08.49.767211@dont.spam> Newsgroups: comp.arch.fpga References: <1176895441.792404.142170@e65g2000hsc.googlegroups.com> <1176918032.296407.242830@e65g2000hsc.googlegroups.com> <1176955910.522711.300730@b75g2000hsg.googlegroups.com> <1176962241.981948.308210@l77g2000hsb.googlegroups.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 11 Date: Thu, 19 Apr 2007 06:08:49 GMT NNTP-Posting-Host: 71.112.129.56 X-Complaints-To: abuse@verizon.net X-Trace: trndny01 1176962929 71.112.129.56 (Thu, 19 Apr 2007 02:08:49 EDT) NNTP-Posting-Date: Thu, 19 Apr 2007 02:08:49 EDT Xref: prodigy.net comp.arch.fpga:129814 nezhate wrote: >> At home I have Linux and use emacs but in univ. they have windows and >> use Ise text editor .... what to do? Perhaps put emacs for windows and your .emacs on a USB key. Or a CD. -- Phil Hays
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