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Aaron Curtin schrieb: > Hi, I have a Microblaze based project that communicates to a 16Bit DAC > by means of an SPI interface. I'm using the OPB_SPI interface with a > OPB to SPI clock ratio of 16 (the minimum for this property) which > works out to be a clock of 3.125 Mhz for a 50Mhz OPB bus. This seems > extremely slow considering that the DAC unit can work up to an SPI > clock frequency of 30Mhz. Does anyone know why the minimum value for > the OPB to SPI clock ratio has to 16 or am I just not configuring it > properly. min ratio is 2 not 16 AnttiArticle: 110976
Hi, I generated my MPMC2 Core with the GUI 1.6. I took a preconfigured core "ml403_ddr_p_100mhz" and changed the memory style, type, part width etc. so that it fits to my board memory (Infineon HYB25D512160BC) and modified the Number of Data Pins in the Memory Settings to 16. After that I generated the Core. The Arbiter Algorithm didn=B4t need to be changed. In XPS I ran the BSB Wizard to build a project with OPB_DDR Controller and some peripheral parts, checked it with the simple TestMemory_App, everything ok. Rescan User Repositories. Then I added the MPMC2 and dcm_por_reset IPs and connected the Ports etc as described in MPMC2 release notes by editing the mhs file. I also removed the opb_ddr instance. After that I build the project, downloaded bitstream and checked per xmd the memory state, there I have this problem mentioned above. Any other suggestions? Thanks, MackArticle: 110977
Aaron Curtin wrote: > Does anyone know why the minimum value for > the OPB to SPI clock ratio has to 16 or am I just not configuring it > properly. The minimum ratio value is 2, at least from OPB SPI version 1.00.b onward (I don't have a datasheet for version 1.00.a). >From the Data Sheet: OPB to SPI SCK frequencies ratio C_OPB_SCK_RATIO 2, 4, 16, 32, NX16 for N=1,2,3,...,128 default: 2 type: integerArticle: 110978
Antti wrote:
> leevv schrieb:
>
> > May be it's not pretty, but i'm using this for quite a while.
> > I'm creating wrapper for the fifo and this component.
> >
> {code snipped}
>
> looks like exactly what I needed, tried last night the same but failed
> with first attempt
>
> sposiba ogromnoje!
>
> Antti
> PS I wonder how many xilinx users have made or have needed this
> auto_read_first
> FIFO fix? really simple thing, but not available with coregen
Pojalujsta. ;-)
Why only xilinx. I'm just currious is it standard feature somewhere
else (A or L)?
Article: 110979Your name wrote: > Hi there, > > I've recently installed the Xilinx ISE toolset so that I can play with the > Memory Interface Generator. I followed the readme and installed ISE 8.1i, > 8.1i_SP3 and then MIG 1.6. When I open CORE Generator and select MIG from > the drop down list nothing happens. I get the "Customise" and "View Data > Sheet" links but when I click on them nothing happens. > > Is there another download that I've missed or is the Xilinx software just > flaky? > What family are you targeting? I think there is a mistake in mig_v1_6.xml file. If you view it, you can find a following line: <family>virtex5</family> In version 1.5 it is: <family>spartan3 spartan3e virtex4</family> Some time ago I tried to add other families to a 1.6 version .xml file and it worked fine for Spartan3. -- Regards RobertP.Article: 110980
Hi Richard, how are you implementing the multiplies in your design? Are you just expressing them as standard HDL and then seeing them inferred as hard multiplier blocks in the logical synthesis stage? Or are you either: a) Explicitly instantiating embedded multipliers in your HDL code? b) Using some kind of pre-synthesised logical netlist that instantiates embedded multipliers as part of your design? Robin rnbrady wrote: > Hi > > I'm compiling my design using Quartus II and using a Cylclone II EP2C35 > device. The fitter reports currently says it's using 34 /70 embedded > 9-bit multiplier blocks. I'd like to see how much extra logic it uses > if I tell it not to use the embedded multipliers, but I can't seem to > turn them off. > > Under the synthesis settings I can set "maximum DSP block usage" from > -1 to 0 but this has no effect. Any tips? > > Thanks, > RichardArticle: 110981
The dedicated FIFO controller in Virtex-5 BRAMs has
First-word-fall-through as an option, and also "synchronous" (=common
read-write clock) as an option, where it avoids the re-synchronation
delay ambiguity.
Peter Alfke, Xilinx Applications
On Oct 26, 7:34 am, "leevv" <l...@mail.ru> wrote:
> Antti wrote:
> > leevv schrieb:
>
> > > May be it's not pretty, but i'm using this for quite a while.
> > > I'm creating wrapper for the fifo and this component.
>
> > {code snipped}
>
> > looks like exactly what I needed, tried last night the same but failed
> > with first attempt
>
> > sposiba ogromnoje!
>
> > Antti
> > PS I wonder how many xilinx users have made or have needed this
> > auto_read_first
> > FIFO fix? really simple thing, but not available with coregenPojalujsta. ;-)
>
> Why only xilinx. I'm just currious is it standard feature somewhere
> else (A or L)?
Article: 110982I'm also interested in hardware stream ciphers, and have been looking at papers related to: http://en.wikipedia.org/wiki/ESTREAM Good luck! alanArticle: 110983
Peter Alfke schrieb: > The dedicated FIFO controller in Virtex-5 BRAMs has > First-word-fall-through as an option, and also "synchronous" (=common > read-write clock) as an option, where it avoids the re-synchronation > delay ambiguity. > Peter Alfke, Xilinx Applications > Peter I feel really stupid - I had to target S3e, but I dont have any nice s3e boards around so I tested on the board that is closest to the keyboard, what happens to be ML501. So somehow looking at the x markings I got the impression that "first word fall through" is not supported by coregen for S3e at all. As Pixel Velocity just told me in email this isnt true. I was too tired eyes hurting too much, didnt see or understand the x's in the coregen screen. So I have implemented Leew's solution that works just perfectly. After that I have also validated the coregen's solution, that also works, but has a hidden 'issue' namly with coregen FIFO 'empty' flag de-asserts not when WR asserts but when it deasserts! so if 1000 words are written to FIFO then empty goes away then when the WR ends eg at time when there are 1000 words already in fifo. Leews solution doesnt have that issue. Ok for my current application both alternatives would work ok, but I already had the Leew's fixup in place AnttiArticle: 110984
I have been using version 1.00.e of the opb_spi interface. I tried
changing the value in the opb_spi property window and it always resets
to 16 if the value entered is below. I then tried changing the value
in the MHS file and I end up getting the following error when I try
building the hardware design:
ERROR:MDT - SPI_DAC (opb_spi) - Invalid parameter:
C_OPB_SCK_RATIO must be 16N where N = 1, 2, 3,...,128
while executing
"error "Invalid parameter:\nC_OPB_SCK_RATIO must be 16N where N = 1,
2,
3,...,128" "" "mdt_err""
(procedure "check_sck_ratio" line 10)
invoked from within
"check_sck_ratio $mhsinst"
(procedure "::hw_opb_spi_v1_00_e::check_iplevel_settings" line
4)
invoked from within
"::hw_opb_spi_v1_00_e::check_iplevel_settings 34196856"
Running UPDATE Tcl procedures for OPTION
PLATGEN_SYSLEVEL_UPDATE_PROC...
ERROR:MDT - platgen failed with errors!
Article: 110985
Aaron, I think it's bug in the GUI, just edit the mhs by hand.
Aurash
Aaron Curtin wrote:
>I have been using version 1.00.e of the opb_spi interface. I tried
>changing the value in the opb_spi property window and it always resets
>to 16 if the value entered is below. I then tried changing the value
>in the MHS file and I end up getting the following error when I try
>building the hardware design:
>
>ERROR:MDT - SPI_DAC (opb_spi) - Invalid parameter:
> C_OPB_SCK_RATIO must be 16N where N = 1, 2, 3,...,128
> while executing
> "error "Invalid parameter:\nC_OPB_SCK_RATIO must be 16N where N = 1,
>2,
> 3,...,128" "" "mdt_err""
> (procedure "check_sck_ratio" line 10)
> invoked from within
> "check_sck_ratio $mhsinst"
> (procedure "::hw_opb_spi_v1_00_e::check_iplevel_settings" line
>4)
> invoked from within
> "::hw_opb_spi_v1_00_e::check_iplevel_settings 34196856"
>
>Running UPDATE Tcl procedures for OPTION
>PLATGEN_SYSLEVEL_UPDATE_PROC...
>ERROR:MDT - platgen failed with errors!
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 110986
Thomas,
Many thanks for your input! Yes you are right, compout is driven
outside the FPGA and is not synchronous. I have tried out your
suggestion (see below), and it does definitely improve things (removes
most of the jumps :-), but I still have something going wrong as there
are still some occasional jumps in the data. I have staggered the
integrator sum to a falling edge of the clock. (see below). Is this
what you meant by 2-stage shift register? Is there anything else I can
try?
sigdelfeedback: process (Clk8MHz) is
begin
if rising_edge(Clk8MHz) then
feedbackbit<=compout;
end if;
end process sigdelfeedback;
integrator: process (Clk8MHz) is
begin
if falling_edge(Clk8MHz) then
if feedbackbit ='1' then
combacc1<=combacc1 + 1;
else
combacc1<=combacc1 - 1;
end if;
end if;
end process integrator;
Thanks again,
Helen
Article: 110987
Zara wrote:
> On Mon, 23 Oct 2006 06:53:24 -0700, gerd <gerd.van.den.branden@ehb.be>
> wrote:
>
> >Hi,
> >
> >I want to use the FSL bus to connect two microblazes together. Because I am not familiar with the FSL bus, I first added a peripheral core using the configure coprocessor wizzard, to instantiate a default paripheral, together with the FSL drivers. However, when I run the SW application it stalls when writing to the FSL bus. I don't get any response afterwards.
> >
> >First, I did not made any changes to the instantiation of the fsl bus. Later on, I changed the clock connections (later on, also in the fsl's mpd file). Unfortunately, none o these measurements made any difference.
> >
> >Is there anyone that can provide me an example design that successfully uses the FSL bus, together with the application software (or a stripped version)? I can not find any satisfying reference designs on the web, nor on the Xilinx site.
> >
> >All help would be welcome!!
> >
> >Thanks,
> >
> >Gerd
>
>
> You must instantiate two fsl bus, to connect two uBlaze, one for each
> sense of communication. In each instance, you should connect
> FSL_Clk,Sys_Rst, FSL_M_CLK and FSL_S_Clk (all three clocks together).
> Bot uBlazes should work at same clock frequency
>
> You should also use the non-blocking versions of read/write functions
> (nput, ncput, nget y ncget).
>
> ANd thta is all there is to it!
>
> Zara
I'll try to explain me...in English o.O :-/ FSL bus works in one
direction: if you connect the peripheral or ublaze to FSL master, you
can write. If you connect the peripheral or ublaze to FSL slave you can
read, then if you want to write and read with the same ublaze or
peripheral, you need 2 FSLs.
I had problems with my FSLperipheral<->ublaze and with
ublaze<->ublaze connection by FSL. The reason was the signal "External
Reset Active High", by defect, it was 1.
If you add the 2nd ublaze, also you must add the bram block, lmb
bus...and you must verify that the bus interface is correct, that all
the necessary ports are connected (for example, when I added the 2nd
ublaze, EDK 8.1 don't add "sys_clk" to my ublaze and I had to put it in
"system.mhs") and that bram block, lmb have addresses.
You don't need to connect the three clocks, if you have synchronous
transmission, only the FSL_Clk is necessary.
To write with ublaze you should use the function: "putfsl(data, 0)"
('0' is the fsl id) and to read: "getfsl(data,0)". In the case of FSL
peripheral, you should use the signals FSL_S_EXISTS, FSL_S_DATA,
FSL_M_WRITE....see the FSL_v20.pdf.
arggghh...3 hours for to write this...:-(
Article: 110988Can anyone tell me what I need to drive a Camera Link output directly from a V4? I have tried LVCMOS25 and I can see differential signals at the outputs but at the end of a 2 meter cable I see only DC differential levels as if the signals are dampened somehow. Brad Smallridge aivisionArticle: 110989
Entire thread:
http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/8a8af923fa745e92/6f5f8b0c63a6bf79?hl=en#6f5f8b0c63a6bf79
The solution is in Answer Record # 11635
See
http://www.support.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=11635
Solution 1:
You can work around this issue in two ways:
1. Change the bus-ordering from (x to y) to (y downto x).
2. Create a separate testbench for functional and timing simulation.
This issue will be fixed in 6.1i.
Like fun it's fixed. If it was, it has since been un-fixed. I am using
Xilinx ISE ver 8.2.03i and ModelSim III XE 6.1e starter edition.
I chose approach 1., declaring the slv_regs as "downto" and rewrote the
Xilinx code for writing to the slv_regs as (eg):
slv_reg11((C_DWIDTH-1)-(byte_index*8) downto
(C_DWIDTH-1)-(byte_index*8+7)) <= Bus2IP_Data(byte_index*8 to
byte_index*8+7)
Simulation succeeds now and is readable, which is an important feature
in simulation, and this should work in the board.
One of the things I tried to fix this was reinstalling ISE and
ModelSim. Then I had the "brilliant" idea that since I was only using
Virtex 4, I would only install the files for that device. Then ISE
would always crash when I would try to open a new project,
notwithstanding trying what Answer Record 23387 said ("Fixed in SP1".
Like fun.). According to a Xilinx CAE, it now crashes because not all
device support was installed. I will try reinstalling with everything.
-James
Jhlw wrote:
> Hi All,
>
> Does anyone have any experience with getting their bit order reversed
> in Xilinx post-translate simulation? I am using Xilinx ISE ver 8.2.03i
> and ModelSim III XE 6.1e starter edition, and this mysteriously started
> happening to me last week when I never had a problem with this before.
> I have reinstalled both programs and have reverted to testing only what
> Xilinx gives me, and I still get the problem. I generated
> user_logic.vhd by following the directions in the
> EDK_82_PPC_Tutorial.pdf for the ML403 board; see
> http://www.xilinx.com/support/techsup/tutorials/edk_tutorials.htm --
> "EDK PowerPC Tutorial using the ML403 Development Kit 8.2"
> (EDK_82_PPC_Tutorial.pdf). Then I took it and put it in a separate new
> ISE project in order to simulate it. I didn't change any synthesize or
> translate options. I made sure that my testbench has sufficient input
> setup time and output valid delay according to the timing report (9 ns
> each, using a clock period of 20 ns). I have reduced the problem to
> just trying to write slv_reg0 and not see the contents backwards
> post-translate. I set Bus2IP_BE to F to select all registers,
> Bus2IP_Data to my test data of 0x01020304 and Bus2IP_WrCE to 8 in order
> to write slv_reg0. This succeeds in behavioral simulation, but in
> post-translate simulation, what I see for slv_reg0 is 0x20C04080, which
> is just the bits reversed low-order to high-order. I opened a webcase
> with Xilinx, but I don't know if they'll be able to reproduce the
> problem.
>
> With fresh installs of ISE and ModelSim, no changes to Synthesize or
> Translate options, no touching of any ModelSim menu options, and VHDL
> straight out of Xilinx's own user_logic from the Create Peripheral
> Wizard that always worked before (and works in Behavioral sim), what is
> left? What could I have set generally on my computer that could be
> causing this? Could there be some Translate option that I idiotically
> set and didn't remember that I set?
>
> It must be a problem with how ISE creates models for simulation, or in
> the simulator, since I can put my built project in the ML403 board and
> write and read the slv_regs correctly following the tutorial, over
> RS232. However, my core doesn't seem to be giving the correct output,
> so I need to simulate, and therefore I need a reliable simulation
> process.
>
> Thanks in advance,
> -James
>
> Here's user_logic.vhd as I am simulating it (straight from the Create
> Peripheral Wizard, with only the two "library proc_common_v2_00_a"
> lines commented-out so that the syntax check will succeed -- this
> always worked before):
> ------------------------------------------------------------------------------
> -- user_logic.vhd - entity/architecture pair
> ------------------------------------------------------------------------------
>
> ------------------------------------------------------------------------------
> -- Filename: user_logic.vhd
> -- Version: 1.00.a
> -- Description: User logic.
> -- Date: Tue Oct 03 15:53:39 2006 (by Create and Import
> Peripheral Wizard)
> -- VHDL Standard: VHDL'93
> ------------------------------------------------------------------------------
> -- Naming Conventions:
> -- active low signals: "*_n"
> -- clock signals: "clk", "clk_div#", "clk_#x"
> -- reset signals: "rst", "rst_n"
> -- generics: "C_*"
> -- user defined types: "*_TYPE"
> -- state machine next state: "*_ns"
> -- state machine current state: "*_cs"
> -- combinatorial signals: "*_com"
> -- pipelined or register delay signals: "*_d#"
> -- counter signals: "*cnt*"
> -- clock enable signals: "*_ce"
> -- internal version of output port: "*_i"
> -- device pins: "*_pin"
> -- ports: "- Names begin with
> Uppercase"
> -- processes: "*_PROCESS"
> -- component instantiations: "<ENTITY_>I_<#|FUNC>"
> ------------------------------------------------------------------------------
>
> -- DO NOT EDIT BELOW THIS LINE --------------------
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_arith.all;
> use ieee.std_logic_unsigned.all;
>
> --library proc_common_v2_00_a;
> --use proc_common_v2_00_a.proc_common_pkg.all;
> -- DO NOT EDIT ABOVE THIS LINE --------------------
>
> --USER libraries added here
>
> ------------------------------------------------------------------------------
> -- Entity section
> ------------------------------------------------------------------------------
> -- Definition of Generics:
> -- C_DWIDTH -- User logic data bus width
> -- C_NUM_CE -- User logic chip enable bus width
> --
> -- Definition of Ports:
> -- Bus2IP_Clk -- Bus to IP clock
> -- Bus2IP_Reset -- Bus to IP reset
> -- Bus2IP_Data -- Bus to IP data bus for user logic
> -- Bus2IP_BE -- Bus to IP byte enables for user
> logic
> -- Bus2IP_RdCE -- Bus to IP read chip enable for
> user logic
> -- Bus2IP_WrCE -- Bus to IP write chip enable for
> user logic
> -- IP2Bus_Data -- IP to Bus data bus for user logic
> -- IP2Bus_Ack -- IP to Bus acknowledgement
> -- IP2Bus_Retry -- IP to Bus retry response
> -- IP2Bus_Error -- IP to Bus error response
> -- IP2Bus_ToutSup -- IP to Bus timeout suppress
> ------------------------------------------------------------------------------
>
> entity user_logic is
> generic
> (
> -- ADD USER GENERICS BELOW THIS LINE ---------------
> --USER generics added here
> -- ADD USER GENERICS ABOVE THIS LINE ---------------
>
> -- DO NOT EDIT BELOW THIS LINE ---------------------
> -- Bus protocol parameters, do not add to or delete
> C_DWIDTH : integer := 32;
> C_NUM_CE : integer := 4
> -- DO NOT EDIT ABOVE THIS LINE ---------------------
> );
> port
> (
> -- ADD USER PORTS BELOW THIS LINE ------------------
> --USER ports added here
> -- ADD USER PORTS ABOVE THIS LINE ------------------
>
> -- DO NOT EDIT BELOW THIS LINE ---------------------
> -- Bus protocol ports, do not add to or delete
> Bus2IP_Clk : in std_logic;
> Bus2IP_Reset : in std_logic;
> Bus2IP_Data : in std_logic_vector(0 to
> C_DWIDTH-1);
> Bus2IP_BE : in std_logic_vector(0 to
> C_DWIDTH/8-1);
> Bus2IP_RdCE : in std_logic_vector(0 to
> C_NUM_CE-1);
> Bus2IP_WrCE : in std_logic_vector(0 to
> C_NUM_CE-1);
> IP2Bus_Data : out std_logic_vector(0 to
> C_DWIDTH-1);
> IP2Bus_Ack : out std_logic;
> IP2Bus_Retry : out std_logic;
> IP2Bus_Error : out std_logic;
> IP2Bus_ToutSup : out std_logic
> -- DO NOT EDIT ABOVE THIS LINE ---------------------
> );
> end entity user_logic;
>
> ------------------------------------------------------------------------------
> -- Architecture section
> ------------------------------------------------------------------------------
>
> architecture IMP of user_logic is
>
> --USER signal declarations added here, as needed for user logic
>
> ------------------------------------------
> -- Signals for user logic slave model s/w accessible register example
> ------------------------------------------
> signal slv_reg0 : std_logic_vector(0 to
> C_DWIDTH-1);
> signal slv_reg1 : std_logic_vector(0 to
> C_DWIDTH-1);
> signal slv_reg2 : std_logic_vector(0 to
> C_DWIDTH-1);
> signal slv_reg3 : std_logic_vector(0 to
> C_DWIDTH-1);
> signal slv_reg_write_select : std_logic_vector(0 to 3);
> signal slv_reg_read_select : std_logic_vector(0 to 3);
> signal slv_ip2bus_data : std_logic_vector(0 to
> C_DWIDTH-1);
> signal slv_read_ack : std_logic;
> signal slv_write_ack : std_logic;
>
> begin
>
> --USER logic implementation added here
>
> ------------------------------------------
> -- Example code to read/write user logic slave model s/w accessible
> registers
> --
> -- Note:
> -- The example code presented here is to show you one way of
> reading/writing
> -- software accessible registers implemented in the user logic slave
> model.
> -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to
> correspond
> -- to one software accessible register by the top level template. For
> example,
> -- if you have four 32 bit software accessible registers in the user
> logic, you
> -- are basically operating on the following memory mapped registers:
> --
> -- Bus2IP_WrCE or Memory Mapped
> -- Bus2IP_RdCE Register
> -- "1000" C_BASEADDR + 0x0
> -- "0100" C_BASEADDR + 0x4
> -- "0010" C_BASEADDR + 0x8
> -- "0001" C_BASEADDR + 0xC
> --
> ------------------------------------------
> slv_reg_write_select <= Bus2IP_WrCE(0 to 3);
> slv_reg_read_select <= Bus2IP_RdCE(0 to 3);
> slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or
> Bus2IP_WrCE(2) or Bus2IP_WrCE(3);
> slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or
> Bus2IP_RdCE(2) or Bus2IP_RdCE(3);
>
> -- implement slave model register(s)
> SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
> begin
>
> if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
> if Bus2IP_Reset = '1' then
> slv_reg0 <= (others => '0');
> slv_reg1 <= (others => '0');
> slv_reg2 <= (others => '0');
> slv_reg3 <= (others => '0');
> else
> case slv_reg_write_select is
> when "1000" =>
> for byte_index in 0 to (C_DWIDTH/8)-1 loop
> if ( Bus2IP_BE(byte_index) = '1' ) then
> slv_reg0(byte_index*8 to byte_index*8+7) <=
> Bus2IP_Data(byte_index*8 to byte_index*8+7);
> end if;
> end loop;
> when "0100" =>
> for byte_index in 0 to (C_DWIDTH/8)-1 loop
> if ( Bus2IP_BE(byte_index) = '1' ) then
> slv_reg1(byte_index*8 to byte_index*8+7) <=
> Bus2IP_Data(byte_index*8 to byte_index*8+7);
> end if;
> end loop;
> when "0010" =>
> for byte_index in 0 to (C_DWIDTH/8)-1 loop
> if ( Bus2IP_BE(byte_index) = '1' ) then
> slv_reg2(byte_index*8 to byte_index*8+7) <=
> Bus2IP_Data(byte_index*8 to byte_index*8+7);
> end if;
> end loop;
> when "0001" =>
> for byte_index in 0 to (C_DWIDTH/8)-1 loop
> if ( Bus2IP_BE(byte_index) = '1' ) then
> slv_reg3(byte_index*8 to byte_index*8+7) <=
> Bus2IP_Data(byte_index*8 to byte_index*8+7);
> end if;
> end loop;
> when others => null;
> end case;
> end if;
> end if;
>
> end process SLAVE_REG_WRITE_PROC;
>
> -- implement slave model register read mux
> SLAVE_REG_READ_PROC : process( slv_reg_read_select, slv_reg0,
> slv_reg1, slv_reg2, slv_reg3 ) is
> begin
>
> case slv_reg_read_select is
> when "1000" => slv_ip2bus_data <= slv_reg0;
> when "0100" => slv_ip2bus_data <= slv_reg1;
> when "0010" => slv_ip2bus_data <= slv_reg2;
> when "0001" => slv_ip2bus_data <= slv_reg3;
> when others => slv_ip2bus_data <= (others => '0');
> end case;
>
> end process SLAVE_REG_READ_PROC;
>
> ------------------------------------------
> -- Example code to drive IP to Bus signals
> ------------------------------------------
> IP2Bus_Data <= slv_ip2bus_data;
>
> IP2Bus_Ack <= slv_write_ack or slv_read_ack;
> IP2Bus_Error <= '0';
> IP2Bus_Retry <= '0';
> IP2Bus_ToutSup <= '0';
>
> end IMP;
Article: 110990Thank you for the reply... I did change the mhs file by hand to a value of 8 for the C_OPB_SCK_RATIO parameter but that is resulting in my previously posted error message. Is it possible to use an earlier version of the interface? ThanksArticle: 110991
Weng Tianxiang wrote:
> What is the difference between my and his procedures?
> I compiled textio.vhd file and compiled all files by clicked icons in
> manu: 'compile' and 'compile all'.
> He compild textio.vhd using compile/compile-selected manus.
Sounds like your son got the compile order
right and "compile all" didn't.
Consider writing a .do file for this and
run it from the command line:
do compile.do
-- Mike Treseler
Article: 110992Here is a snippet of the final error after changing the mhs file and re-implementing the design. ERROR:MDT - C:\Spartan3E_Projects\PWM_IPIF\system.mhs line 179 - PARAMETER C_OPB_SCK_RATIO has value 2 which does not fall in the range (16:2048), specified in MPD What is the MPD?Article: 110993
I am getting from time to time garbage (all signals high) displayed in the Chipscope after successful triggering (which would not have happened if all the signals were indeed high). The debugger (gdb) seems to indicate that the transaction was in fact successful... So, I was wondering if anyone else has seen this problem and whether it has anything to do to the fact that I am using the same JTAG port for both? Thanks, /MikhailArticle: 110994
Mike Treseler wrote: > Weng Tianxiang wrote: > > > What is the difference between my and his procedures? > > I compiled textio.vhd file and compiled all files by clicked icons in > > manu: 'compile' and 'compile all'. > > He compild textio.vhd using compile/compile-selected manus. > > Sounds like your son got the compile order > right and "compile all" didn't. > Consider writing a .do file for this and > run it from the command line: > do compile.do > > -- Mike Treseler Hi Mike, It has nothing to do with compile order. My son is not an vhdl writer, but knows many thing unregular. He just happend to get the thing done right, many times I asked for his help and he got things done. I tried following several options without success: 1. Put textio.vhd in the project top position; 2. Compile all by clicking manu icon; 3. Compile by clicking manu icon with textio.vhd selected; My son put textio.vhd at the last position in project file list, select textio.vhd, then clicked manu compile/compile-selected and compiled textio.vhd only. After that he compiled all files and succeeded. If the compile position is concerned, his position is wrong, because textio.vhd would be called before all files, but he did it. Thank you. WengArticle: 110995
Aaron Curtin wrote: > Here is a snippet of the final error after changing the mhs file and > re-implementing the design. > > ERROR:MDT - C:\Spartan3E_Projects\PWM_IPIF\system.mhs line 179 - > PARAMETER C_OPB_SCK_RATIO has value 2 which does not fall in the range > (16:2048), specified in MPD > > What is the MPD? Interesting. In the 1.00.d core, the range in the MPD is 2 to 2048, in the 1.00.e core, its 16 to 2048. The MPD files are under the EDK tree, per core. Example for my installation: C:\EDK8.1\hw\XilinxProcessorIPLib\pcores\opb_spi_v1_00_d\data\opb_spi_v2_1_0.mpdArticle: 110996
> Interesting. > In the 1.00.d core, the range in the MPD is 2 to 2048, in the 1.00.e > core, its 16 to 2048. > > The MPD files are under the EDK tree, per core. > Example for my installation: > > C:\EDK8.1\hw\XilinxProcessorIPLib\pcores\opb_spi_v1_00_d\data\opb_spi_v2_1_0.mpd Try using 1.00.d instead In the 1.00.e data sheet, there is the following note on page 5: Notes: 1.Ratios of 2 and 4 are not supported in this release of the core. I quickly scanned the datasheet, but didn't see any explanation of why this restriction exists in this newest version of the core.Article: 110997
Weng Tianxiang wrote:
> My son is not an vhdl writer,
> but knows many thing unregular. He just happend to get the thing done
> right, many times I asked for his help and he got things done.
Yes, your sun was just lucky.
I don't use the Modelsim GUI for compilation because
it doesn't always get it right and I can never tell
exactly what it is doing.
My point was, that if you write a script, you are in control.
It is a good idea to clean out the work directory
each time as shown below because you can fool
yourself with leftovers otherwise. Good luck
-- Mike Treseler
_________________________________________________
# http://home.comcast.net/~mike_treseler/uart.do
set this uart
set mydesign $this
set mytb test_$this
echo Assuming [pwd] is the right directory.
vdel -all ;# clean last compilation
vlib work
vmap work work
vcom $mydesign.vhd $mytb.vhd
restart -f ;# so I can use this same script to rerun
radix hex; ;# Make bus values easy to read
add wave * ;# Signals
add wave /$mytb/main/* ;# Test variables
add wave /$mytb/dut/main/* ;# UUT variables
run -all;
# Make wave window readable
WaveRestoreCursors {{Cursor 1} {194 ns} 0}
configure wave -namecolwidth 277
WaveRestoreZoom {178 ns} {281 ns}
Article: 110998Chris wrote: > Nope won't work. I talked to Lattice today. There is no internal osc to > use, and they did not recommend using a bunch of gates. Moreover there is > no extra flash space either - zip. This is not the first time. Overall I > am very disappointed with what they put out in their MachXO and XP NV > families. They lack a lot of little features that would make them so much > more powerful. I guess they have heard that from others too, he told me > that they were coming out with a 'revised' new XP line next year. XP-II I > think he said. > > Chris. Hello Chris, I spoke with our Director of Applications, Bertrand Leigh on this topic and confirmed that the application will work. Antti is correct, you CAN build an internal ring oscillator based on stacked inverters for a coarse frequency oscillator inside the XP or EC/ECP type devices. This is a proven method that has worked at Lattice and at other users. XO and ECP2/M device families have built-in oscillator based on the configuration oscillator that is accessable from the FPGA fabric after configuration. For Flash write back both options are available -- PERSISTENT=ON for sysConfig port and through JTAG. We will follow up with the person you spoke to on our technical support line and let them know about this application. Sorry if they caused any confusion. Hope this helps. Bart Borosky, Lattice SemiconductorArticle: 110999
Antti schrieb: > Peter Alfke schrieb: > > > The dedicated FIFO controller in Virtex-5 BRAMs has > > First-word-fall-through as an option, and also "synchronous" (=common > > read-write clock) as an option, where it avoids the re-synchronation > > delay ambiguity. > > Peter Alfke, Xilinx Applications > > > > Peter > > I feel really stupid - I had to target S3e, but I dont have any nice [] actually i feel less stupid, I did checkout coregen FWFT fifo yesterday, but I used a testbench that writes a burst to the fifo, and I looked in the simulation where the burst starts, and the FIFO output did not change so I assumed the FIFO wasnt working - I did not notice that the coregen FIFO delay its output update and the EMPTY flag de-assertion until the burst ends. this can be at the same time when is completly full, seems like a little bizarre behaviour for an FIFO. for me it was so unexpected that I didnt investigate the coregen FWFT fifo any longer, and implemented the workaround Antti
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