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Glad I posted the question. You guys are great. So much info. I think the 8 bit micro is the right approach level: PicoBlaze, Micro8. There is another PacoBlaze that looks interesting. Probably others too. Waiting for info on ERIC5. The LatticeXP approach is attractive from a couple standpoints. Being NV and single supply, if I can use the config clock in user mode, and keep some of my own extra data in the internal flash, than it becomes possible to do the whole implementation with a single part. No regulators, no external flash, no xtal/osc. Great for PCB routing and space. Very slick and clean. One single part. Might be able to use a double sided board. Need to talk to Lattice about a couple points there. I think I can keep the config osc running by setting the PERSISTENT flag ON, but not sure about flash usage. Otherwise Xilinx 3E-100 is probably best choice. Thanks guys! Chris.Article: 110901
Chris schrieb: > Glad I posted the question. You guys are great. So much info. > > I think the 8 bit micro is the right approach level: PicoBlaze, Micro8. > There is another PacoBlaze that looks interesting. Probably others too. > Waiting for info on ERIC5. > > The LatticeXP approach is attractive from a couple standpoints. Being NV > and single supply, if I can use the config clock in user mode, and keep some > of my own extra data in the internal flash, than it becomes possible to do > the whole implementation with a single part. No regulators, no external > flash, no xtal/osc. Great for PCB routing and space. Very slick and clean. > One single part. Might be able to use a double sided board. > > Need to talk to Lattice about a couple points there. I think I can keep the > config osc running by setting the PERSISTENT flag ON, but not sure about > flash usage. Otherwise Xilinx 3E-100 is probably best choice. > > Thanks guys! > > Chris. in XP the config oscillator is NOT accessible. but that is not a big deal at all, you can use in fabric oscillator as well, works great I have tested with lattice XP as well AnttiArticle: 110902
"Gary Spivey" <gspivey@georgefox.edu> wrote: >In the following module, >module mult (output reg[7:0] z, input [3:0] a); > always @* begin > z = a*a; > end >endmodule > >ModelSim returns 225 when a is 15, but the Xilinx implementation on a >Spartan3 returns a 1 (-1 * -1). Does anybody know why Xilinx ISE is >interpreting the four bit numbers as signed numbers rather than unsigned? > Search for the thread 'multiplier madness' from a couple of weeks ago. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 110903
Subhasri krishnan wrote: > Hi All, > I was working with a design which stored data in a single bank in a > memory and it worked just fine. Now I have moved my design to a chip > with a smaller capacity (64Mb) so I need use multiple banks. > > When I use banks 0 and 1 and try to display image from bank 0, the > image from bank 1 is displayed. But if I use banks 0 and 2 or 0 and 3, > and when i try to display from bank 0, the result is ok. Similarly if > I use 2 and 3 , it doesnt work. But if I use 2 and 0 or 2 and 1 then it > is ok. Has anyone had a similar problem before? Have you obtained a VHDL/Verilog model of the memory somewhere (even a similar memory, if you cannot find the exact one) and seen what happens in simulation?Article: 110904
> Waiting for info on ERIC5. Hi Chris, I have seen that you have requested the ERIC5-datasheets & eval-kit on our homepage, you should have received it automatically via e-mail. Maybe the supplied e-mail address was incorrect (althought it looks plausible), or the mail was blocked by a firewall / spam-filter? If it really did not arrive, you can send me an e-mail. ThomasArticle: 110905
Det var smuk og solrig dag da skrev news:1161699388.262970.67360@b28g2000cwb.googlegroups.com i comp.arch.fpga: > is that a known bug ? > > ISE 8.2 / win XP seems to freeze while synthesing design (no more mouse > or menu/button action event response... looks like a threading bug) > > at the end of computation, it comes back to normal execution. Same problem here, but only when doing mapping. I can see that it is progressing by looking at the scrollbar which becomes thinner and thinner. At the start of place and route all the text pops up, and ISE responds normally. Just another bug in ISE... -- Rune D. JørgensenArticle: 110906
> in XP the config oscillator is NOT accessible. According to their sysCONFIG pdf, the CCLK is brought out to a pin. If you set the PERSISTENT flag to ON, then the config is suppose to keep alive. Doesn't that mean that the CCLK will keep going? > but that is not a big deal at all, you can use in fabric oscillator I assume you mean the sysClock. I saw that PLL but assumed it needed an external input. What about using the internal flash for read/write during user mode. Any experience with XP parts on that? Thanks, Chris.Article: 110907
Chris schrieb: > > in XP the config oscillator is NOT accessible. > > According to their sysCONFIG pdf, the CCLK is brought out to a pin. If you > set the PERSISTENT flag to ON, then the config is suppose to keep alive. > Doesn't that mean that the CCLK will keep going? > > > but that is not a big deal at all, you can use in fabric oscillator > > I assume you mean the sysClock. I saw that PLL but assumed it needed an > external input. > > What about using the internal flash for read/write during user mode. Any > experience with XP parts on that? > > Thanks, Chris. no, I did mean the CCLK "inside" the FPGA, the config osc primitive is visible in devive viewer but the primitive cant be used in XP, it can used in ECP and some other lattice fpgas there is no user flash, but if you mean the flash config that is rewriteable but you need to wire loop jtag pins to user io AnttiArticle: 110908
Gabor wrote: > Subhasri krishnan wrote: > > Hi All, > > I was working with a design which stored data in a single bank in a > > memory and it worked just fine. Now I have moved my design to a chip > > with a smaller capacity (64Mb) so I need use multiple banks. > > > > When I use banks 0 and 1 and try to display image from bank 0, the > > image from bank 1 is displayed. But if I use banks 0 and 2 or 0 and 3, > > and when i try to display from bank 0, the result is ok. Similarly if > > I use 2 and 3 , it doesnt work. But if I use 2 and 0 or 2 and 1 then it > > is ok. Has anyone had a similar problem before? > > > > Thanks > > Subhasri > > It seems too obvious, but are you sure you're actually driving the > BA[0] address line? The symptoms look like the line isn't switching... I just checked my hardware and BA[0] isnt working. Thanks for that suggestion. I always end up thinking that there is something wrong with my description.Article: 110909
---------- Is an 8-bit soft-core CPU (e.g. picobalze(tm)), too big for your task? Is even a 4-bit CPU too much? Well at Fly-by-Night Enterprises, we have the perfect solution - the 2-bit FemtoFire CPU! If you've ever wanted a real 2-bit processor from a 2-bit company, now is the time to get one. And if you place your order in the next 2 minutes, you can get the FemtoFire for only 2-bits (0.25USD)! What a deal! If you need a high-end soft-core, we offer the MaxiFire 33-1/3 bit CPU. With some tweaking of the design, you can even create a 78-bit CPU. Accessing the MaxiFire's serial bus is via a magnetic transducer (found at any electronics surplus center). All of our soft-cores are offered in our poprietary FbNHDL, which in keeping with Fly-by-Night's philosophy, is not compatible with _any_ existing HDL. Both the source code and compiler are free, but there is a small download fee (*). Payment can be made with either PayMeBuddy or gold-pressed latinum. (* - 0.25USD per byte) ------------- This is what happens when I have a bad cold and cabin fever! I hope you enjoyed it. My apologies to PayPal(tm)! -Dave PollumArticle: 110910
Dave Pollum schrieb: > ---------- > Is an 8-bit soft-core CPU (e.g. picobalze(tm)), too big for your task? > Is even a 4-bit CPU too much? Well at Fly-by-Night Enterprises, we > have the perfect solution - the 2-bit FemtoFire CPU! If you've ever > wanted a real 2-bit processor from a 2-bit company, now is the time to > get one. And if you place your order in the next 2 minutes, you can > get the FemtoFire for only 2-bits (0.25USD)! What a deal! If you need > a high-end soft-core, we offer the MaxiFire 33-1/3 bit CPU. With some > tweaking of the design, you can even create a 78-bit CPU. Accessing > the MaxiFire's serial bus is via a magnetic transducer (found at any > electronics surplus center). All of our soft-cores are offered in our > poprietary FbNHDL, which in keeping with Fly-by-Night's philosophy, is > not compatible with _any_ existing HDL. Both the source code and > compiler are free, but there is a small download fee (*). Payment can > be made with either PayMeBuddy or gold-pressed latinum. > (* - 0.25USD per byte) > ------------- > This is what happens when I have a bad cold and cabin fever! > I hope you enjoyed it. My apologies to PayPal(tm)! > -Dave Pollum I had cold recently too. But I am serious about designing and soft-core that uses 0 slices, 0 luts and 0 FF's :) Antti PS I an I almost had some experiene with 2 bit processors, dont recall the part type any more but I had some of them in my hands. Well didnt ever make a PCB for them. Was some funky military 2 bit wide bit-slice thing.Article: 110911
> no, I did mean the CCLK "inside" the FPGA, the config osc primitive is > visible in devive viewer but the primitive cant be used in XP, it can > used in ECP > and some other lattice fpgas > > there is no user flash, but if you mean the flash config that is > rewriteable > but you need to wire loop jtag pins to user io Exactly. PERSISTENT=ON keeps the pins alive. If I wire those around to other IO pins, then I should be able to read/write to the Flash while running and use the CCLK to run the CPU. Chris.Article: 110912
Antti wrote: > > I had cold recently too. > But I am serious about designing and soft-core that uses 0 slices, 0 > luts and 0 FF's :) > And this design has no inputs, outputs, or clocks, either? -Dave > Antti > PS I an I almost had some experiene with 2 bit processors, > dont recall the part type any more but I had some of them > in my hands. Well didnt ever make a PCB for them. Was > some funky military 2 bit wide bit-slice thing.Article: 110913
Dave Pollum schrieb: > Antti wrote: > > > > I had cold recently too. > > But I am serious about designing and soft-core that uses 0 slices, 0 > > luts and 0 FF's :) > > > And this design has no inputs, outputs, or clocks, either? > -Dave Why? it is a clocked desing with lots of inputs and outputs, no problems with them at all. it is really doable and fun thing to design. AnttiArticle: 110914
Chris schrieb: > > no, I did mean the CCLK "inside" the FPGA, the config osc primitive is > > visible in devive viewer but the primitive cant be used in XP, it can > > used in ECP > > and some other lattice fpgas > > > > there is no user flash, but if you mean the flash config that is > > rewriteable > > but you need to wire loop jtag pins to user io > > Exactly. PERSISTENT=ON keeps the pins alive. If I wire those around to > other IO pins, then I should be able to read/write to the Flash while > running and use the CCLK to run the CPU. > > Chris. there is no need for persistant, the JTAG pins that you need are available always no matter config settings just wire jtag to io and use ring oscillator, thats it AnttiArticle: 110915
THe xilinx TCP/ip is buggy. HOwever there is an open source one in the edk you can implement easily. Its fine for clients but if you wish to setup a slave you need to fix the xilinx configuration bug. -- --------------------------------- --- -- - Posted with NewsLeecher v3.8 Beta 3 Web @ http://www.newsleecher.com/?usenet ------------------- ----- ---- -- -Article: 110916
>@MM: There is only one memory chip on my eval board, so the databus >should be 16 bit. >Now i worked out that the original mpmc2 reference design >"v4fx12lc_ddr_idpp_100mhz" also have this memory problem. The same >behaviour, a write to 0x0 also appears at 0x0+8. I built it as a blank >XPS design importing system.mhs, system.ucf files and ipcores. >Now I´m quite confused if it is principally possible to interface a 16 >bit memory correctly. I suppose there could be wrong parameter >settings. Any change to the MPMC2 has to be done with the GUI. It is not clear from your posts whether you actually ran the GUI to modify the controller or if you simply hacked the MHS file... The GUI seems to allow 16-bit wide memory... /MikhailArticle: 110917
Weng Tianxiang wrote:
> It is still problem !!!
> ** Error: $MODEL_TECH/../vhdl_src/std/textio.vhd(18): (vcom-1136)
> Unknown identifier "read_mode".
> What can I do to resolve the problem?
Maybe you have an old version of modelsim?
Upgrade or read the manual.
-- Mike Treseler
Rebuilding Supplied Libraries
Resource libraries are supplied precompiled in the modeltech
installation directory. If you need
to rebuild these libraries, the sources are provided in the vhdl_src
directory; a macro file is also
provided for Windows platforms (rebldlibs.do). To rebuild the
libraries, invoke the DO file
from within ModelSim with this command:
do rbldlibs.do
Make sure your current directory is the modeltech install directory
before you run this file.
Note
Because accelerated subprograms require attributes that are
available only under the 1993
standard, many of the libraries are built using vcom with the
-93 option.
Shell scripts are provided for UNIX (rebuild_libs.csh and
rebuild_libs.sh). To rebuild the
libraries, execute one of the rebuild_libs scripts while in the
modeltech directory.
Article: 110918Metastability is often blamed for things that have nothing to do with metastability. I am not an expert on Altera parts, but I understand metastability problems. It seems unbelievable to me that a Max-II flip-flop can misbehave for dozens of nanoseconds. Look somewhere else! Peter Alfke, Xilinx Applications. On Oct 25, 8:49 am, ghel...@lycos.com wrote: > I'm trying to snag a 90nS pulse with a 16MHz clock. On paper, it > should work just fine: 62.5 < 90. > > What I see is that if the leading edge of the pulse is co-incident with > the leading edge of the clock, the pulse is not clocked in. (Which I > think it should be; at least on the next clock edge.) > > To make it more "interesting", it will then miss the next few pulses; > mayby 10 or so. > > After that, it will go back to normal operation, clocking in the pulses > as intended. > > Anyone else seen something like this? Any pointers as to what to look > for? > > Regards, > GHArticle: 110919
ghelbig@lycos.com wrote: > I'm trying to snag a 90nS pulse with a 16MHz clock. On paper, it > should work just fine: 62.5 < 90. > > What I see is that if the leading edge of the pulse is co-incident with > the leading edge of the clock, the pulse is not clocked in. (Which I > think it should be; at least on the next clock edge.) > > To make it more "interesting", it will then miss the next few pulses; > mayby 10 or so. > > After that, it will go back to normal operation, clocking in the pulses > as intended. > > Anyone else seen something like this? Any pointers as to what to look > for? > I suspect that there is something else that you're not quite telling us and that the problem is that the setup time is being violated on some 'other' logic that is causing the pulses to be missed. In other words, if the 90ns pulse signal is 'D' and the output that gets 'missed' is 'Q', then does 'D' feed into ANY logic other than that for 'Q'? Like a state machine perhaps? If so, then whatever that other path(s) is is probably getting whacked out because of the setup time violation. To check this look at your fitted design in the Quartus Technology Map viewer and verify that 'D' is only an input to the flip flop that compute 'Q'. KJArticle: 110920
ghelbig@lycos.com wrote:
> I'm trying to snag a 90nS pulse with a 16MHz clock. On paper, it
> should work just fine: 62.5 < 90.
>
> What I see is that if the leading edge of the pulse is co-incident with
> the leading edge of the clock, the pulse is not clocked in. (Which I
> think it should be; at least on the next clock edge.)
>
> To make it more "interesting", it will then miss the next few pulses;
> mayby 10 or so.
>
> After that, it will go back to normal operation, clocking in the pulses
> as intended.
>
> Anyone else seen something like this? Any pointers as to what to look
> for?
Can you post a sample design? Nowadays FFs, even when they go metastable,
will only get into that state for a very brief time.
Assuming the incoming pulse is asynchronous to your system clock, I'd say
something like this should do the trick:
entity snagpulse is
port (
clk : in std_logic;
rst : in std_logic;
pulsein : in std_logic;
snagged : out std_logic
);
end snagpulse;
architecture justtoillustrate of snagpulse is
signal FF1, FF2, FF3;
begin
-- Sync the incoming pulse to the system clock
process(clk)
begin
if rising_edge(clk) then
FF1 <= pulsein;
end if;
end process;
-- Time-shift the synchronized pulse and check if we see a rising edge
process(clk, rst)
begin
if rst = '1' then
FF2 <= '0';
FF3 <= '0';
elsif rising_edge(clk) then
FF2 <= FF1;
FF3 <= FF2;
if FF2 = '1' and FF3 = '0' then
snagged <= '1';
end if;
end if;
end process;
end justtoillustrate;
Best regards,
Ben
Article: 110921Ben Twijnstra wrote: Hmmm... Seem to have forgotten the bits where snagged is set to '0' again - I'll trust everyone's intelligence to add the appropriate two statements. Best regards, BenArticle: 110922
Brad Smallridge wrote: >> Well, you "could" but, the old spartan method works fine. >> You can also use only one output DDR flip flop connected to a OBUFDS >> that will output a differential signal on two pins. > > I guess my confusion is that when you go to the FPGA Editor one sees > an OSERDES box near the output pin and not the set of registers you see > in a Spartan. > > This is a differential output for an xclk Camera Link interface, > if that matters. Not a memory device. > > Brad Smallridge > aivision > > You may still instantiate an ODDR primitive followed by an OBUFDS. The OSERDES is a superset of ODDR, so instantiating the ODDR will set up the OSERDES as an ODDR. -KevinArticle: 110923
kdfake@spam.com wrote: > THe xilinx TCP/ip is buggy. HOwever there is an open source one in the edk you can implement easily. Its fine for > clients but if you wish to setup a slave you need to fix the xilinx configuration bug. Are you saying there is a bug in the xilinx lwip port when using it as a server? What is it? Alan NishiokaArticle: 110924
Antti wrote: > Dave Pollum schrieb: > > > Antti wrote: > > > > > > I had cold recently too. > > > But I am serious about designing and soft-core that uses 0 slices, 0 > > > luts and 0 FF's :) > > > > > And this design has no inputs, outputs, or clocks, either? > > -Dave > Why? > > it is a clocked desing with lots of inputs and outputs, > no problems with them at all. > > it is really doable and fun thing to design. > > Antti Hmmm....I wasn't sure if you were joking when you said "0 slices, 0 luts and 0 FF's". I assumed that there was nothing left. I'm guessing that I/O buffers, clock logic, and interconnect circuitry would be left (I'm faimiliar with CPLDs, but I'm still learning about FPGAs). -Dave Pollum
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z