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On Wed, 18 Oct 2006 16:33:31 GMT, samiam <samiamSPAMTHIS@spamalert.com> wrote: >Figured this was the place to ask (comp.arch.embedded or comp.arch.fpga) > >Whats the cheapest board to study VHDL on? > >Ideally Id like an FPGA based board with a few inputs (dip >switches,toggles?), some outputs (parallel or serial connector, some >leds) < $100 > >I am looking on ebay now, and I see one or two boards well above $100. >Any suggestions? > >Thanks in advance This is another low-cost option - not many IOs but easy to add your own on some protoboard : http://shop.trenz-electronic.de/catalog/product_info.php?products_id=81Article: 110651
Alex wrote: > Hi, Nigel. > Thanks for clarifications. > Please see my comments below. > > NigelE wrote: > > > Alex, I think you need to be careful not to confuse the generic use of > > terms like entities (things) in the AVM cookbook with VHDL key words. > > This may be not a problem : I am pure Verilog coder ;) > > > I agree it is difficult to tie down a definition of a transaction, as > > transactions can be different things to different people > > eg a h/w designer may want to identify individual transfers of data on > > a bus as a transaction, while someone viewing the design at a higher > > level is more interested in frames or packets, while at a system level > > it may be a message between s/w on different processors. > > All are valid transactions. > > That's sound like a problem. Transaction definition is too broad to be > useful. To clarify things, different companies developed their own > understanding of transaction. (see link to the article below). > > > In terms of the AVM, the basic TLM communication mechanism is based on > > the semantics of the OSCI TLM, implemented in SystemC and/or > > SystemVerilog. > > OSCI definition of transaction also seems too broad to be useful: > > "OSCI seems to have the most liberal interpretation. OSCI includes > several levels of abstraction under TLM, including Programmer's View > (PV), which contains no timing; Programmer's View with Timing (PVT), > which adds timed protocols and can analyze latency or throughput; and > Cycle Accurate, which is accurate to the clock edge but does not model > internal registers. > > >From an OSCI point of view, pretty much everything above RTL can be > considered TLM, said Pat Sheridan, OSCI executive director and the > director of marketing at CoWare Inc. But the way most users think of > TLM appears to include just the untimed (PV) and cycle-approximate > (PVT) styles of modeling." > > http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=181503693&printable=true > > > > This defines the use of put(), get() and peek() function/task calls to > > transfer a transaction from one component to another. > > Which means that it is possible to use these convenient functions for > transaction communication. But, it is also possible to connect bus > master with the bus slave - they will also communicate with > transactions through the signal-level interface. And this is > transaction-level modeling too. > > > Both these languages support a component calling the tasks/functions of > > another component (using classes and/or interfaces). Thus my monitor > > can call the write() function of my scoreboard without needing to what > > it does. This allows me to change the scoreboard without effecting the > > monitor, provided the new scoreboard also implements a function called > > write(). > > There may be different methods for transaction communication for reuse. > For example, there are strong arguments against AVM method, where > monitor code has to be modified in order to communicate with specific > checking component. Since monitor is protocol-specific > (design-independent), it is usualy more reusable then design-specific > checker/scoreboard. Then, it may be a better idea for monitor to simply > "present" transaction without calling some external functions. Then, it > will be the task of checking component to grab needed data from needed > monitors when they are signalling about "transaction completion". This > make monitors to be independent from the "external world" and thus > highly reusable between the projects. > > In any case, functions/tasks presented by OSCI do not clarify the > meaning of transaction, but rather provide some implementational > details. > > > This is the basis for verification component reuse in the AVM (and > > other transaction based verification methodologies.) > > > > So in the AVM, a transaction is most commonly just a function/task call > > between verification components, thus the third definition. > > I agree. In this case, AVM may contain only third transaction > definition. This will greatly clarify the meaning of transaction in the > context of AVM. > > Regards, > -Alex I actually think the broad scope of TLM is one of its key strengths. Being able to apply the same techniques across a wide range of problems means the same methodology can be used at multiple abstraction levels. Transactors are used to communicate across these abstraction boundaries (not just the TLM<>signal boundary) enabling modelling to occur at the highest abstraction level appropriate resulting in smaller/faster code. A quick point on AVM monitors. The AVM provides a capability called an analysis port (which is an implementation of the OO design observer design pattern). An analysis port provides a mechanism for a monitor to broadcast transactions to zero or more subscribers (listeners) via a single write() function call. The subscribers need to implement a write() function, each of which can do different things (eg record functional coverage, update a scoreboard etc). Thus a monitor does not need to know in what context it will be used as it is only in the top level environment of the simulation where analysis components are registered onto a particular analysis port. This makes AVM monitors extremely generic, being able to be used in module, chip and system verification and across multiple designs using the same interface. Regards - NigelArticle: 110652
On Wed, 18 Oct 2006 10:38:36 -0700, Mike Treseler <mike_treseler@comcast.net> wrote: >samiam wrote: > >> Whats the cheapest board to study VHDL on? > >To learn vhdl, all you need is a simulator >to verify your uut and testbench code >and quartus or ise to view the rtl schematic. > >A board is of little value until >the code is complete and tested. > > -- Mike Treseler If you want to get something running as quickly as possible, some more practically-inclined people may prefer to dive straight in & play to get a feel of things. Different things work for differnt people. I taught myself about FPGAs & VHDL recently by completing a fairly complex project (including TFT display. SDRAM interface) without going anywhere near a simulator. I did however have a very good digital scope. http://www.electricstuff.co.uk/ektapro.html#newcontArticle: 110653
"himassk" <himassk@gmail.com> wrote in message
news:1161244375.063929.128940@i42g2000cwa.googlegroups.com...
> Hi,
> The static timing analysis report for my design is as follows:
>
> From: DAT_FSM/FULL_TEMP:CLK
> To: DAT_FSM/count[10]:D
> data required time 14.609
> data arrival time 15.146
> slack -0.537
>
> Could any one please suggest me the techniques to avaoid negative
> slack.
Try praising Bob.
No seriously... all that negative slack means is that you have too much
logic between flip-flop stages. So, you should simplify and/or pipeline your
circuit. (In fact, it could be a problem with I/O, but in this case it looks
like it's probably an internal path.)
Your timing analysis tool should be giving you a list of the nets on the
"critical paths" in your design. Look at the logic you've designed and think
carefully about whether it is overcomplicated, whether you can split a
computation or control decision into two stages to be performed in separate
clock cycles. Without specific details of what the circuit does, it's quite
hard to make more specific suggestions.
It might help to specify what tools you are using and what device you are
targeting. I'm just a little bit concerned that the "From:" net specifies a
clock... but this may be just the way your tool is reporting the timing
violation.
Good luck,
-Ben-
Article: 110654Roger wrote: > A design is built to work at 50MHz, but the deisgn when tested works > only at 48MHz. What > should we do to make the design meet specific timing constraint .i.e. > to make the design to make it work at 50 MHz? > Thanks > Did the P&R meet the constraints? have you run a post-layout simulation? You said "design is built do work at 50 MHz", but if the place & route did pass the constraints it is probably not uptodate (as John and Larry said). Al -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 110655
Eli Bendersky wrote: > The solution usually used is an external > reset circuit (they come packed in nice tiny ICs these days) that > provides a clean reset signal of 200 ms (or whatever you set it to) > whenever there's a problem with the supplies, and as a byproduct, when > the power is going up. Excuse me Eli, can you give me a reference for those tiny ICs? thanks a lot Al -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 110656
samiam wrote: > Figured this was the place to ask (comp.arch.embedded or comp.arch.fpga) > > Whats the cheapest board to study VHDL on? > > Ideally Id like an FPGA based board with a few inputs (dip > switches,toggles?), some outputs (parallel or serial connector, some > leds) < $100 > > I am looking on ebay now, and I see one or two boards well above $100. > Any suggestions? > > Thanks in advance The Digilent/Xilinx Spartan 3 Starter Kit is $99, and should do everything you want. LeonArticle: 110657
Frank Buss <fb@frank-buss.de> writes: > Petter Gustad wrote: > > > Altera MAXII developers kit. I think this was $99 last time I > > checked. It has LED's, USB, LCD display, temprature sensor, PCI, etc. > > Do you mean this board? > > http://www.altera.com/products/devkits/altera/kit-maxii-1270.html > > Looks like it costs $150 and it is an CPLD, only. And do you need an > additional programmer for it? If you want to try Altera and want to spend A byteblaster II prgramming cable is included. I got the board for $99 once. Maybe it was a special deal. The MAXII is a CPLD, but looks much like an FPGA even though there is an internal FLASH for configuration and user data. The Spartan3 is a nice starter kit as well. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 110658
Yes,
I want to integrate one port signal over a time.
Jaywant.
Al wrote:
> What do you mean by "integrator"? do you need to integrate over time,
> over frequency?
>
> Al
>
> Jai wrote:
> > Hello all,
> > I want to implement integrator using vhdl, all xilinx logic core, is
> > it available or anyone worked on this topic?
> >
> > Jaywant
> >
>
> --
> Alessandro Basili
> CERN, PH/UGC
> Hardware Designer
Article: 110659"jacko" <jackokring@gmail.com> writes: > i'm thinking of getting the MAX II $100 board too. can it work external > to the pc or pci only. does it auto program, can it be used to program > other cpld and can the display be made external off board, for case > mounting? i'd have to revert to on board gfx again as no free pci while > agp in use. It can be powered by USB so you don't need to have it in your PCI slot unless you will be designing some PCI logic. I don't know what you mean by autoprogram, but you download the programming file into the internal FLASH in the MAXII. When you power it on it will load the configuration from there. You can use it to program other devices, but that will require you to design some logic. Actually I use the board to program some microcontrollers over USB. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 110660
If you look at page 6 of the PDF datasheet that comes with the core you will see two simple formulas for RES and RATIO. These two feature in the TX and RX conf registers, and are used to set sample rate etc. You need to ensure TX is in master mode too. Marc > I'm trying to use the Opencores I2S master logic as the driver for my > test platform. > > The core came configured with SCK = 2.77 MHz and WS(left/right clock)= > 69.44 KHz. > > I would like to be able to reconfigure the core to generate SCK=3.07MHz > and WS=48 KHz. > > I played around with the conf variable but could not get the ratio I'm > looking for. > > Could I get some help? > > ThanksArticle: 110661
Has anyone recently done any benchmarking of Windows PC's for Xilinx ISE Compiles? Is ISE multithreaded? Can it use multiple processors (or cores)? Do big CPU caches help? Regards Marc P4-3GHz HT 2GB DDR2-533 RAMArticle: 110662
According to the manual, The sample rate is given by bit_rate/(RES * 2) If I choose the sample rate to be 48 KHz, and the resolution is 20-bits, the bit rate would be 1.92 Mbps. However, the RATIO would then be calculated as follows. RATIO= (wishbone_bus_clock - (sample_rate * RES * 8)) / (sample_rate * RES * 4) wishbone_bus_clock= 50 MHz sample rate = 48 KHz RES=20 bits which would then be equal to ~22 (10110) This is not giving me the values of 48KHz for WS and 3.072 MHz for i2s_sck. What am I missing? I really need some help. Thanks, cbr marc_ely wrote: > If you look at page 6 of the PDF datasheet that comes with the core you > will see two simple formulas for RES and RATIO. These two feature in > the TX and RX conf registers, and are used to set sample rate etc. > You need to ensure TX is in master mode too. > > Marc > > > I'm trying to use the Opencores I2S master logic as the driver for my > > test platform. > > > > The core came configured with SCK = 2.77 MHz and WS(left/right clock)= > > 69.44 KHz. > > > > I would like to be able to reconfigure the core to generate SCK=3.07MHz > > and WS=48 KHz. > > > > I played around with the conf variable but could not get the ratio I'm > > looking for. > > > > Could I get some help? > > > > Thanks From henrik.kirneh@gmail.com Thu Oct 19 04:54:10 2006 Path: newssvr13.news.prodigy.com!newsdbm04.news.prodigy.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!newsfeed.freenet.de!news.tiscali.de!uio.no!news.banetele.no!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Message-Id: <45376762$0$49201$14726298@news.sunsite.dk> From: Henrik Pedersen <henrik.kirneh@gmail.com> Subject: Re: WebPack on Linux Newsgroups: comp.arch.fpga Reply-To: henrik.kirneh@gmail.com Date: Thu, 19 Oct 2006 13:54:10 +0200 References: <4533cbef$0$49200$14726298@news.sunsite.dk> <pan.2006.10.16.22.59.58.430093@polybusPleaseDontSPAMme.com> <45353150$0$49200$14726298@news.sunsite.dk> <pan.2006.10.17.19.51.33.988757@polybusPleaseDontSPAMme.com> <45365e1c$0$49209$14726298@news.sunsite.dk> <pan.2006.10.18.17.09.42.134573@polybusPleaseDontSPAMme.com> User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 12 Organization: SunSITE.dk - Supporting Open source NNTP-Posting-Host: 217.116.244.170 X-Trace: news.sunsite.dk DXC=7CCaff0GO2S[eoV[BRG`:]YSB=nbEKnk[=EO><:f6NBPYDoQ\kQ?kDT^PgABlB42E_IHQFW\gATb[1VYSn^jGTgTGX_hS]faD:S\PhB;4ZK73Z X-Complaints-To: staff@sunsite.dk Xref: prodigy.net comp.arch.fpga:121618 Next problem. Running a simulation turns up the following error. ERROR:Simulator:222 - Generated C++ compilation was unsuccessful Seaching Xilinx.com does'nt give many ideas as to what is happening. Anyone here has a clue ? HenrikArticle: 110663
On Thu, 19 Oct 2006 13:54:10 +0200, Henrik Pedersen wrote: > Next problem. > > Running a simulation turns up the following error. > ERROR:Simulator:222 - Generated C++ compilation was unsuccessful > > Seaching Xilinx.com does'nt give many ideas as to what is happening. > > Anyone here has a clue ? > > Henrik What simulator are you using?Article: 110664
Hi I am working on some Spartan3 projects using ISE8.2 on WindowsXP. One of the designs (XC3S4000) instantiates a core from a 3rd party as an EDIF netlist. I then add all sorts of other home spun blocks around it. I am quite happy with the core's function, and am now just adding peripheral blocks and debugging them etc. This is proving frustrating due to the Xilinx tool ripping up and re-routing the whole design each time I compile. It takes 1.5hrs to recompile, which may not sound a lot, but to add a wire is a bit ridiculous IMHO. I would really like to fix down some of the blocks to stop the Xilinx tool re-placing etc. At first glance there seems to be many options in the Xilinx tools to do this, but I can't get any of them to work properly. So far I have tried the following: - Partitions. They don't work >at all< do they? I can't even add one and get it to pass through MAP. - Incremental Design Flow, I don't seem to be able to get ISE to use my area constraints, and how do you find out how big to make blocks in floorplanner? - Planahead. Beta, poor doc's, didn't know where to start really. Even my FAE doesn't have a scooby-doo about this one. - FPGA Editor Does anyone use the probe points to debug? I don't seem to have anywhere near a full netlist to choose from, even if I don't flatten So questions to experienced ISE users; 1) How do you tie blocks down? (or do you not bother?) 2) Are the 8.2 service packs an improvment? I briefly tried pack2 a couple of weeks back, but it destroyed one of my projects so I couldn't load it into a non SP version on another PC. Obviously backwards compatibility is not high on Xilinx's lists. 3) Does anyone use Floorplanner? Are there any GOOD tutorials out there? Regards MarcArticle: 110665
Hello. I'm designing an asynchronus circuit with combinatorial loops which are strongly required for the function of the circuit. To avoid unwanted logic optimization, the gates are seperated in different components. As mapper preferences, I've UNchecked the following options: - Trim unconnected signals - Logic optimization across hierarchie Synthesis works fine, translation even better, but mapping results in the following errors (some of the following kind): ERROR:MapLib:661 - LUT2 symbol "XLXI_1/wa_vh45/inputtemp<3>1" (output signal=XLXI_1/wa_vh45/SIGNALFELD<1><2>) has input signal "input<3>" which will be trimmed. See the trim report for details about why the input signal will become undriven. Unused block "XLXI_1/wa_vh45/inverters_i0/inverter_i1/output1" (ROM) removed. Xilinx Help and google-search didn't result in useful hints about MapLib:661 Looking at the RTL-Schematic, I find connections from the input to the output of the circuit, through the trimmed part of the circuit. Why does the mapper trim the needed components, and is there a possibility to keep software from thinking about the sense of the circuit and just doing what I want? The simulation with modelsim exactly does what I'm expecting. I need this circuit for my diploma-thesis and would be very thankful for every hint to solve this problem. Regards, Jonas PS: I'm using Xilinx ISE 7.1.04iArticle: 110666
jonas schrieb: > Hello. > > I'm designing an asynchronus circuit with combinatorial loops which are > strongly required for the function of the circuit. 1) use virtual wires that have an constant value, but are no seen as constant by the tools, that works always. 2) sometimes using primitives directly also works. AnttiArticle: 110667
On 18 Oct 2006 03:15:59 -0700, "Jai" <jaywant.kolhe@gmail.com> wrote:
>Hello all,
> I want to implement integrator using vhdl, all xilinx logic core, is
>it available or anyone worked on this topic?
It's very easy...
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity integrator is
port (
clock : in std_logic;
reset : in std_logic; -- synchronous, '1' to reset integrator
data_enable : in std_logic; -- '1' for clocks carrying new data
data : in std_logic_vector;
sigma : out std_logic_vector
);
end;
----------------
architecture RTL of integrator is
begin
process(clock) is
variable sum: signed(sigma'range);
begin
if rising_edge(clock) then
if reset = '1' then
sum := (others => '0');
elsif data_enable = '1' then
sum := sum + signed(data);
end if;
sigma <= std_logic_vector(sum);
end if;
end process;
end;
But the hard part is up to you...
* when should you reset?
* what size vector should you provide for "sigma"?
Tell us more about what you want to do. Do you want a leaky
integrator, or an unbounded one like mine? And so on...
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 110668Josh Rosen wrote: > On Thu, 19 Oct 2006 13:54:10 +0200, Henrik Pedersen wrote: > >> Next problem. >> >> Running a simulation turns up the following error. >> ERROR:Simulator:222 - Generated C++ compilation was unsuccessful >> >> Seaching Xilinx.com does'nt give many ideas as to what is happening. >> >> Anyone here has a clue ? >> >> Henrik > > What simulator are you using? I was told that Multisim was'nt supported for the free edition of webpack for Linux, så i'm trying to make the ISE simulator work. HenrikArticle: 110669
samiam wrote:
> Mike, I felt that having an FPGA board, where I can download the code,
> and do things ... "see" the results for myself, would only serve to
> reinforce what I am reading
>
> A simulator is one thing ... "seeing" the results on bare metal is
> another
Sorry I rained on your parade.
Trial and error synthesis using a logic analyzer works also.
I guess I spent too many years hooking up those
little clip leads and waiting for a trigger.
-- Mike Treseler
Article: 110670Thanks both for the replies. All my burning was done by the CPU, and I verified byte order etc. several ways so it wasn't that. Also the width matching is on by default so it wasn't that. However the mention of caching was spot on. I added the burst/cacheline support parameter and it is working now. Thanks again. SteveArticle: 110671
marc_ely wrote: > Has anyone recently done any benchmarking of Windows PC's for Xilinx > ISE Compiles? > > Is ISE multithreaded? > Can it use multiple processors (or cores)? > Do big CPU caches help? > > Regards > Marc > P4-3GHz HT 2GB DDR2-533 RAM I'm not sure if QuartusII or ISE is multithreaded but the first generation dual core systems I wasn't impressed with. My experience is my company provided me with a dual core system to do development work with. When my system wasn't living up to my expectations I did a little research. The MS Windows performance meter and some third party tools showed little activity. When it did it was about 85% or better, occasionally pegged. I did some other poking around on my system and discovered that they cheaped out with the graphics card and hard drives. My advice to you and this is partly experience and the other part gut feeling is compare the price difference between the Extreme and Dual Core chips if the price is negligible look for the one with faster front side bus (FSB) speed. And, the second item I'd look into is a caching SATA controller that supports mirror and some really fast hard drives. Avoid striping the drives there is a performance hit but try mirroring. From my observations, development tools I use are mostly memory and hard drive bound. When you compile and PAR your design a fast CPU is beneficial but it is also working with a lot supporting files and storing/retrieving information from memory. In the past most users report the biggest benefits from more and faster memory. DerekArticle: 110672
For that to be a time integrator wouldn't you need to multiply your sigma result with the period of the clock. Of course, this approximates the wave as a series of rectangles of width T. You could do something more complex by drawing a line between two consecutive samples and use that line to make two rectangle with width T/2 opposed to the larger rectangle. Or you could get really fancy and do polynomial interpolation to build finer grain estimates. ---Matthew Hicks "Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message news:qeuej25n60a6fi2nci8vvhji1d9sremond@4ax.com... > On 18 Oct 2006 03:15:59 -0700, "Jai" <jaywant.kolhe@gmail.com> wrote: > >>Hello all, >> I want to implement integrator using vhdl, all xilinx logic core, is >>it available or anyone worked on this topic? > > It's very easy... > > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all; > entity integrator is > port ( > clock : in std_logic; > reset : in std_logic; -- synchronous, '1' to reset integrator > data_enable : in std_logic; -- '1' for clocks carrying new data > data : in std_logic_vector; > sigma : out std_logic_vector > ); > end; > ---------------- > architecture RTL of integrator is > begin > process(clock) is > variable sum: signed(sigma'range); > begin > if rising_edge(clock) then > if reset = '1' then > sum := (others => '0'); > elsif data_enable = '1' then > sum := sum + signed(data); > end if; > sigma <= std_logic_vector(sum); > end if; > end process; > end; > > But the hard part is up to you... > * when should you reset? > * what size vector should you provide for "sigma"? > > Tell us more about what you want to do. Do you want a leaky > integrator, or an unbounded one like mine? And so on... > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.bromley@MYCOMPANY.com > http://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated.Article: 110673
On Thu, 19 Oct 2006 10:01:53 -0500, "Matthew Hicks" <mdhicks2@uiuc.edu> wrote: >For that to be a time integrator wouldn't you need to multiply your sigma >result with the period of the clock. Yes, definitely. Sorry, I was cheating and being careless. If the clock enable is asserted once per N clocks (constant N) and the clock period is constant, then the multiplier is constant too; that's my excuse :-) > Of course, this approximates the wave >as a series of rectangles of width T. You could do something more complex >by drawing a line between two consecutive samples and use that line to make >two rectangle with width T/2 opposed to the larger rectangle. Or you could >get really fancy and do polynomial interpolation to build finer grain >estimates. All perfectly true, as you know much better than I. Perhaps it's time for the OP to give us a bit more information about the application! I'm guessing that the proposed integrator forms part of a feedback loop, so that the sum value definitely won't grow without limit; but that's only a guess... maybe we need the thing to saturate as well. So many questions, so few answers :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 110674
On Thu, 19 Oct 2006 16:38:26 +0200, Henrik Pedersen wrote: > Josh Rosen wrote: > >> On Thu, 19 Oct 2006 13:54:10 +0200, Henrik Pedersen wrote: >> >>> Next problem. >>> >>> Running a simulation turns up the following error. >>> ERROR:Simulator:222 - Generated C++ compilation was unsuccessful >>> >>> Seaching Xilinx.com does'nt give many ideas as to what is happening. >>> >>> Anyone here has a clue ? >>> >>> Henrik >> >> What simulator are you using? > > I was told that Multisim was'nt supported for the free edition of webpack > for Linux, så i'm trying to make the ISE simulator work. > > Henrik I don't know anyone who is using the ISE simulator. Most people use NCsim, VCS or ModelSim, I use NC. If you are looking for a free simulator I'd suggest that you give icarus a try. http://www.icarus.com/eda/verilog/
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