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What do you mean by "integrator"? do you need to integrate over time, over frequency? Al Jai wrote: > Hello all, > I want to implement integrator using vhdl, all xilinx logic core, is > it available or anyone worked on this topic? > > Jaywant > -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 110576
I am creating my own test IP and can't find the proper way to generate external NET connection with logic using graphics tools of EDK how do I generate the "mytest_rx_pin" entries in system.ucf ? (In port flat view, I never had the choice to "make an external connection" in my tes_0 instance, as said in docs...) my test is rather simple : I want access from microblaze to H13 button as in : value = XIo32_In(0x42000000); (value changes if buton is pressed) my config is spartan3E starter kit and EDK 8.1. user_logic.vhd -=-=-=-=-=-=-= ... signal data : std_logic; ... IP2Bus_data(0) <= data; mytest.vhd -=-=-=-=-= -- ADD USER PORTS BELOW THIS LINE ------------------ test_rx : in std_logic; -- ADD USER PORTS ABOVE THIS LINE ------------------ ... ------------------------------------------ -- instantiate the User Logic ------------------------------------------ test_rx => test_x,Article: 110577
On 17 Oct 2006 12:12:37 -0700, "Antti" <Antti.Lukats@xilant.com> wrote: > >Brian Drummond schrieb: > >> On 16 Oct 2006 04:43:54 -0700, "Antti" <Antti.Lukats@xilant.com> wrote: >> >ML505 - allows PCIe testing >> >ML523 - GTP characterization board >> >ML555 - 8x PCIe card >> >> Hmmm, www.xilinx.com "search" on "ML505" returns 0 results... >> these boards sound interesting though! >> >> - Brian > >you didnt look deep enough :) or Google didn't :) >ok here is the link > >http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/capabilities/PCIe.htm Thanks! I guess we just have to wait a little longer for real information... - BrianArticle: 110578
I reply to myself : it is possible to manualy edit the MPD file and add a PORT ligne as needed is there a better way ? rpons...@gmail.com wrote: > I am creating my own test IP and can't find the proper way to generate > external NET connection with logic using graphics tools of EDK > > how do I generate the "mytest_rx_pin" entries in system.ucf ? (In port > flat view, I never had the choice to "make an external connection" in > my tes_0 instance, as said in docs...) > > my test is rather simple : I want access from microblaze to H13 button > as in : > value = XIo32_In(0x42000000); > (value changes if buton is pressed) > > > my config is spartan3E starter kit and EDK 8.1. > > user_logic.vhd > -=-=-=-=-=-=-= > ... > > signal data : std_logic; > ... > > IP2Bus_data(0) <= data; > > mytest.vhd > -=-=-=-=-= > -- ADD USER PORTS BELOW THIS LINE ------------------ > test_rx : in std_logic; > -- ADD USER PORTS ABOVE THIS LINE ------------------ > > ... > > ------------------------------------------ > -- instantiate the User Logic > ------------------------------------------ > test_rx => test_x,Article: 110579
Brian Drummond schrieb: > On 17 Oct 2006 12:12:37 -0700, "Antti" <Antti.Lukats@xilant.com> wrote: > > > > >Brian Drummond schrieb: > > > >> On 16 Oct 2006 04:43:54 -0700, "Antti" <Antti.Lukats@xilant.com> wrote: > > >> >ML505 - allows PCIe testing > >> >ML523 - GTP characterization board > >> >ML555 - 8x PCIe card > >> > >> Hmmm, www.xilinx.com "search" on "ML505" returns 0 results... > >> these boards sound interesting though! > >> > >> - Brian > > > >you didnt look deep enough :) > or Google didn't :) > > >ok here is the link > > > >http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/capabilities/PCIe.htm > > Thanks! I guess we just have to wait a little longer for real > information... > > - Brian the main features of 4xx and 5xx boards should be fairly similar so you can look at 405, 423, 455 documentation, to have approx idea what featueres each board has ML505 should be fairly same as ML501 as the same reference designs work on both (except the GTP stuff) - ML505 has some knobs replaced by rotary encoder I think. AnttiArticle: 110580
I just did this yesterday for the first time. I had EDK generate my peripheral and then I had to edit .ucf, .mhs, .mpd, peripheral.vhd, AND user_logic.vhd to add my clock and ADC lines. If you find a faster way please post. Thanks, Clark <rponsard@gmail.com> wrote in message news:1161171882.555693.74530@e3g2000cwe.googlegroups.com... > I reply to myself : > > it is possible to manualy edit the MPD file and add a PORT ligne as > needed > > is there a better way ? > > > rpons...@gmail.com wrote: > > I am creating my own test IP and can't find the proper way to generate > > external NET connection with logic using graphics tools of EDK > > > > how do I generate the "mytest_rx_pin" entries in system.ucf ? (In port > > flat view, I never had the choice to "make an external connection" in > > my tes_0 instance, as said in docs...) > > > > my test is rather simple : I want access from microblaze to H13 button > > as in : > > value = XIo32_In(0x42000000); > > (value changes if buton is pressed) > > > > > > my config is spartan3E starter kit and EDK 8.1. > > > > user_logic.vhd > > -=-=-=-=-=-=-= > > ... > > > > signal data : std_logic; > > ... > > > > IP2Bus_data(0) <= data; > > > > mytest.vhd > > -=-=-=-=-= > > -- ADD USER PORTS BELOW THIS LINE ------------------ > > test_rx : in std_logic; > > -- ADD USER PORTS ABOVE THIS LINE ------------------ > > > > ... > > > > ------------------------------------------ > > -- instantiate the User Logic > > ------------------------------------------ > > test_rx => test_x, >Article: 110581
which FPGA are you using? All the families, basically, have embedded RAM blocks which can be easily instantiated both in a schematic and hdl way. I did it few times with Altera chips APEX and FLEX and turned out very simple on quartus. I usually make a schematic, place the block that I need, follow the wizard and once is done i export the vhdl so that I will place it in my hierarchy. There's going to be an easier way though, this is just the one I worked out by myself. cheers Al ashu_19_1980@yahoo.com wrote: > hiiiiiii, > > I am designing a switch controller to be implemented on > FPGA,i need to map memory blocks to FPGA,are there any libraries to do > this?Does the simulator automatically map the memory?if so give me an > example how to do this. > > regards, > hema. > -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 110582
M E wrote: > I'm doing a new design with a SERDES at 1.6Gbps. For cost reasons, I'm > using an FPGA without serial IO, so I'm looking at using one of the > following TI parts: > > - TLK2501 > - TLK2521 > - TLK2701 > > I am having trouble choosing between them. They all look basically the > same except that the 2521 is 18-bits using Start/Stop bits, while the > other 2 use 8B/10B coding. The 2701 gives you direct access to the > K-codes, while the 2501 just gives you sync and error signals. > > My question is this: Is there a reason I should prefer 8B/10B over > 18-bit? I don't really need the additional 2 bits, but my concern is > with maintaing sync. I need to burst packets through, but there is no > way to retransmit anything if there is any kind of loss. It needs to > be obvious when packets start and end. > > I'd also like to be able to eventually talk to one of these with a > Rocket-IO, so that sort of compatibility is necessary. > > Any advice would be appreciated. > > Thanks, > Matt The technical comparison depends on your application. If you aregoing to drive a cable between two different pieces of equipment, then 8B/10B encoding is superior for a number of reasons. If you are going point to point (between two boards in a chassis) then start/stop may be sufficient. Start/stop has a lower overhead than 8B/10B encoding, so your power will be a little lower (effective line rate at 1.6Gb.s throughput -> 1.8Gb/s) than 8B/10B encoding (line rate 1.92Gb/s), but start/stop has run lengths of up to 17 bits where 8B/10B encoding has a maximum run length of 5. This simplifies coupling (for AC coupled signals, such as across cables). The shorter run length also simplifies the interconnect ac model (by limiting the low frequency end of the effective bandwidth). 8B/10B encoding also has low DC wander (zero across long times) whereas start/stop does not. Much depends on 'what you want to connect to' and how. Cheers PeteSArticle: 110583
Hello, I'd like to know if there is any documentation on the (presumably normal) form of the LUT boolean equations as used by Xilinx to describe the LUT's operation in fpga_editor and xdl files, and if there is any existing algorithm to get this normalized equation from the LUT's memory contents. Thank you, JBArticle: 110584
jbnote wrote: > Hello, > > I'd like to know if there is any documentation on the (presumably > normal) form of the LUT boolean equations as used by Xilinx to describe > the LUT's operation in fpga_editor and xdl files, and if there is any > existing algorithm to get this normalized equation from the LUT's > memory contents. think of the LUT's memory contents are the 0 and 1 entries in a Karnaugh Map. It is straightforward to derive the corresponding logic equation from that. I used the algorithms from k-map http://k-map.sourceforge.net for this. Markus > > Thank you, > JB >Article: 110585
Hi, I am having a problem with simulation of EDIF netlist file. I have generated EDIF file using leonardospectrum synthesis tool, then created a Xilinx project with ISE and provided the ucf file. But here, I am not able to get the sdf and timesim files for the timing simulation. Please, tell me how to go about this.Article: 110586
rponsard@gmail.com wrote: > I reply to myself : > > it is possible to manualy edit the MPD file and add a PORT ligne as > needed > > is there a better way ? > > > rpons...@gmail.com wrote: >> I am creating my own test IP and can't find the proper way to generate >> external NET connection with logic using graphics tools of EDK >> >> how do I generate the "mytest_rx_pin" entries in system.ucf ? (In port >> flat view, I never had the choice to "make an external connection" in >> my tes_0 instance, as said in docs...) >> >> my test is rather simple : I want access from microblaze to H13 button >> as in : >> value = XIo32_In(0x42000000); >> (value changes if buton is pressed) >> >> >> my config is spartan3E starter kit and EDK 8.1. >> >> user_logic.vhd >> -=-=-=-=-=-=-= >> ... >> >> signal data : std_logic; >> ... >> >> IP2Bus_data(0) <= data; >> >> mytest.vhd >> -=-=-=-=-= >> -- ADD USER PORTS BELOW THIS LINE ------------------ >> test_rx : in std_logic; >> -- ADD USER PORTS ABOVE THIS LINE ------------------ >> >> ... >> >> ------------------------------------------ >> -- instantiate the User Logic >> ------------------------------------------ >> test_rx => test_x, > I always edit these files manually (.mpd, .pao, .bbd and .vhd). AFAIK there is no better/faster way of doing this. The documentation says: For peripheral creation, you must do the following: Indicate the module name and destination, such as the XPS project or EDK repository in which the peripheral must be stored. Select the bus interface to which the peripheral is targeted. For OPB/PLB peripherals, select and configure IPIF services. These are common functions required by most peripherals. If you select this, reduce the amount of HDL code you write. For FSL peripherals, select and configure the FSL bus interface and driver function. -> Implement user logic in generated files. This requires the use of common HDL-based design flows. Implement peripheral driver files. This requires the use of common software-based design flows. FrankArticle: 110587
what is netgen software? Is it available with Xilinx? Petter Gustad wrote: > "Mak" <makarand.deshmukh@gmail.com> writes: > > > I am having a problem with simulation of EDIF netlist file. I have > > generated EDIF file using leonardospectrum synthesis tool, then created > > a Xilinx project with ISE and provided the ucf file. But here, I am not > > able to get the sdf and timesim files for the timing simulation. > > Please, tell me how to go about this. > > netgen can generate a verilog and sdf file from post-par ncd file. > > Petter > -- > A: Because it messes up the order in which people normally read text. > Q: Why is top-posting such a bad thing? > A: Top-posting. > Q: What is the most annoying thing on usenet and in e-mail?Article: 110588
Hello Markus, Thank you for the quick reply and the pointer. I also had a look at wikipedia before posting, which lists several algorithms for getting a boolean equation from a truth table. My question was more about the fact that the number of possible equations is huge, and I was under the impression that Xilinx used some kind of normal form for this, meaning that for each LUT content the equation as written in the XDL or NCD would be deterministic. I may have completely misunderstood the problem though. JBArticle: 110589
jbnote wrote: > Hello Markus, > > Thank you for the quick reply and the pointer. I also had a look at > wikipedia before posting, which lists several algorithms for getting a > boolean equation from a truth table. > My question was more about the fact that the number of possible > equations is huge, and I was under the impression that Xilinx used some > kind of normal form for this, meaning that for each LUT content the > equation as written in the XDL or NCD would be deterministic. > > I may have completely misunderstood the problem though. > > JB > Xilinx specifies the content as a hex string that reflects the LUT content as though it is a 16x1 memory. It is up to you to reduce the logic equation if that is what you want.Article: 110590
I have seen a picture and specs of the ML555 and looks not a bad board but I am sure we can do better. Anyone with particular feature wants let us know before we get as far as the launch and they might get included. John Adair Enterpoint Ltd. - Home of Broaddown4. The Ultimate Virtex-4 Development Board. http://www.enterpoint.co.uk "Antti" <Antti.Lukats@xilant.com> wrote in message news:1161171979.295249.126390@h48g2000cwc.googlegroups.com... > Brian Drummond schrieb: > >> On 17 Oct 2006 12:12:37 -0700, "Antti" <Antti.Lukats@xilant.com> wrote: >> >> > >> >Brian Drummond schrieb: >> > >> >> On 16 Oct 2006 04:43:54 -0700, "Antti" <Antti.Lukats@xilant.com> >> >> wrote: >> >> >> >ML505 - allows PCIe testing >> >> >ML523 - GTP characterization board >> >> >ML555 - 8x PCIe card >> >> >> >> Hmmm, www.xilinx.com "search" on "ML505" returns 0 results... >> >> these boards sound interesting though! >> >> >> >> - Brian >> > >> >you didnt look deep enough :) >> or Google didn't :) >> >> >ok here is the link >> > >> >http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/capabilities/PCIe.htm >> >> Thanks! I guess we just have to wait a little longer for real >> information... >> >> - Brian > > the main features of 4xx and 5xx boards should be fairly similar > so you can look at 405, 423, 455 documentation, to have approx > idea what featueres each board has > > ML505 should be fairly same as ML501 as the same reference designs > work on both (except the GTP stuff) - ML505 has some knobs replaced > by rotary encoder I think. > > Antti >Article: 110591
John Adair schrieb: > I have seen a picture and specs of the ML555 and looks not a bad board but I > am sure we can do better. Anyone with particular feature wants let us know > before we get as far as the launch and they might get included. > > John Adair I am sure. We can do it better. Anytime. 100% Antti http://groups.google.com/group/virtex5Article: 110592
hi indi16.3.3 release: less stringent timing requirements 60MHz 12 MIPS 332 LEs 30ns external memory for 60MHz 64MHz is target frequency for easy video generation of 8MHz pixel clock. jacko wrote: > rickman wrote: > > jacko wrote: > > > all instructions are load -> alu -> store (using the 1 memory bus) > > > this would make a two cycle minimum. for 2 memory accesses. > > > each memory access takes 2 cycles, this is due to 1 cycle data out or > > > in settling time before 1 cycle latching time. this allows cheap > > > external memory use, internal use could reduce mem io to 1 cycle, but > > > not designed in yet. > > > so total = 4 clock cycles so far. > > > then 2 instructions come in one word so 2 cycles for fetch but only 1 > > > equiv cycle per instruction. > > > so grand total of 5 cycles per instruction. > > > > > > is that clearer? the two cycle memory access also makes for an easier > > > WAIT pin which halts the processor after the current memory access. > > > memory access wait state insertion would have to occur via clock > > > division. > > > > That is a big difference. My design only runs on internal FPGA memory. > > It is intended to be a chip controller, not a general purpose CPU. > > > > > > > I think it may work, got rid of many logic errors by simplyfying some > > > logic and changing the external bus, moved to 5 cycle per instruction > > > throughput in design while maintaining low complexity. This required > > > the removal of RAS, CAS addressing easy direct support, but SRAM is > > > best at 128KB maximum memory size ( except when using CS[1] to isolate > > > stack memory from program and data memory. (( CS[0] selects program=0 > > > or data=1 memory.but no dictionary extension can occur if CS[0] is used > > > like this. )) > > > > > > cheers. > > > > > > p.s. when you must simply fit in 330 LEs then this is whats needed. > > > > What is the application for this design? > > 1. Open and Free Specification IP > 2. For the hell of it > 3. 2007 Christmas toy market, investigating options > 4. 8-bit replacement of low complexity > 5. 32 and 64 bit options should not be that hard to engineer. need to > find best utility for extra 16 or 48 bits in instruction word. > 6. test before manufacture in full custom as a 44-pin QFP. > > there may be others. Any interested Fab $ 0.25 per chip royalty with > right to use any utility ROM images and more complicated 32 and 64 bit > technologies. > > cheersArticle: 110593
"Mak" <makarand.deshmukh@gmail.com> writes: > I am having a problem with simulation of EDIF netlist file. I have > generated EDIF file using leonardospectrum synthesis tool, then created > a Xilinx project with ISE and provided the ucf file. But here, I am not > able to get the sdf and timesim files for the timing simulation. > Please, tell me how to go about this. netgen can generate a verilog and sdf file from post-par ncd file. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 110594
Figured this was the place to ask (comp.arch.embedded or comp.arch.fpga) Whats the cheapest board to study VHDL on? Ideally Id like an FPGA based board with a few inputs (dip switches,toggles?), some outputs (parallel or serial connector, some leds) < $100 I am looking on ebay now, and I see one or two boards well above $100. Any suggestions? Thanks in advanceArticle: 110595
Hi all, I'm new to the Xilinx FPGA FIR filter and would like to ask for help. I have two (X and Y) channels and their frequency is about 10Mhz. Using 2 14-bits ADC with sampling 50Mhz. I have my Xilinx clock about 50Mhz. How many taps for each channel is necessary for doing a cutoff frequency of 10MHz? How many bits should the coefficients length is? how to do a optimal design? I have to use FIR because my moving avaraging doesn't solve the problem. What other terms I need to consider? is my Spartan 3 xcs3s400 enough? 16 multipliers. is that 1 tap require 1 multiplier. If so, I would get a virtex II pro. board. At last, I want to say thank you for looking at my thread and I hope you can answer my questions. thanks again, Kenny,Article: 110596
On a sunny day (Wed, 18 Oct 2006 11:46:44 -0500) it happened "cutemonster" <ckh827@hotmail.com> wrote in <9qKdnRAOY6vpx6vYRVn_vA@giganews.com>: > >Hi all, I'm new to the Xilinx FPGA FIR filter and would like to ask forhelp. >I have two (X and Y) channels and their frequency is about 10Mhz. >Using 2 14-bits ADC with sampling 50Mhz. >I have my Xilinx clock about 50Mhz. > >How many taps for each channel is necessary for doing a cutoff frequencyof 10MHz? > >How many bits should the coefficients length is? how to do a optimaldesign? > >I have to use FIR because my moving avaraging doesn't solve the problem. > >What other terms I need to consider? This is free: http://www.mediatronix.com/FIRTool.htm From henrik.kirneh@gmail.com Wed Oct 18 10:02:22 2006 Path: newssvr21.news.prodigy.com!newsdbm04.news.prodigy.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!newsfeed.freenet.de!news-out1.kabelfoon.nl!newsfeed.kabelfoon.nl!bandi.nntp.kabelfoon.nl!news.banetele.no!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Message-Id: <45365e1c$0$49209$14726298@news.sunsite.dk> From: Henrik Pedersen <henrik.kirneh@gmail.com> Subject: Re: WebPack on Linux Newsgroups: comp.arch.fpga Reply-To: henrik.kirneh@gmail.com Date: Wed, 18 Oct 2006 19:02:22 +0200 References: <4533cbef$0$49200$14726298@news.sunsite.dk> <pan.2006.10.16.22.59.58.430093@polybusPleaseDontSPAMme.com> <45353150$0$49200$14726298@news.sunsite.dk> <pan.2006.10.17.19.51.33.988757@polybusPleaseDontSPAMme.com> User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 50 Organization: SunSITE.dk - Supporting Open source NNTP-Posting-Host: 217.116.244.170 X-Trace: news.sunsite.dk DXC=b9Wdc@T3GT=RV[Kf06ReB9YSB=nbEKnk;4Vnb:@f4o6;YDoQ\kQ?kD4^PgABlB42E?IHQFW\gATb;1VYSn^jGTg4GX_hS]faD:3f?<_gk_01\2 X-Complaints-To: staff@sunsite.dk Xref: prodigy.net comp.arch.fpga:121549 Josh Rosen wrote: > On Tue, 17 Oct 2006 21:38:56 +0200, Henrik Pedersen wrote: > >> Josh Rosen wrote: >> >>> On Mon, 16 Oct 2006 20:14:07 +0200, Henrik Pedersen wrote: >>> >>>> Greetings >>>> >>>> How is this supposed to work ? >>>> >>>> I have installed webpack for Linux on my FC5 box, and that part is >>>> working. I can compile my VHDL files, generate fitterrepports etc. >>>> But the following does'nt work: >>>> >>>> "Assign Package Pins" >>>> When i click it, it says >>Started : "Assign Package Pins".<< >>>> But nothing happens. >>>> I think that the executable is a file name "pace", and when i run pace >>>> in a console window i get the error >>>> /opt/Xilinx/bin/lin/_pace: error while loading shared libraries: >>>> libXm.so.3: cannot open shared object file: No such file or directory >>>> I have installed openmotif, which should contain the file in question, >>>> but without any luck. >>>> >>>> Then i have tried executing different files in the /opt/Xilinx/bin/lin/ >>>> directory. (create_sdc, arwz, qtconfig) and a couple others all of them >>>> generates errors about missing libX?????.so files that actually are >>>> located in the same directory. >>>> >>>> How do i go about narrowing down the problem and getting it to work ? >>>> >>>> Henrik >>> >>> Make sure you have the compatibility libraries loaded. The Xilinx tools >>> are targeted at RHEL which is way behind Fedora so you need to load the >>> compatibility libraries. >> >> Sounds good and easy, but how do i go about doing that ? >> >> Henrik > > Use Yumex. Search for compat and then install the compat-libstdc++-33 > library. Allready installed. What am i missing here ? HenrikArticle: 110597
On Wed, 18 Oct 2006 19:02:22 +0200, Henrik Pedersen wrote:
> Josh Rosen wrote:
>
>> On Tue, 17 Oct 2006 21:38:56 +0200, Henrik Pedersen wrote:
>>
>>> Josh Rosen wrote:
>>>
>>>> On Mon, 16 Oct 2006 20:14:07 +0200, Henrik Pedersen wrote:
>>>>
>>>>> Greetings
>>>>>
>>>>> How is this supposed to work ?
>>>>>
>>>>> I have installed webpack for Linux on my FC5 box, and that part is
>>>>> working. I can compile my VHDL files, generate fitterrepports etc.
>>>>> But the following does'nt work:
>>>>>
>>>>> "Assign Package Pins"
>>>>> When i click it, it says >>Started : "Assign Package Pins".<<
>>>>> But nothing happens.
>>>>> I think that the executable is a file name "pace", and when i run pace
>>>>> in a console window i get the error
>>>>> /opt/Xilinx/bin/lin/_pace: error while loading shared libraries:
>>>>> libXm.so.3: cannot open shared object file: No such file or directory
>>>>> I have installed openmotif, which should contain the file in question,
>>>>> but without any luck.
>>>>>
>>>>> Then i have tried executing different files in the /opt/Xilinx/bin/lin/
>>>>> directory. (create_sdc, arwz, qtconfig) and a couple others all of them
>>>>> generates errors about missing libX?????.so files that actually are
>>>>> located in the same directory.
>>>>>
>>>>> How do i go about narrowing down the problem and getting it to work ?
>>>>>
>>>>> Henrik
>>>>
>>>> Make sure you have the compatibility libraries loaded. The Xilinx tools
>>>> are targeted at RHEL which is way behind Fedora so you need to load the
>>>> compatibility libraries.
>>>
>>> Sounds good and easy, but how do i go about doing that ?
>>>
>>> Henrik
>>
>> Use Yumex. Search for compat and then install the compat-libstdc++-33
>> library.
>
> Allready installed.
> What am i missing here ?
>
> Henrik
Have you set your LD_LIBRARY_PATH env variable? You need the following
either in your .cshrc or in your scripts that call the Xilinx tools,
set path = (${path} $XILINX/bin/lin)
setenv LD_LIBRARY_PATH ${LD_LIBRARY_PATH}:${XILINX}/bin/lin:${XILINX}/lib
setenv LMC_HOME ${XILINX}/smartmodel/lin/installed_lin
setenv NPX_PLUGIN_PATH ${XILINX}/java/lin/jre/plugin/i386/ns4
Article: 110598I'm sure you have seen it on Ebay but have a look at our Raggedstone1. Ebay wise look for the non-EEC price if you are in the US. Similar pricing on our own website. It just about gets under you $100 mark depending on the current exchange rate. For something much cheaper you probably talking about a CPLD board. John Adair Enterpoint Ltd. samiam wrote: > Figured this was the place to ask (comp.arch.embedded or comp.arch.fpga) > > Whats the cheapest board to study VHDL on? > > Ideally Id like an FPGA based board with a few inputs (dip > switches,toggles?), some outputs (parallel or serial connector, some > leds) < $100 > > I am looking on ebay now, and I see one or two boards well above $100. > Any suggestions? > > Thanks in advanceArticle: 110599
If you have "another stable clock", why don't you use that for your NCO ? Peter Alfke On Oct 17, 11:08 pm, luca_gro...@hotmail.com wrote: > Hi everyone, > I'm currently using a vitex-II pro FPGA, I've implemented an NCO > frequency generator, which is supplied with a 64bit init & delta phase > value. I'm currently using a local oscillator to clock the NCO ( must > use specific local oscillator) but this does contain a margin of offset > and drift thus influencing output frequency of NCO. A compensation > circuit which includes another stable clock is used to correct the > drift and offset by using a frequency counter on both clocks then > calculating appropriate delta phase to compensate. My problem is that > my equation to calculate adjusted delta which requires a 64 bit > division > > Delta2 = (count2/count1) * delta1 > > Delta2 = new delta phase with correction > Count2 = frequency counter for Local Oscillator > Count1 = frequency counter for external Oscillator > Delta1 = Original calculated delta phase to product output frequency > > What would be the most appropriate way of doing this calculation, > especially with the division? also time constraints, everyone 1.6ms > roughly this will occur. > Maybe this could be done differently? Ideas I've been thinking about > are on the lines of, Maybe reduces the counting resolution ? use > internal PPC (CPU) > > Any advice would be appreciated :) > Cheers Luca
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