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I would like to remotely force a reconfiguration of my XUP board from CompactFlash by talking to the SysACE chip, perhaps with an iMPACT script. According to the "System ACE CompactFlash Solution" document (ds080.pdf), the necessary capability is available through the CONTROLREG register, but that register is unfortunately not exposed through the JTAG interface (as verified in the xccace.bsd BSDL file). But perhaps there's some other way of accomplishing the same thing? Does anybody have any suggestions?Article: 110726
Do you know any util links where I can fund materials helping me. Antti Lukats ha scritto: > "Adriano" <adrianotamburo@libero.it> schrieb im Newsbeitrag > news:1161355598.926990.281240@i3g2000cwc.googlegroups.com... > > Sorry, but I'm a very beginner of the FPGA technologies. What does "the > > BSCA primitive" mean exactly? > > Do you know any examples that they could help me?? > > > > Thanks. > > > > Antti ha scritto: > > > >> Adriano wrote: > >> > I'm implementing some Image Processing algorithms in VHDL, I'm testing > >> > these algorithms > >> > on the FPGA Spartan IIE xc2s200E. Is there any way to use the JTAG pins > >> > > >> > of the xc2s200E for user I/O? I want to download data from the PC, via > >> > a Parallel Port > >> > to JTAG Port on the xc2s200E. > >> > >> not directly but you can use the BSCA primitive to implement > >> some custom gateway that passes the data to your ip core > >> > >> Antti > > > sorry BSCAN > > it allows user logic to added into JTAG chain. > its mostly 'advanced' topic - so there arent much easy to use examples. > > you can download the xilinx picoblaze stuff some of the files there use > the BSCAN to load BRAMs over jtag > > anttiArticle: 110727
Adriano schrieb: > Do you know any util links where I can fund materials helping me. > > Antti Lukats ha scritto: > > > "Adriano" <adrianotamburo@libero.it> schrieb im Newsbeitrag > > news:1161355598.926990.281240@i3g2000cwc.googlegroups.com... > > > Sorry, but I'm a very beginner of the FPGA technologies. What does "the > > > BSCA primitive" mean exactly? > > > Do you know any examples that they could help me?? > > > > > > Thanks. > > > > > > Antti ha scritto: > > > > > >> Adriano wrote: > > >> > I'm implementing some Image Processing algorithms in VHDL, I'm testing > > >> > these algorithms > > >> > on the FPGA Spartan IIE xc2s200E. Is there any way to use the JTAG pins > > >> > > > >> > of the xc2s200E for user I/O? I want to download data from the PC, via > > >> > a Parallel Port > > >> > to JTAG Port on the xc2s200E. > > >> > > >> not directly but you can use the BSCA primitive to implement > > >> some custom gateway that passes the data to your ip core > > >> > > >> Antti > > > > > sorry BSCAN > > > > it allows user logic to added into JTAG chain. > > its mostly 'advanced' topic - so there arent much easy to use examples. > > > > you can download the xilinx picoblaze stuff some of the files there use > > the BSCAN to load BRAMs over jtag > > > > antti try www.xilinx.com enter picoblaze click on search AnttiArticle: 110728
Aaron Curtin wrote: > Hi, I have a design that connects a Spartan 3e running a Microblaze > soft-core with an SPI unit attached to the OPB bus to a 16 Bit DAC unit > (DAC8534). The data I send to the DAC unit has the bit order reversed. > The SPI_OPB pheripheral has no way of reversing the shift out order > from what I can see. Below is a program snippet of sending data to the > dac unit: > ------------------------------------------------------------------------------------------------------------------------- > // Select the DAC Unit > XSpi_mSetSlaveSelectReg(XPAR_SPI_DAC_BASEADDR, SPI_DAC_SELECT); > > // Set the message data. > send_data[0]=0x20; // Control Register > send_data[1]=0x0F; // Upper 8 bit value > send_data[2]=0x0F; // Lower 8 bit value > > // Send the message data. > spi_transfer(send_data, 3); > > // Deselect the DAC Unit > XSpi_mSetSlaveSelectReg(XPAR_SPI_DAC_BASEADDR, SPI_NONE_SELECT); > ------------------------------------------------------------------------------------------------------------------------- > > The data sent to the dac unit appears as 0xF0F0 instead of 0x0F0F > disregarding the control byte. Does anyone know of how I can reverse > the bit order at a minimal overhead cost. Can you give an example of > bit order reversing? > > Thanks, > Aaron Curtin > Is the SPI selecting the correct register? If it was a consistent issue, then the register would also be reversed, one might think (so in your snippet you would address 0x04 for bit reversal). Interesting. A simple (very simplistic) bit order reverser (single cycle) would take 8 regs plus maybe a LUT. Something like reg [7:0] DataIn; reg [7:0] DataOut; ... in some always block DataOut[7:0] <= dataIn[0:7]; Of course, you could just have it always connected: assign DataOut[7:0] = DataIn[0:7]; Write it to DataIn, send it to SPI from DataOut. Cheers PeteSArticle: 110729
Hello, I am fairly certain the main reason for the "requirement" is because Xilinx IP Solutions has a validation platform with all eight lanes on one side of the FPGA. Xilinx guarantees what is listed in the datasheet, and it's prudent (as you can imagine) for Xilinx invest significant time in testing complex IP cores such as this one. Other topologies are possible. Three considerations come to mind, there may be others: 1. Using both sides requires that you distribute a common MGT reference clock to BOTH sides of the device on the PCB. Typically, this would be a clock derived from the 100 MHz reference on the PCIe connector. 2. Using both sides *may* make it more difficult to meet timing (that's not a promise, just something to think about). For instance, the physical layer is now having to stripe/assemble the data streams to/from MGT on opposite sides of the device. 3. You will require some IP core options that may not be available for general use through Core Generator. Specifically, the channel bonding signals that run between MGT need to be pipelined where the signal from the master crosses the device horizontally to the slaves on the other side. You may be familiar with the MASTER, 1HOP, and 2 HOP attributes for the channel bonding behavior. In addition to attribute changes, it also requires a connectivity change. If you have serious interest (versus "just curious"), I encourage you to follow up with Xilinx through your FAE or distributor. Eric > The datasheet of the Xilinx PCIe endpoint core states that an 8-lane > configuration requires an FX60. The size of the core does not justify > this. The 4-lane configuration supports FX20. > > What is the reason for this requirment? > I suspect that all lanes must be on the same side of the FPGA or a > similar constraint. But the datasheet does not state anything like that. > > Would be good to know that for doing a board layout.... > > Kolja SulimmaArticle: 110730
"Neil Steiner" <neil.steiner@vt.edu> schrieb im Newsbeitrag news:4538FD13.9080409@vt.edu... >I would like to remotely force a reconfiguration of my XUP board from >CompactFlash by talking to the SysACE chip, perhaps with an iMPACT script. >According to the "System ACE CompactFlash Solution" document (ds080.pdf), >the necessary capability is available through the CONTROLREG register, but >that register is unfortunately not exposed through the JTAG interface (as >verified in the xccace.bsd BSDL file). > > But perhaps there's some other way of accomplishing the same thing? Does > anybody have any suggestions? one solution is to download into the FPGA a very small special core that does nothing else as force reconfig using the MPU interface. if the bitstream done with compress enabled then it would be rather small other solution you can use the FPGA boundary scan to emulate acccess to the sysace MPU both not so easy but sure doable AnttiArticle: 110731
fpga_toys@yahoo.com wrote: > Mike Treseler wrote: > > Sorry I rained on your parade. > > Trial and error synthesis using a logic analyzer works also. > > I guess I spent too many years hooking up those > > little clip leads and waiting for a trigger. > > Not only are HP16xxx logic analyzers cheap on eBay these days, Anyone want mine? > but making one out of an FPGA is yet another fun project. it's real easy. The hard part is coming up with some nice host software! -aArticle: 110732
Kyle H. wrote: > > - "netlist shematic" (where do I find/how do I generate this?) > > still lost on this part, even more lost after talking with someone > about it. > Perhaps you want the "RTL schematic"? > > - "waveforms from timing simulation" (are these sythesis specific, or > > are these just my modelsim simulation waveforms?) > > same, I must be missing something very important here, from my > understanding they are not modelsim simulation waveforms, but still > don't know where to start. > I would assume these are the waveforms from Modelsim, however you need to simulate the back-annotated design, not the behavioral simulation. This is very straightforward if you use the Project Navigator GUI in ISE. If your testbench is included in the project you can list the processes available for the testbench and start Modelsim from the GUI with the appropriate model: Behavioral Post-Translate Post-Map Post-Place & Route > > and he also asks for the min/max clock freq, with slack times after a) > > sythesis, b) mapping and c) p&r > > > > I will have to define a clock period I assume? Do I enter this via the > > constraint editor? If so, maybe a syntax example of how I might do > > this? After that I just need to view the timing reports after each > > process (a,b and, c)? > > I've defined a timing constraint and I am able to come up with > min/max/slack, but I don't understand how to get it after each of the > three steps above (still). Again with the Project Navigator GUI you have items in the process window for "static timing" after each stage of the design (the post synthesis timing is part of the synthesis report). You may need to open up the process hierarchy a bit (click on the "+" signs) to find these: Post-Map Static Timing Report Post-Place & Route Static Timing Report Good Luck, GaborArticle: 110733
Do you think that it's possible to develop a bi-directional communication between FPGA and Computer Host using Picoblaze? Sorry, but I'm very confused on the way that I can do it. Antti ha scritto: > Adriano schrieb: > > > Do you know any util links where I can fund materials helping me. > > > > Antti Lukats ha scritto: > > > > > "Adriano" <adrianotamburo@libero.it> schrieb im Newsbeitrag > > > news:1161355598.926990.281240@i3g2000cwc.googlegroups.com... > > > > Sorry, but I'm a very beginner of the FPGA technologies. What does "the > > > > BSCA primitive" mean exactly? > > > > Do you know any examples that they could help me?? > > > > > > > > Thanks. > > > > > > > > Antti ha scritto: > > > > > > > >> Adriano wrote: > > > >> > I'm implementing some Image Processing algorithms in VHDL, I'm testing > > > >> > these algorithms > > > >> > on the FPGA Spartan IIE xc2s200E. Is there any way to use the JTAG pins > > > >> > > > > >> > of the xc2s200E for user I/O? I want to download data from the PC, via > > > >> > a Parallel Port > > > >> > to JTAG Port on the xc2s200E. > > > >> > > > >> not directly but you can use the BSCA primitive to implement > > > >> some custom gateway that passes the data to your ip core > > > >> > > > >> Antti > > > > > > > sorry BSCAN > > > > > > it allows user logic to added into JTAG chain. > > > its mostly 'advanced' topic - so there arent much easy to use examples. > > > > > > you can download the xilinx picoblaze stuff some of the files there use > > > the BSCAN to load BRAMs over jtag > > > > > > antti > > try > www.xilinx.com > enter picoblaze > click on search > > AnttiArticle: 110734
Zorjak wrote: > Ray Andraka wrote: > >>Zorjak wrote: >> >> >>>Hi. >>>I am trying to write generic VHDL code for FIR filter. generic >>>parametars should be word_length, filter_order. Can anybody help me >>>how to input filter coeficients. I tought something like, read >>>coeficitients from file and write it in some LUT table. Could it be >>>done (or something similar)? >>> >>>Thanks for help >>> >> >>If it is synthesizable code, it can't go and read files. What you can >>do though is have a helper function that converts your coefficient file >>into a VHDL package containing the coefficient constants. Write that >>package to a file, and then include that file with the rest of the >>design when you compile the design. The helper function can be >>non-synthesizable VHDL, C, Matlab or any other programming language you >>feel like using. Alternatively, you can cut and paste your coefficients >>into a VHDL package or directly into a constant array in your code. >> >>You can also pass the coefficients into the entity through a generic by >>defining an integer_array type in a top level package, referring to that >>package in the library declarations, and then putting the int_array in >>the generics like this: >> >> component matrix >> generic( >> coefs: int_array:= ( >> -62465, -8923, 24026, 39814, 41873, 33635, 18534, >>0,-18534,-33636,-41873,-39813,-24025, 8925, 62468, >> 48188, 27536, 10061)); >> port( >> clk : in std_logic; >> >>Leaving the integer array unconstrained allows you to put in an >>arbitrary number of coefficients (must be more than 1). > > > Thanks for your answer Ray > > I am using Altera Quartus|| software and I've seen there thet some > *.mif files are using for ram initialization so I thought could I do > something similar with my FIR filter. Can you help me with that helper > function if it isnt to much that I am asking. I am VHDL beginer and I > am not very familiar with it so any lkind of help would used me. > > If is to much that I asking, sory. > Thanks again > The *.MIF files are tie-ins to the altera tools, and have nothing to do with the VHDL. You don't have the hooks you need to get inside the place and route tools to bring in your own custom initialization. The helper program I talked about just has to write out a text file containing a VHDL package. The package contains a constant containing your coefficients.Article: 110735
"Adriano" <adrianotamburo@libero.it> schrieb im Newsbeitrag news:1161371194.956021.249000@e3g2000cwe.googlegroups.com... > Do you think that it's possible to develop a bi-directional > communication between FPGA and Computer Host using Picoblaze? > Sorry, but I'm very confused on the way that I can do it. I just gave you a reference where the BSCAN is used. you can use to implement different kind of protocols the picoblaze has nothing todo with it, it was just an example application where BSCAN is used. if you are confused then read the JTAG stuff BSCAN allows you to add custom scan chain in FPGA fabric, whatever you do there its up to you. anttiArticle: 110736
On 19 Oct 2006 09:19:03 -0700, "Tommy Thorn" <tommy.thorn@gmail.com> wrote: >I recently went from an Athlon 64 2.0 GHz/1 MiB L2$ to a E6600 Core 2 >Duo 2.4 GHz/4 MiB L2$. For my benchmark, the time for Synth/P&R went >from 12m34/33m40 to ~6m/~15m, thus more then double the P&R >performance. When overclocked to 3.3 GHz the result scaled to >5m54/11m12, thus 3X the P&R performance. Could you give us some info on what the disk subsystems look like for each machine? (ide, sata what speed, any raid? etc) > Other experiments confirm that >it scales linearly with frequency (assuming memory scales equally). What do you think explains for no change in synthesis for C2D change from 2.4GHz to 3.3GHz ?Article: 110737
enavacchia@virgilio.it wrote: > Hi all! > > We've some custom boards with i486 processor, some RAM, some dual port > ram and other stuff (interrupt controller, buffers, I/O transceiver and > so on). I'm investigating the opportunity to replace all of those > discrete ICs with soft/hard IP (cycle accurate), and syntesize the > system in an FPGA (Altera or Xilinx). > > Actually I don't care about costs and efforts that are involved in this > approach. The goal is to get a replacement for that processor without > re-writing the operating system and any other kernel routines. > > Any suggestions? As David suggested, why not use a Pentium off the shelf, say a PC104 board with Via or Transmeta? chip for low power or Intel for medium performance, will run way faster than any FPGA 486 ever could and you might even find a board thats alot like what you already have in compact form. I recall PC104 has atleast 100 vendors and these boards will be around for awhile. You may even find some with your fav FPGA vendor onboard too or you can just do a doughter board for ISA or PCI to finish things up. There may be some PC104 FPGA development boards around too. If it seems cost is no object as in say a mil boondoggle then these PC104 boards are pretty much ready to go. I suspect that if a FPGA 486 could be designed for 32b RISC clean code only, it wouldn't be such a big deal to get code running on it. It wouldn't likely ever be cycle accurate due to caches but abandoning the old segment stuff and arcane 8,16 bit codes would reduce the task possibly an order of magnitude since the main core is pretty RISC with microcode for everything else. Can't say if your code is dependant on those rarely used codes though. John JaksonArticle: 110738
> one solution is to download into the FPGA a very small special core that > does nothing else as force reconfig using the MPU interface. > if the bitstream done with compress enabled then it would be rather small Oh. I like it. I think I'm going to try that. Thanks.Article: 110739
mk wrote: > Could you give us some info on what the disk subsystems look like for > each machine? (ide, sata what speed, any raid? etc) I could, but it would misleading as it's completely irrelevent to the posted numbers. The benchmark is operating almost exclusively out of the buffer cache and even then it's not reading that much data. That said, for everything else disk latency matters a lot, so I used a single SATA 150 GB Raptor (15,000 RPM) in the new box. The old box had a quiet average speed Samsung PATA drive (7,200 RPM). > What do you think explains for no change in synthesis for C2D change > from 2.4GHz to 3.3GHz ? My measurements were too informal. There is a change, just not as substantial. I'd need to study this closer to understand what's going on. TommyArticle: 110740
Hello.
Im relatively new to VHDL and im doing a small project in which i've to
store the co-efficients of the FIR filter into the block ram at system
startup which are supposed to be used later by the filter block for
implementing the MAC operation needed for the filter.
I am using spartan II by xilinx. First of all, what i'd like to know is
that, what does the phrase 'infer from the code' imply in the context
of memory instantiation in vhdl or any HD.
I used to think that there are dedicated hardware memory blocks on the
FPGA and we need to address the port pins as in done in microcontroller
programming environments and the like. After reading for a while and
coming accross many codes for that, I now understand it as the
synthesis tool 'realises' such a block in the FPGA. The only
restriction we have is that we should write code keeping in mind the
actual hardware capabilities of the board and/or the target device.
Like incase of the XC2S50 device we can instantiate 8 blocks of 4K bits
each and so on.
Is my thinking correct in this regard or is there something which i am
overlooking and/on misinterpreting?
Now heres the second question: The block ram in the spartan II FPGA is
arranged as 4K blocks and the blocks can have variable address and data
bus widths depending on the width of the data bus.
My data is 10 bits wide and I actually need 9 (actually 8.6) bits to
address that data. So when I write the code for that, can I declare an
input port which is 10 bits wide (std_logic_vector(9 downto 0) ) or do
I have to specify it using a signal which is 16 bits wide. The xilinx
user manual says that the block ram can have data widths of 1,2,4,8,
and 16. So if I declare my signal as 10 bits wide does the tool infer
the code and create a 4K block with a data bus which is 16 bits wide.
Heres a sample code which I've adapted from my synthesis tool vendor's
reference guide:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY syncram_sndsmple IS
generic (
data_width : natural := 10;
addr_width : natural := 4);
port (
clk : in std_logic;
we : in std_logic;
addr : in std_logic_vector(addr_width - 1 downto 0);
data_in : in std_logic_vector(data_width - 1 downto 0);
data_out : out std_logic_vector(data_width - 1 downto 0));
END ENTITY syncram_sndsmple ;
--
ARCHITECTURE rtl OF syncram_sndsmple IS
type mem_type is array (2**addr_width downto 0) of
std_logic_vector(data_width - 1 downto 0);
signal mem : mem_type;
signal addr_reg : std_logic_vector(addr_width - 1 downto 0);
attribute block_ram : boolean;
attribute block_ram of mem : signal is true;
begin
singleport_sndsmple : process(clk)
begin
if clk'event and clk = '1' then
if we = '1' then
mem(conv_integer(addr)) <= data_in;
end if;
addr_reg <= addr;
end if;
end process singleport_sndsmple;
data_out <= mem(conv_integer(addr_reg));
END ARCHITECTURE rtl;
Is this enough for it to be up and running. If I instantiate a
component which uses the above entity will it create a 'RAM - like'
structure on the FPGA die while programming?
How does the tool know that it has to create a RAM when it synthesizes
the above code? in the example above, does the 'block_ram' attribute
tells the synthesis tool that we are asking for a dedicated Block RAM
and we do not want it to be implemented using the CLB of the FPGA? So
is using such vendor specific attributes the way by which the synthesis
tool infers what it is meant to synthesize?
A last question: If I want to have more than 16 bit wide data bus, say
a 20 bit bus, do I just have to change it in the generic map for the
data_width and the synthesis tool will infer and create two 4K block
RAMs (in case of spartan II devices) and then cascade them to obtain
the given data width?
Help would be sincerely appreciated.
With best Regards,
Aijaz Baig.
Article: 110741> one solution is to download into the FPGA a very small special core that > does nothing else as force reconfig using the MPU interface. > if the bitstream done with compress enabled then it would be rather small ... and that worked beautifully. Again, thanks.Article: 110742
<enavacchia@virgilio.it> wrote in message news:1161356623.922727.228880@i42g2000cwa.googlegroups.com... > Hi all! > > We've some custom boards with i486 processor, some RAM, some dual port > ram and other stuff (interrupt controller, buffers, I/O transceiver and > so on). I'm investigating the opportunity to replace all of those > discrete ICs with soft/hard IP (cycle accurate), and syntesize the > system in an FPGA (Altera or Xilinx). > > Actually I don't care about costs and efforts that are involved in this > approach. The goal is to get a replacement for that processor without > re-writing the operating system and any other kernel routines. > > Any suggestions? Is it safe to assume that you don't have (and can't buy) the source code to the OS & application? Trying to design a 486 from scratch and match the exact performance of an existing chip is something I don't think even Intel would take on at this point. It can't be the best thing to do. If you don't have source, but if you have rights to disassemble the code, you could fairly easily recreate 'assembly' source. This is something that you can 'farm-out' to someone in India or many other places and get done fairly easily. You basically do a flow control analysis on it and as long as there aren't too many indirect jumps you get a good representation of code. Then you back-annotate it so you can find the important routines. This is the first step in moving it to a Pentium processor that you lower the 'effective' clock rate to get performance something close to what you are running on the 486. good luck -BHArticle: 110743
Hi, I would like to know how many clocks are needed for a fastest ADD instruction of latest Intel CPU. I found there are no descriptions for the latest CPU from their specifications. For Pentium, 386 and 486, the fastest ADD instruction needs 2 clocks based on their specifications. I am curious to want to know if 2 clocks for earlier year CPUs are improved to be 1 clocks for Intel latest CPU chip. Thank you. WengArticle: 110744
Ray Andraka wrote: > Zorjak wrote: > > Ray Andraka wrote: > > > >>Zorjak wrote: > >> > >> > >>>Hi. > >>>I am trying to write generic VHDL code for FIR filter. generic > >>>parametars should be word_length, filter_order. Can anybody help me > >>>how to input filter coeficients. I tought something like, read > >>>coeficitients from file and write it in some LUT table. Could it be > >>>done (or something similar)? > >>> > >>>Thanks for help > >>> > >> > >>If it is synthesizable code, it can't go and read files. What you can > >>do though is have a helper function that converts your coefficient file > >>into a VHDL package containing the coefficient constants. Write that > >>package to a file, and then include that file with the rest of the > >>design when you compile the design. The helper function can be > >>non-synthesizable VHDL, C, Matlab or any other programming language you > >>feel like using. Alternatively, you can cut and paste your coefficients > >>into a VHDL package or directly into a constant array in your code. > >> > >>You can also pass the coefficients into the entity through a generic by > >>defining an integer_array type in a top level package, referring to that > >>package in the library declarations, and then putting the int_array in > >>the generics like this: > >> > >> component matrix > >> generic( > >> coefs: int_array:= ( > >> -62465, -8923, 24026, 39814, 41873, 33635, 18534, > >>0,-18534,-33636,-41873,-39813,-24025, 8925, 62468, > >> 48188, 27536, 10061)); > >> port( > >> clk : in std_logic; > >> > >>Leaving the integer array unconstrained allows you to put in an > >>arbitrary number of coefficients (must be more than 1). > > > > > > Thanks for your answer Ray > > > > I am using Altera Quartus|| software and I've seen there thet some > > *.mif files are using for ram initialization so I thought could I do > > something similar with my FIR filter. Can you help me with that helper > > function if it isnt to much that I am asking. I am VHDL beginer and I > > am not very familiar with it so any lkind of help would used me. > > > > If is to much that I asking, sory. > > Thanks again > > > > The *.MIF files are tie-ins to the altera tools, and have nothing to do > with the VHDL. You don't have the hooks you need to get inside the > place and route tools to bring in your own custom initialization. > > The helper program I talked about just has to write out a text file > containing a VHDL package. The package contains a constant containing > your coefficients. I think I understand you. I'll try to do that Thanks again, RayArticle: 110745
"Weng Tianxiang" <wtxwtx@gmail.com> writes: > I would like to know how many clocks are needed for a fastest ADD > instruction of latest Intel CPU. Look at Intel's latest Optimization Guide for its CPUs. It will tell you. -- Ben Pfaff email: blp@cs.stanford.edu web: http://benpfaff.orgArticle: 110746
Hey everyone, I'm fairly new to VHDL and especially to synthesizing code to program an FPGA. For a class project, I developed a FSM that received its inputs from a ps/2 keyboard. So this project has a keyboard controller (host-receive only), a component to translate the scan-codes into appropriate actions, the FSM being controlled by those actions, and a BCD converter which is to be mapped to a 7 segment display. Anyway, I've got to the point where my code simulates perfectly, but when testing on different FPGA boards, I get mixed results. I recently purchased a Xilinx Spartan-3E Starter Kit with a 500k gate chip. When I program my project into this board, it does nothing but go to the default state. None of the keys that are supposed to be recognized are. We also have a board that our professor loaned to us which is a Xilinx Spartan-3 with a 200k gate chip. On this one, the code functions pretty well and the keys are recognized. My (long winded) question is, is this normal? Should code that simulates and synthesizes fine work on one FPGA and not at all on another? thanks JayArticle: 110747
Ben Pfaff wrote: > Look at Intel's latest Optimization Guide for its CPUs. It will > tell you. Certainly look at the current Itanium products too. The more interesting question for some time, with multi-issue architectures, is how MANY add's can you do in a clock cycle :)Article: 110748
shadfc wrote: > Hey everyone, I'm fairly new to VHDL and especially to synthesizing > code to program an FPGA. For a class project, I developed a FSM that > received its inputs from a ps/2 keyboard. So this project has a > keyboard controller (host-receive only), a component to translate the > scan-codes into appropriate actions, the FSM being controlled by those > actions, and a BCD converter which is to be mapped to a 7 segment > display. > > Anyway, I've got to the point where my code simulates perfectly, but > when testing on different FPGA boards, I get mixed results. I recently > purchased a Xilinx Spartan-3E Starter Kit with a 500k gate chip. When > I program my project into this board, it does nothing but go to the > default state. None of the keys that are supposed to be recognized > are. We also have a board that our professor loaned to us which is a > Xilinx Spartan-3 with a 200k gate chip. On this one, the code > functions pretty well and the keys are recognized. > > My (long winded) question is, is this normal? Should code that > simulates and synthesizes fine work on one FPGA and not at all on > another? > > thanks > Jay > I'm by no means an expert, I've only played with the Spartan-3e starter board and no other, and I've never moved vhdl from one fpga to another. But my gut reaction is you haven't setup the constraints properly, your ps/2 connector probably isn't feeding the data in to your state machine correctly. You just need to work the problem, find out where things go wrong. Keyboard frequencies are trivial for any fpga to handle, I'd think. Maybe your vhdl is right on the edge -- you could have an iffy construct that happens to work sometimes and not others. Consider the case that fails reliably as a godsend and use it to work the problem and maybe learn something about what not to do in the future. Good luck. -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 110749
The most likely problem provided you have set up period constraints correctly is probably not dealing with what are esssentially asynchronous inputs properly. The timing out your keyboard is unlikely to bear much relationship to your internal clock. Also keyboards tend have open collector/drain driving which makes edges fairly slow and makes timing even more variable. Your design needs to account for those ensuring the data capture point you use is stable. Other things to check are (1) That you do have a pullup on the lines in both cases, either phyiscal resistor or FPGA internal, and finally the value of those pullups in discrete components. (2) Check your keyboard does not need 5V CMOS levels. Occasionally they do and get upset by 3.3V driving or limiting by protection diodes on the FPGA. Small variations in the 3.3V supply might make one board work and the other not if it is the margin levels zone. John Adair Enterpoint Ltd. - Home of Tarfessock1. The Student Development Board shadfc wrote: > Hey everyone, I'm fairly new to VHDL and especially to synthesizing > code to program an FPGA. For a class project, I developed a FSM that > received its inputs from a ps/2 keyboard. So this project has a > keyboard controller (host-receive only), a component to translate the > scan-codes into appropriate actions, the FSM being controlled by those > actions, and a BCD converter which is to be mapped to a 7 segment > display. > > Anyway, I've got to the point where my code simulates perfectly, but > when testing on different FPGA boards, I get mixed results. I recently > purchased a Xilinx Spartan-3E Starter Kit with a 500k gate chip. When > I program my project into this board, it does nothing but go to the > default state. None of the keys that are supposed to be recognized > are. We also have a board that our professor loaned to us which is a > Xilinx Spartan-3 with a 200k gate chip. On this one, the code > functions pretty well and the keys are recognized. > > My (long winded) question is, is this normal? Should code that > simulates and synthesizes fine work on one FPGA and not at all on > another? > > thanks > Jay
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