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Deja Vu all over again... ;) PeteS wrote: > Is it just me, or are we having a sense of deja vu? > > Cheers > > PeteSArticle: 110851
IIRC, it's the mapper that actually instantiates the block RAM. If in doubt, call up your design in the 'fpga editor' (view/edit routed design) and look for wires connected to the RAM blocks. GH Guy_Sweden wrote: > > But i wonder if I have been able to acheive my objective of realising > ROMs using block RAM as the synthesis report never shows anything that > any block RAM was ever used. >Article: 110852
Alan Nishioka wrote: > Stevo_V2pro wrote: > > I'm having a problem when Data2Mem runs and was wondering if > > someone could help me out. I have a simple dual PPC system, with both > > procs on the same plb bus. I also have two brams and the ddr memory on > > the same plb bus as the PPC cores as well. I'm trying to run a > > separate program on each PPC core (i.e. I am not trying to have the > > procs communicate with eachother through a shared memory). If I create > > a SW project and execute it on PPC405_0, the design sysnthesizes > > without any problems and executes the code correctly. However, when I > > create a second SW project and tell it to execute on PPC405_1, I get > > the following error message when data2mem runs when I try to download > > it to the board: > > > > "ADDRESS_SPACE or ADDRESS_MAP tag name 'ppc405_1' was not found. Some > > data may have not been translated." > > The last time I tried this it was simply a matter of specifying the > software under the applications tab in XPS. Is this where you are > making changes? > > Is "Mark to Initialize BRAMs" set on both projects? > > I also started with a dual ppc example project from Xilinx, so it might > be a good idea to download that from the Xilinx site. > > Alan Nishioka Thanks for the quick reply Alan. Yes, I was doing this in the apps tab for XPS and mark to intialize brams was checked. For some reason I had to manually go in an edit the main .bmm file, probably because I manually added the second PPC core and did not use an example project from Xilinx. Thanks again. SteveArticle: 110853
Chris schrieb: > I've written Verilog for over 10 years and the design for the logic portion > is already done. However this is the first time using a soft core CPU. > Basically this is a backplane bus interface. Address decode and 32 bit > porting. But I need RAM for a fast buffer and also a little CPU for > converting serial I2C DACs and ADCs into parallel data. So a little > embedded CPU with I2C core would probably do it. Perhaps SPI so I can > update calibration constants in config Flash. > > PicoBlaze seems very easy to hook your own logic to. Nios seems much more > involved since you have to go through the SOPC arch. It also appears the > size of the gates will be 2X higher using Nios than PicoBlaze. The chip > size could be twice the price. > > Chris. if you only need i2c and spi, then any small cpu would do, and there is no need for the i2c or spi to be present in hardware, software bitbang is almost always as efficient AnttiArticle: 110854
Hi I am writing a memory controller for a zbt sram. Do I need to be concerned with the setup times. What I mean by this is do I need to arange my signals realtive to the clock so that the time is not violated. The only simple way I can see of doing this is to clock off the neg edge of the clock and then read on the pos edge. Thanks JArticle: 110855
Mack, Does your board have only one memory chip? If there are 2 chips then your memory bus width should probably be 32 bits. I doubt the MPMC2 was ever tested with 16-bit memory. /MikhailArticle: 110856
WinDriver is installed and I have verified that the driver files are there, I even updated to the latest version, 8.1.0 from Jungo. I have tried it with my parallel port set to ECP and ECP+EPP and no joy!Article: 110857
Avnet is also now selling V5 eval kit AES-XLX-V5LX-EVL50 http://www.em.avnet.com/ctf_shared/evk/df2df2usa/xlx_v5_lx_dev-pb092506.pdf priced at $895 it has far less features than ML501, but maybe more user io in the high density P240 extension connector Antti http://groups.google.com/group/virtex5Article: 110858
maxascent wrote:
> Hi
>
> I am writing a memory controller for a zbt sram. Do I need to be concerned
> with the setup times.
<sarcastic_mode>
It depends ... Are you concerned by your design actually working ?
Of course you need to be concerned by setup times ... and hold times (if
any) ... What you were just thinking these were pretty numbers that just
looks good on the datasheet ?
</sarcastic_mode>
Sylvain
Article: 110859ghelbig@lycos.com wrote: > Deja Vu all over again... > > ;) > > PeteS wrote: > >>Is it just me, or are we having a sense of deja vu? >> >>Cheers >> >>PeteS > > Ahh - the immortal Yogi Berra speaks! ;)Article: 110860
Sylvain Munaut wrote: > maxascent wrote: > >>Hi >> >>I am writing a memory controller for a zbt sram. Do I need to be concerned >>with the setup times. > > > <sarcastic_mode> > It depends ... Are you concerned by your design actually working ? > > Of course you need to be concerned by setup times ... and hold times (if > any) ... What you were just thinking these were pretty numbers that just > looks good on the datasheet ? > </sarcastic_mode> > > > Sylvain Hmmm.. Just out of interest - do you understand the various timings in the datasheet? There's no shame in _not_ knowing - we all didn't know at one time. As Sylvain has imputed (in an inimitable way) one must understand what the timing requirements *mean* if one is going to design around them. Setup time, hold time, group jitter, clock uncertainty (for synchronous types) - all these things are specified not because it's 'cool', but because they are fundamental parameters to be met if you want the thing to operate. Please espouse your design (or desired design) more fully. Cheers PeteSArticle: 110861
jbnote wrote: > Hello, > > I came accross what I think is a bug in virtex4 debug bitstream > generation. In this mode, the two pad frames (82 bytes) which are > needed at the end of each row configuration are written *after* the > LOUT write of the FAR, while they are expected to take place in the > previous FDRI write. > > I don't know if this really is a bug or some specific quirk in virtex4 > bitstream handling -- I don't have a virtex4 at hand, so I cannot > really test whether the hardware is happy with this or not. > > JB if you dont have v4 at hand, but you are stumbling on bitstream debug issues - what are you doing ?! AnttiArticle: 110862
Hi Mack, What about: PARAMETER C_PLB_0_PLB_NUM_MASTERS = 2 - is that correct. Mine GSRD2 desing (MPMC2 based) works fine on Virtex-4 FX12 Mini Module and it basically the same platform. Use the MPMC2 GUI to generate custom MPMC2 core!! Guru Mack wrote: > Hi all, > > I'm working on a Virtex-4 FX12LC Design with PPC405 Core, SDRAM and > Multiport Memory Controller 2 (MPMC2 release 2006/08/31). The Memec > Development Board contains the Infineon DDR SDRAM HYB25D512160BC-6 (64 > Mbyte, Databus 16 bit). I started the Design with BSB and > OPB_DDR_CNTLR, then replaced the DDR_CNTLR with the MPMC2 Core of from > "ml403_ddr_p_100mhz" and changed the Memory Width to 16 bit, Pin > Constraints etc. The MPMC2 is configured to hold only one PLB > connection, the remaining 7 ports are set to "None". > After the project was built, I tried to access the SDRAM Memory via a > simple C Application or XMD. The problem now is, that the memory > content seems to be mirrored every 32 bit. For example, when I write at > address 0x00000000 a 32 bit value 0xA5A5A5A5, the same value appears > at address 0x00000008. The same behavior between addresses 0x00000004 > and 0x0000000C. > > It looks like: > 0x00000000: 0xA5A5A5A5 0x00000000 0xA5A5A5A5 0x00000000 > 0x00000010: 0x00000000 0xDEADBEEF 0x00000000 0xDEADBEEF > 0x00000020: 0x00001111 0x00002222 0x00001111 0x00002222 > 0x00000030: 0x00000000 0x00000000 0x00000000 0x00000000 > > The MPMC Part in system.mhs: > > BEGIN mpmc2_ddr_p_100mhz_x16_hyb25d512160bc_6 > PARAMETER INSTANCE = mpmc2_ddr_p_100mhz_x16_hyb25d512160bc_6_0 > PARAMETER HW_VER = 1.04.a > PARAMETER C_PLB_0_BASEADDR = 0x0000_0000 > PARAMETER C_PLB_0_HIGHADDR = 0x03ff_ffff > PARAMETER C_PLB_0_PLB_NUM_MASTERS = 2 > PARAMETER C_PLB_0_PLB_MID_WIDTH = 1 > PARAMETER C_PLB_0_PI_TO_MPMC2_CLK_RATIO = 1 > PARAMETER C_PLB_0_MPMC2_TO_PI_CLK_RATIO = 1 > PARAMETER C_PLB_0_BRIDGE_TO_PI_CLK_RATIO = 1 > BUS_INTERFACE PLB_S_0 = plb > PORT MPMC2_0_Rst = sys_bus_reset > PORT PLB_0_PLB_SlClk = CLK_100MHz > PORT MPMC2_0_Clk0_2X = net_gnd > PORT MPMC2_Slowest_Clk = CLK_100MHz > PORT MPMC2_0_Clk0 = CLK_100MHz > PORT MPMC2_0_Clk90 = CLK_100MHz_90 > PORT MPMC2_0_Clk_Cal = CLK_100MHz > PORT MPMC2_0_Clk_200MHz = CLK_200MHz > PORT MPMC2_0_Clk_Mem = CLK_100MHz_90 > PORT MPMC2_0_DDR_Clk_O = DDR_Clk > PORT MPMC2_0_DDR_Clk_n_O = DDR_Clkn > PORT MPMC2_0_DDR_CE_O = DDR_CKE > PORT MPMC2_0_DDR_BankAddr_O = DDR_BA > PORT MPMC2_0_DDR_Addr_O = DDR_Addr > PORT MPMC2_0_DDR_CS_n_O = DDR_CSn > PORT MPMC2_0_DDR_RAS_n_O = DDR_RASn > PORT MPMC2_0_DDR_CAS_n_O = DDR_CASn > PORT MPMC2_0_DDR_WE_n_O = DDR_WEn > PORT MPMC2_0_DDR_DQ = DDR_DQ > PORT MPMC2_0_DDR_DQS = DDR_DQS > PORT MPMC2_0_DDR_DM = DDR_DM > END > > The MPMC parameters are equal to the reference design > "v4fx12lc_ddr_idpp_100mhz", except the parameters which setup the > number of master/slaves, and of course the datawidth of memory. I > checked the pin constraints, they are ok. > So where could be the mistake? Are there any MPMC Parameters which I > forgot to set correctly? Do I need to modify PLB Settings? > > Are there any suggestions or hints? > Thanks in advance. > MackArticle: 110863
Hi all, Did anyone try to use the Spartan3 Starter Kit (S3ESK) as a USB JTAG programmer? I want to connect the Virtex4 MiniModule (2.5V JTAG) to the 3.3V S3ESK JTAG port. I tried to with some resistor dividers to accomodate voltage (100 & 330ohm) and TDO & TDI swapped, but the connection was not very sucesfull. Any ideas? GuruArticle: 110864
I know the documentation says I can't do it, however looking at the files generated by the Chipscope Pro Core Generator, it seems that it might in fact be possible... Has anyone tried? My problem is that all the MGT clocks on the board have to be programmed by PPC before they can be used for MGT testing.... Thanks, /MikhailArticle: 110865
"Chris" <nospam@nospam.com> wrote: >I am evaluating using the Altera Cyclone with Quartus SOPC vs. Xilinx >Spartan3E and PicoBlaze. I need a soft core processor and I think PicoBlaze >would be enough. SOPC and Nios-II is very powerful but the learning curve >looks like a potential nightmare to me. In order to use SOPC I might have >to get involved writing custom components to do the job and then one has to >master the Avalon interface. That looks like a lot of potential debugging >time. > >The Xilinx solution seems more direct, and under my control, since PicoBlaze >is stand alone and does not depend on so many bus interrelated components >and SOPC infrastructure. Easier and quicker to write direct interfaces. >Nios seems to need much more of the SOPC (RAM,ROM,Avalon,etc) around it to >work. > >Also, it seems like the Nios/SOPC solution is likely to require far more >gates than a Xilinx/PicoBlaze implementation. > >I would be curious to know any of your experiences with SOPC/Nios-II. I >have very limited R&D time for this project. If time is limited, go for the Picoblaze. Even though it needs to be programmed in assembly. The assembly language it uses is very straightforward and easy to learn. Be aware though that the design around a Picoblaze may not meet timing when a lot of datasources are connected to it and / or the Picoblaze is running at high clock speeds. You may need one or more extra registers to split paths (this is explained in the Picoblaze documentation). -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 110866
Hi Chris, you can also take a look at our ERIC5. It is more powerful than Picoblaze (esp. size of code-space) at about the same resource-usage. And it is vendor-indepent, so you do not have to base your FPGA-decision on the processer-choice. For larger projects (with sufficient code-ROM) there is also a C-compiler available. If you want something for free, maybe also Lattice Mico8 can do the job. Regards, Thomas www.entner-electronics.com "Chris" <nospam@nospam.com> schrieb im Newsbeitrag news:ysmdnTmSee0P56DYnZ2dnUVZ_vOdnZ2d@comcast.com... >I am evaluating using the Altera Cyclone with Quartus SOPC vs. Xilinx > Spartan3E and PicoBlaze. I need a soft core processor and I think > PicoBlaze > would be enough. SOPC and Nios-II is very powerful but the learning curve > looks like a potential nightmare to me. In order to use SOPC I might have > to get involved writing custom components to do the job and then one has > to > master the Avalon interface. That looks like a lot of potential debugging > time. > > The Xilinx solution seems more direct, and under my control, since > PicoBlaze > is stand alone and does not depend on so many bus interrelated components > and SOPC infrastructure. Easier and quicker to write direct interfaces. > Nios seems to need much more of the SOPC (RAM,ROM,Avalon,etc) around it to > work. > > Also, it seems like the Nios/SOPC solution is likely to require far more > gates than a Xilinx/PicoBlaze implementation. > > I would be curious to know any of your experiences with SOPC/Nios-II. I > have very limited R&D time for this project. > > Thanks, Chris. > >Article: 110867
Francesco wrote: > Yestarday I manage to compile the kernel! > it is working now!!! > As first attempt I don't have the 10/100 MAC yet. > My next step will be to add a 10/100 MAC and try some network > applications. Um, do you think maybe you can share exactly what you did to fix the problem? :) -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 110868
Hi All, I've been trying to work with a Xilinx II Virtex Pro board and its SysAce controller. I've read many papers and related topics in this group, but I found no solutions as such. I need to use the CF card for simple data storage, and not to boot the board or anything else. One of the main questions I have is what kind of partitioning I need to for this. I used the mkdos utility to format the card to FAT 16 with 1 reserved sector. When I do a Sys_fopen, the operation fails. I can initialize the card, set and release a lock on it. Can I do simple file I/O without worrying about .ACE and .SYS files? Can I use a complete FAT parition and not have an etc partition? There was one post in this group where the user has asked a similar question and it was pointed out that his MSS and MHS files were incomplete. My files appear complete. I will post them if needed. I'd appreciate any suggestions that will put me in the right track... Thanks in advance PrithviArticle: 110869
Thomas Entner wrote: > If you want something for free, maybe also > Lattice Mico8 can do the job. fyi, the LatticeMico8 is free and open source: http://www.latticesemi.com/products/intellectualproperty/referencedesigns/8bitmicrocontrollermico8.cfm if you'd like a free and open source 32-bit soft processor, you might check out the LatticeMico32: http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/index.cfm Bart Borosky, LatticeArticle: 110870
I have just installed ISE on my laptop and it is connectiong to the board perfectly! Thankfully it means the cable and board are fine, it's obviously a software issue that I can now fix at my leisure! Thanks for you help!Article: 110871
We are still shipping them at a good rate, obviously for production and not for new designs. Considering the price, I don't assume they end up in desk drawers. The absolute top-of-the-line part always finds many customers. Might include all the ones that were dying for an even bigger part... Peter Alfke On Oct 23, 8:14 am, tmo...@cape-source.com (Tyler ) wrote: > Does anyone know is this big FPGA is still being used in production? > Thank you!Article: 110872
Hi,
I have a problem with textio library while compiling a file using
ModelSim.
I have use the library:
use std.textio.all; -- for Read(), Write()
It had worked before and now I don't know why it generates an error:
-- * Error: $MODEL_TECH/../vhdl_src/std/textio.vhd(18): (vcom-1136)
Unknown identifier "read_mode".
-- ** Error: $MODEL_TECH/../vhdl_src/std/textio.vhd(18): (vcom-1112)
FILE declaration was written using 1076-1993 syntax. Recompile using
the -93 option.
This is the line with noted error:
-- changed for vhdl92 syntax:
file input : TEXT open read_mode is "STD_INPUT"; -- line
18
I checked related *.mpf file and there is a line:
[vcom]
; Turn on VHDL-1993 as the default. Normally is off.
VHDL93 = 1
So it is assumed that VHDL93 is specified. What should I do now to
correct the error?
Thank you.
Weng
Article: 110873
In the following module,
module mult (output reg[7:0] z, input [3:0] a);
always @* begin
z = a*a;
end
endmodule
ModelSim returns 225 when a is 15, but the Xilinx implementation on a
Spartan3 returns a 1 (-1 * -1). Does anybody know why Xilinx ISE is
interpreting the four bit numbers as signed numbers rather than unsigned?
-Gary
Article: 110874
Hi All,
Does anyone have any experience with getting their bit order reversed
in Xilinx post-translate simulation? I am using Xilinx ISE ver 8.2.03i
and ModelSim III XE 6.1e starter edition, and this mysteriously started
happening to me last week when I never had a problem with this before.
I have reinstalled both programs and have reverted to testing only what
Xilinx gives me, and I still get the problem. I generated
user_logic.vhd by following the directions in the
EDK_82_PPC_Tutorial.pdf for the ML403 board; see
http://www.xilinx.com/support/techsup/tutorials/edk_tutorials.htm --
"EDK PowerPC Tutorial using the ML403 Development Kit 8.2"
(EDK_82_PPC_Tutorial.pdf). Then I took it and put it in a separate new
ISE project in order to simulate it. I didn't change any synthesize or
translate options. I made sure that my testbench has sufficient input
setup time and output valid delay according to the timing report (9 ns
each, using a clock period of 20 ns). I have reduced the problem to
just trying to write slv_reg0 and not see the contents backwards
post-translate. I set Bus2IP_BE to F to select all registers,
Bus2IP_Data to my test data of 0x01020304 and Bus2IP_WrCE to 8 in order
to write slv_reg0. This succeeds in behavioral simulation, but in
post-translate simulation, what I see for slv_reg0 is 0x20C04080, which
is just the bits reversed low-order to high-order. I opened a webcase
with Xilinx, but I don't know if they'll be able to reproduce the
problem.
With fresh installs of ISE and ModelSim, no changes to Synthesize or
Translate options, no touching of any ModelSim menu options, and VHDL
straight out of Xilinx's own user_logic from the Create Peripheral
Wizard that always worked before (and works in Behavioral sim), what is
left? What could I have set generally on my computer that could be
causing this? Could there be some Translate option that I idiotically
set and didn't remember that I set?
It must be a problem with how ISE creates models for simulation, or in
the simulator, since I can put my built project in the ML403 board and
write and read the slv_regs correctly following the tutorial, over
RS232. However, my core doesn't seem to be giving the correct output,
so I need to simulate, and therefore I need a reliable simulation
process.
Thanks in advance,
-James
Here's user_logic.vhd as I am simulating it (straight from the Create
Peripheral Wizard, with only the two "library proc_common_v2_00_a"
lines commented-out so that the syntax check will succeed -- this
always worked before):
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Tue Oct 03 15:53:39 2006 (by Create and Import
Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with
Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--library proc_common_v2_00_a;
--use proc_common_v2_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DWIDTH -- User logic data bus width
-- C_NUM_CE -- User logic chip enable bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus for user logic
-- Bus2IP_BE -- Bus to IP byte enables for user
logic
-- Bus2IP_RdCE -- Bus to IP read chip enable for
user logic
-- Bus2IP_WrCE -- Bus to IP write chip enable for
user logic
-- IP2Bus_Data -- IP to Bus data bus for user logic
-- IP2Bus_Ack -- IP to Bus acknowledgement
-- IP2Bus_Retry -- IP to Bus retry response
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_ToutSup -- IP to Bus timeout suppress
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_DWIDTH : integer := 32;
C_NUM_CE : integer := 4
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to
C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to
C_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to
C_NUM_CE-1);
Bus2IP_WrCE : in std_logic_vector(0 to
C_NUM_CE-1);
IP2Bus_Data : out std_logic_vector(0 to
C_DWIDTH-1);
IP2Bus_Ack : out std_logic;
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_reg3 : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_reg_write_select : std_logic_vector(0 to 3);
signal slv_reg_read_select : std_logic_vector(0 to 3);
signal slv_ip2bus_data : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible
registers
--
-- Note:
-- The example code presented here is to show you one way of
reading/writing
-- software accessible registers implemented in the user logic slave
model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to
correspond
-- to one software accessible register by the top level template. For
example,
-- if you have four 32 bit software accessible registers in the user
logic, you
-- are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE or Memory Mapped
-- Bus2IP_RdCE Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_select <= Bus2IP_WrCE(0 to 3);
slv_reg_read_select <= Bus2IP_RdCE(0 to 3);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or
Bus2IP_WrCE(2) or Bus2IP_WrCE(3);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or
Bus2IP_RdCE(2) or Bus2IP_RdCE(3);
-- implement slave model register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
case slv_reg_write_select is
when "1000" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <=
Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0100" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8 to byte_index*8+7) <=
Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0010" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <=
Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0001" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8 to byte_index*8+7) <=
Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model register read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_select, slv_reg0,
slv_reg1, slv_reg2, slv_reg3 ) is
begin
case slv_reg_read_select is
when "1000" => slv_ip2bus_data <= slv_reg0;
when "0100" => slv_ip2bus_data <= slv_reg1;
when "0010" => slv_ip2bus_data <= slv_reg2;
when "0001" => slv_ip2bus_data <= slv_reg3;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data;
IP2Bus_Ack <= slv_write_ack or slv_read_ack;
IP2Bus_Error <= '0';
IP2Bus_Retry <= '0';
IP2Bus_ToutSup <= '0';
end IMP;
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