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Davy wrote: > Hi all, > > IMHO, there is something compare the golden output and DUT output in > testbench (I call it Checker). But in verification book, there is both > Scoreboard and Checker. Are they similar? > > Please recommend some reading on it.Thanks! > > Best regards, > Davy Davy, A checker is used to check whether a given transaction has taken place correctly . This may include data correctness and correct signalling order. A Scoreboard is used to keep track of how many transactions were initiated, how many finished and how many are pending and wether a given transaction passed or failed. Regards -- We are now hiring in India check our requirements at http://edaindia.com/cgi-bin/forms/formhandler/show_job.pl?job=7Article: 110601
samiam wrote:
> Whats the cheapest board to study VHDL on?
To learn vhdl, all you need is a simulator
to verify your uut and testbench code
and quartus or ise to view the rtl schematic.
A board is of little value until
the code is complete and tested.
-- Mike Treseler
Article: 110602Thanks John. Ill take a look John Adair wrote: > I'm sure you have seen it on Ebay but have a look at our Raggedstone1. > Ebay wise look for the non-EEC price if you are in the US. Similar > pricing on our own website. It just about gets under you $100 mark > depending on the current exchange rate. For something much cheaper you > probably talking about a CPLD board. > > John Adair > Enterpoint Ltd. >Article: 110603
Mike, I felt that having an FPGA board, where I can download the code, and do things ... "see" the results for myself, would only serve to reinforce what I am reading A simulator is one thing ... "seeing" the results on bare metal is another Mike Treseler wrote: > samiam wrote: > >> Whats the cheapest board to study VHDL on? > > To learn vhdl, all you need is a simulator > to verify your uut and testbench code > and quartus or ise to view the rtl schematic. > > A board is of little value until > the code is complete and tested. > > -- Mike TreselerArticle: 110604
Unless you are trying to interface to something else, and need to prove that what you designed can talk to it, a simulator will "show" you much more than you will ever see from an FPGA board. I'm not saying there is anything wrong with the satisfaction that is gained from seeing your project "working in real life", but that has nothing to do with any reinforcement of knowledge gained. I should add that the insights gained through thorough simulation (both rtl and gate-level, post-route timing simulations), synthesis, place & route, and static timing analysis will far exceed those gained from "seeing" it work. But seeing it work will probably provide more satisfaction than all those activities. Andy samiam wrote: > Mike, I felt that having an FPGA board, where I can download the code, > and do things ... "see" the results for myself, would only serve to > reinforce what I am reading > > A simulator is one thing ... "seeing" the results on bare metal is > another > > > Mike Treseler wrote: > > samiam wrote: > > > >> Whats the cheapest board to study VHDL on? > > > > To learn vhdl, all you need is a simulator > > to verify your uut and testbench code > > and quartus or ise to view the rtl schematic. > > > > A board is of little value until > > the code is complete and tested. > > > > -- Mike TreselerArticle: 110605
My research group is building a mezzanine card that contains a lot of critical nets. We have four 500MHz DSPs and a V2P FPGA all connected together in a network. Each DSP also has access to SDRAM. Can anyone suggest a PCB design house that would route the board for us, someone used to dealing with signal integrity of many high-speed digital signals in smaller form factors? If at all possible, we would prefer someone in Illinois or a consultant that could come to Illinois. ---Matthew HicksArticle: 110606
bart wrote: > Lattice is holding a webcast tomorrow Wednesday, October 18, "Embedded > Design with LatticeMico32 Open, Free 32-bit Soft Processor." I couldn't turn-in, but I'd like to hear comments from people who did! It sounds interesting. EricArticle: 110607
I'm trying to use the Opencores I2S master logic as the driver for my test platform. The core came configured with SCK = 2.77 MHz and WS(left/right clock)= 69.44 KHz. I would like to be able to reconfigure the core to generate SCK=3.07MHz and WS=48 KHz. I played around with the conf variable but could not get the ratio I'm looking for. Could I get some help? ThanksArticle: 110608
"Mak" <makarand.deshmukh@gmail.com> writes: > what is netgen software? Is it available with Xilinx? It's part of the ISE package. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 110609
Davy wrote: > Hi all, > > IMHO, there is something compare the golden output and DUT output in > testbench (I call it Checker). But in verification book, there is both > Scoreboard and Checker. Are they similar? > > Please recommend some reading on it.Thanks! > > Best regards, > Davy IMO, There is lack for clear definition of verification terms. For me, both of them are verification components which check specific design properties for all simulation times and all testcases. They correspond to the "safety" properties in formal verification: during system execution, something wrong will never happen. IN AVM Cookbook, there is definition for the scoreboard as a transaction-level checking component. There are no defition of checker in the cookbook, yet there is an example of so-called "Assertion-based checker". From this example, we can find out that assertion-based checker checks lower-level interface properties. Also, it has to be implemented using assertions, but implementation details are not important here. So, to find the differences between scoreboard and checker we have to understand the meaning of transaction: "The transaction is quantum of activity that occurs in design bounded by time" "A transaction is a single transfer of control or data between 2 entities" "A transaction is a function call" First definition is too broad. By this definition, scoreboard is the same as assertion-based checker, since both of them deal with quantums of design activity bounded by time. Second definition is different from the first one and too restrictive. What does it mean "single transfer"? Why between only two entities? Third definition is the one I cannot understand. Does it mean that "transaction-based" component must contain functions? Regards, -AlexArticle: 110610
>On a sunny day (Wed, 18 Oct 2006 11:46:44 -0500) it happened "cutemonster" ><ckh827@hotmail.com> wrote in <9qKdnRAOY6vpx6vYRVn_vA@giganews.com>: > >> >>Hi all, I'm new to the Xilinx FPGA FIR filter and would like to ask forhelp. >>I have two (X and Y) channels and their frequency is about 10Mhz. >>Using 2 14-bits ADC with sampling 50Mhz. >>I have my Xilinx clock about 50Mhz. >> >>How many taps for each channel is necessary for doing a cutoff frequencyof 10MHz? >> >>How many bits should the coefficients length is? how to do a optimaldesign? >> >>I have to use FIR because my moving avaraging doesn't solve the problem. >> >>What other terms I need to consider? > >This is free: > http://www.mediatronix.com/FIRTool.htm Thanks, and I used this tool before. What I don't understand is the minimum taps that I need. Is the sampling rate ok? is the fpga clock ok? I have many fundamental questions that I could find from my textbooks. thank you, Kenny,Article: 110611
On a sunny day (Wed, 18 Oct 2006 14:09:06 -0500) it happened "cutemonster" <ckh827@hotmail.com> wrote in <sPmdnTlNNfBP5qvY4p2dnA@giganews.com>: >>On a sunny day (Wed, 18 Oct 2006 11:46:44 -0500) it happened >"cutemonster" >><ckh827@hotmail.com> wrote in <9qKdnRAOY6vpx6vYRVn_vA@giganews.com>: >> >>> >>>Hi all, I'm new to the Xilinx FPGA FIR filter and would like to ask >forhelp. >>>I have two (X and Y) channels and their frequency is about 10Mhz. >>>Using 2 14-bits ADC with sampling 50Mhz. >>>I have my Xilinx clock about 50Mhz. >>> >>>How many taps for each channel is necessary for doing a cutoff >frequencyof 10MHz? >>> >>>How many bits should the coefficients length is? how to do a >optimaldesign? >>> >>>I have to use FIR because my moving avaraging doesn't solve the >problem. >>> >>>What other terms I need to consider? >> >>This is free: >> http://www.mediatronix.com/FIRTool.htm > >Thanks, and I used this tool before. What I don't understand is the >minimum taps that I need. Is the sampling rate ok? is the fpga clock ok? >I have many fundamental questions that I could find from my textbooks. > >thank you, >Kenny, Well, I am no filter expert but these parameters you mention, and the type of filter, depend on how steep the filter needs to be, and how much ripple is allowed, the phase response... So I cannot answer that with numbers. Also the speed of course, more speed more hardware basically.Article: 110612
cutemonster wrote: > Hi all, I'm new to the Xilinx FPGA FIR filter and would like to ask for > help. > I have two (X and Y) channels and their frequency is about 10Mhz. > Using 2 14-bits ADC with sampling 50Mhz. > I have my Xilinx clock about 50Mhz. > > How many taps for each channel is necessary for doing a cutoff frequency > of 10MHz? > > How many bits should the coefficients length is? how to do a optimal > design? > > I have to use FIR because my moving avaraging doesn't solve the problem. > > What other terms I need to consider? > > is my Spartan 3 xcs3s400 enough? 16 multipliers. > is that 1 tap require 1 multiplier. If so, I would get a virtex II pro. > board. > > At last, I want to say thank you for looking at my thread and I hope you > can answer my questions. > > thanks again, > Kenny, > The number of taps required depends on how sharp the transitions are in your filter characteristic, how much passband ripple you are willing to accept and how much stopband attenuation you need. You will need a filter design tool to design the filter (can be done by hand, but is extremely tedious), so when you get your hands on that tool you can play with the parameters to find a decent compromise. As far as number of bits in the coefficient goes, that depends mostly on the amount of stopband attenuation you desire. Quantizing the coefficients changes the filter characteristic, and generally speaking the effect is manifested as peaks in your stopband. A good rule of thumb for the number of coefficient bits needed is you get about 5dB better stopband attenuation for each additional coefficient bit. Whether a particular FPGA is satisfactory depends on your sample rate, the clock rate at which you can comfortably clock the FPGA (depends on your design skills), and the number of taps needed to realize the filter you desire. That said, the Spartan3 XCS3S400 should be fine as long as your filter is modest. You may have to pull some tricks if your filter turns out to be more than 16 taps such as symmetry folding or time multiplexing the multipliers to handle more than one tap per sample (this is where working with a multiplied clock really helps out).Article: 110613
luca_grossi@hotmail.com wrote: > Hi everyone, > I'm currently using a vitex-II pro FPGA, I've implemented an NCO > frequency generator, which is supplied with a 64bit init & delta phase > value. I'm currently using a local oscillator to clock the NCO ( must > use specific local oscillator) but this does contain a margin of offset > and drift thus influencing output frequency of NCO. A compensation > circuit which includes another stable clock is used to correct the > drift and offset by using a frequency counter on both clocks then > calculating appropriate delta phase to compensate. My problem is that > my equation to calculate adjusted delta which requires a 64 bit > division > > Delta2 = (count2/count1) * delta1 > > Delta2 = new delta phase with correction > Count2 = frequency counter for Local Oscillator > Count1 = frequency counter for external Oscillator > Delta1 = Original calculated delta phase to product output frequency > > What would be the most appropriate way of doing this calculation, > especially with the division? also time constraints, everyone 1.6ms > roughly this will occur. > Maybe this could be done differently? Ideas I've been thinking about > are on the lines of, Maybe reduces the counting resolution ? use > internal PPC (CPU) > > Any advice would be appreciated :) > Cheers Luca > Division is the brute force way of addressing that, but is not really a good approach in most cases. When dealing with two counts like that, you can count the number of clocks of the numerator clock per cycle (or multiple cycles) of the denominator clock to determine the ratio without performing an explicit division. In fact, you don't even need a frequency counter, as that is what you are constructing here anyway. The more cycles of clk1 you accumulate clk2 over, the greater the precision of your result. Basically you have a counter that counts up with each cycle of clk2 that is read and reset every N cycles of clk1. Multiply that by your delta constant to get the adjustment. There are some more advanced tricks to determine fractional clocks in order to reduce the accumulation time, but that is beyond the scope of a usenet post I think. For this type of application, it is more common to use a feedback loop and a measured parameter such as residual frequency after the mixer to nudge the DDS increment up or down. Look at phase lock loops for this.Article: 110614
>cutemonster wrote: >> Hi all, I'm new to the Xilinx FPGA FIR filter and would like to ask for >> help. >> I have two (X and Y) channels and their frequency is about 10Mhz. >> Using 2 14-bits ADC with sampling 50Mhz. >> I have my Xilinx clock about 50Mhz. >> >> How many taps for each channel is necessary for doing a cutoff frequency >> of 10MHz? >> >> How many bits should the coefficients length is? how to do a optimal >> design? >> >> I have to use FIR because my moving avaraging doesn't solve the problem. >> >> What other terms I need to consider? >> >> is my Spartan 3 xcs3s400 enough? 16 multipliers. >> is that 1 tap require 1 multiplier. If so, I would get a virtex II pro. >> board. >> >> At last, I want to say thank you for looking at my thread and I hope you >> can answer my questions. >> >> thanks again, >> Kenny, >> > >The number of taps required depends on how sharp the transitions are in >your filter characteristic, how much passband ripple you are willing to >accept and how much stopband attenuation you need. You will need a >filter design tool to design the filter (can be done by hand, but is >extremely tedious), so when you get your hands on that tool you can play >with the parameters to find a decent compromise. > >As far as number of bits in the coefficient goes, that depends mostly on >the amount of stopband attenuation you desire. Quantizing the >coefficients changes the filter characteristic, and generally speaking >the effect is manifested as peaks in your stopband. A good rule of >thumb for the number of coefficient bits needed is you get about 5dB >better stopband attenuation for each additional coefficient bit. > >Whether a particular FPGA is satisfactory depends on your sample rate, >the clock rate at which you can comfortably clock the FPGA (depends on >your design skills), and the number of taps needed to realize the filter >you desire. That said, the Spartan3 XCS3S400 should be fine as long as >your filter is modest. You may have to pull some tricks if your filter >turns out to be more than 16 taps such as symmetry folding or time >multiplexing the multipliers to handle more than one tap per sample >(this is where working with a multiplied clock really helps out). > thank you for answering my question. I really appreciate it. Kenny,Article: 110615
Alex wrote: > So, to find the differences between scoreboard and checker we have to > understand the meaning of transaction: > "The transaction is quantum of activity that occurs in design bounded > by time" > "A transaction is a single transfer of control or data between 2 > entities" > "A transaction is a function call" > > First definition is too broad. By this definition, scoreboard is the > same as assertion-based checker, since both of them deal with quantums > of design activity bounded by time. > Second definition is different from the first one and too restrictive. > What does it mean "single transfer"? Why between only two entities? > Third definition is the one I cannot understand. Does it mean that > "transaction-based" component must contain functions? > > Regards, > -Alex Alex, I think you need to be careful not to confuse the generic use of terms like entities (things) in the AVM cookbook with VHDL key words. I agree it is difficult to tie down a definition of a transaction, as transactions can be different things to different people eg a h/w designer may want to identify individual transfers of data on a bus as a transaction, while someone viewing the design at a higher level is more interested in frames or packets, while at a system level it may be a message between s/w on different processors. All are valid transactions. In terms of the AVM, the basic TLM communication mechanism is based on the semantics of the OSCI TLM, implemented in SystemC and/or SystemVerilog. This defines the use of put(), get() and peek() function/task calls to transfer a transaction from one component to another. Both these languages support a component calling the tasks/functions of another component (using classes and/or interfaces). Thus my monitor can call the write() function of my scoreboard without needing to what it does. This allows me to change the scoreboard without effecting the monitor, provided the new scoreboard also implements a function called write(). This is the basis for verification component reuse in the AVM (and other transaction based verification methodologies.) So in the AVM, a transaction is most commonly just a function/task call between verification components, thus the third definition. I hope this help clarify things - NigelArticle: 110616
I have a EDk based design with 8 MB of external flash memory on PLB via the plb_emc core. This is for a Virtex II Pro using EDK/ISE 7.1i, latest service packs. Running a PPC program in either BRAM or SDRAM, I can burn and verify test patterns in the entire flash memory. I have another program that runs fine downloaded into external SDRAM. I am now trying to execute it in flash. I seems I get an illegal instruction exception on the very first instruction. I put in a single assembly instruction that lights an LED through a GPIO register and use XMD to start at that instruction. Works in SDRAM, not in flash. I have rechecked the timing parameters to the emc core and incresed the margins. For instance, my flash specs a read cycle of 90 ns, I'm giving it 120. I figure my next step is to learn enough of ChipScope to look at the bus cycles. However I'm hoping someone here has other suggestions or experience executing out of flash.Article: 110617
Without it's something like your flash chip is still in program mode when you try to jump to it, I expect it has something to do with the cache or the C_INCLUDE_DATAWIDTH_MATCHING option. What's the width of your flash device? Can you post the plb_emc section from your .mhs? Also, when you read the flash memory from xmd do you the the 32-bit words you expect? -Clark "Steve" <sgfallows@gmail.com> wrote in message news:1161204457.947152.292440@i42g2000cwa.googlegroups.com... > I have a EDk based design with 8 MB of external flash memory on PLB via > the plb_emc core. This is for a Virtex II Pro using EDK/ISE 7.1i, > latest service packs. Running a PPC program in either BRAM or SDRAM, I > can burn and verify test patterns in the entire flash memory. > > I have another program that runs fine downloaded into external SDRAM. I > am now trying to execute it in flash. I seems I get an illegal > instruction exception on the very first instruction. I put in a single > assembly instruction that lights an LED through a GPIO register and use > XMD to start at that instruction. Works in SDRAM, not in flash. I have > rechecked the timing parameters to the emc core and incresed the > margins. For instance, my flash specs a read cycle of 90 ns, I'm giving > it 120. > > I figure my next step is to learn enough of ChipScope to look at the > bus cycles. > > However I'm hoping someone here has other suggestions or experience > executing out of flash. >Article: 110618
pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote: > Specificly what kind of license is used..?, and what are the terms? For the LatticeMico32 there is an Open IP Core Licensing Agreement. This license lets you freely mix proprietary with open code and freely distribute hardware (FPGAs) without license documentation. This Open IP Core Licensing Agreement applies to the generated microprocessor HDL code and selected peripheral components HDL code. Click here to see the license: http://www.latticesemi.com/dynamic/view_document.cfm?document_id=21674 For the Development Tools (complier, assembler, linker and debugger) there is a GNU - General Public License (GPL). Hope this helps. Regards, Bart Borosky, LatticeArticle: 110619
Eric wrote: > I couldn't turn-in, but I'd like to hear comments from people who did! > It sounds interesting. > > Eric Starting tomorrow you should be able to view the archive of the webcast "on-demand" from the same link. rgds, bartArticle: 110620
On 2006-10-18, Steve <sgfallows@gmail.com> wrote: > I have a EDk based design with 8 MB of external flash memory on PLB via > the plb_emc core. This is for a Virtex II Pro using EDK/ISE 7.1i, I've done this on a V4 with newer EDK. One parameter that comes to mind is C_INCLUDE_DATAWIDTH_MATCHING if your flash bus width is narrower than the PLB. Another thing to check would be if you are loading the flash using something other than the CPU (eg jtag or a programmer) and your endianness doesn't match. If all accesses are via the CPU, that can't be it. -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 110621
samiam <samiamSPAMTHIS@spamalert.com> writes: > I am looking on ebay now, and I see one or two boards well above $100. > Any suggestions? Altera MAXII developers kit. I think this was $99 last time I checked. It has LED's, USB, LCD display, temprature sensor, PCI, etc. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 110622
Petter Gustad wrote: > samiam <samiamSPAMTHIS@spamalert.com> writes: > > > I am looking on ebay now, and I see one or two boards well above $100. > > Any suggestions? > > Altera MAXII developers kit. I think this was $99 last time I > checked. It has LED's, USB, LCD display, temprature sensor, PCI, etc. > > Petter > -- > A: Because it messes up the order in which people normally read text. > Q: Why is top-posting such a bad thing? > A: Top-posting. > Q: What is the most annoying thing on usenet and in e-mail? i'm thinking of getting the MAX II $100 board too. can it work external to the pc or pci only. does it auto program, can it be used to program other cpld and can the display be made external off board, for case mounting? i'd have to revert to on board gfx again as no free pci while agp in use. cheersArticle: 110623
Petter Gustad wrote: > Altera MAXII developers kit. I think this was $99 last time I > checked. It has LED's, USB, LCD display, temprature sensor, PCI, etc. Do you mean this board? http://www.altera.com/products/devkits/altera/kit-maxii-1270.html Looks like it costs $150 and it is an CPLD, only. And do you need an additional programmer for it? If you want to try Altera and want to spend $149, this is a nice board: http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=39&No=14 Anything is included on the board, like USB Blaster for programming and it has some nice interfaces, like video out and audio in/out and demo version of Nios etc. If you want to try Xilinx, Spartan3 is nice, too and costs $99 (there is anything included, too, so you don't need any additional programmer) : http://www.digilentinc.com/Products/Detail.cfm?Prod=S3BOARD&Nav1=Products&Nav2=Programmable I'm sure Lattice and other vendors have good development boards, too, but I have tested both boards, the Spartan 3 starter kit (and Spartan 3E starter kit) and the TREX C1, so I can guarantee that they are very good for this price. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 110624
Hi. I am trying to write generic VHDL code of ROM (read only memory). Values that shoud be writen in the memory need to be determined before compilation (from some file). I am working with Altera QuartusII software and I have seen there that Some mif or hex files were used for rom and ram initialization. How do I write VHDL code which will read that kind of file and its values write in ROM. Can anyone help me Thanks
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Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z