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On 16 Oct 2006 04:43:54 -0700, "Antti" <Antti.Lukats@xilant.com> wrote: >http://www.xilinx.com/prs_rls/2006/silicon_vir/0696v5lxt.htm > >already pricing given for 1000qty not bad at all. > >unfortunatly the LXT related user guides >ug194 EMAC >ug196 GTP >ug197 PCIe > >are all deadlinks at the moment but hopefully those documents become >available shortly. > >new eval boards (besides ML501) are > >ML505 - allows PCIe testing >ML523 - GTP characterization board >ML555 - 8x PCIe card Hmmm, www.xilinx.com "search" on "ML505" returns 0 results... these boards sound interesting though! - BrianArticle: 110551
leeaby@gmail.com wrote: > Hi everyone, > > I am new to the FPGA, and would like to know more about how we can > program an FPGA to do a complex task. > > Please suggest the steps or any website relevant to this which aids in > studying. > > Thanks to all in advance > You should probably start by realizing that "programming" the FPGA is actually digital logic design. I hate the word "program" when it is associated with FPGA design because it leads folks to think that developing an FPGA application is similar to developing a computer program. It is not, and if you attempt to treat it as if it was, you will have a difficult time getting your design working reliably. With that in mind, the first step is to try to envision the logic circuit that would accomplish your desired task, then use whatever tools you are most comfortable with to capture that design, simulate it and then synthesize it to the FPGA hardware. The FPGA vendors for the most part have free or low cost tools to do all of that for smaller FPGAs.Article: 110552
Brian Drummond schrieb: > On 16 Oct 2006 04:43:54 -0700, "Antti" <Antti.Lukats@xilant.com> wrote: > > >http://www.xilinx.com/prs_rls/2006/silicon_vir/0696v5lxt.htm > > > >already pricing given for 1000qty not bad at all. > > > >unfortunatly the LXT related user guides > >ug194 EMAC > >ug196 GTP > >ug197 PCIe > > > >are all deadlinks at the moment but hopefully those documents become > >available shortly. > > > >new eval boards (besides ML501) are > > > >ML505 - allows PCIe testing > >ML523 - GTP characterization board > >ML555 - 8x PCIe card > > Hmmm, www.xilinx.com "search" on "ML505" returns 0 results... > these boards sound interesting though! > > - Brian you didnt look deep enough :) ok here is the link http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/capabilities/PCIe.htm end of page, all 3 boards listed Antti From henrik.kirneh@gmail.com Tue Oct 17 12:38:56 2006 Path: newssvr21.news.prodigy.com!newsdbm04.news.prodigy.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!news.linkpendium.com!news.linkpendium.com!uio.no!uninett.no!news.net.uni-c.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Message-Id: <45353150$0$49200$14726298@news.sunsite.dk> From: Henrik Pedersen <henrik.kirneh@gmail.com> Subject: Re: WebPack on Linux Newsgroups: comp.arch.fpga Reply-To: henrik.kirneh@gmail.com Date: Tue, 17 Oct 2006 21:38:56 +0200 References: <4533cbef$0$49200$14726298@news.sunsite.dk> <pan.2006.10.16.22.59.58.430093@polybusPleaseDontSPAMme.com> User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 38 Organization: SunSITE.dk - Supporting Open source NNTP-Posting-Host: 217.116.244.170 X-Trace: news.sunsite.dk DXC=WnPeB4f1UB=Bi9D?DQ_c:4YSB=nbEKnk;BkLN3=Hd2i;YDoQ\kQ?kD4^PgABlB42E?IHQFW\gATb;1VYSn^jGTg4GX_hS]faD:3Qd]m8kXAX=4 X-Complaints-To: staff@sunsite.dk Xref: prodigy.net comp.arch.fpga:121499 Josh Rosen wrote: > On Mon, 16 Oct 2006 20:14:07 +0200, Henrik Pedersen wrote: > >> Greetings >> >> How is this supposed to work ? >> >> I have installed webpack for Linux on my FC5 box, and that part is >> working. I can compile my VHDL files, generate fitterrepports etc. >> But the following does'nt work: >> >> "Assign Package Pins" >> When i click it, it says >>Started : "Assign Package Pins".<< >> But nothing happens. >> I think that the executable is a file name "pace", and when i run pace in >> a console window i get the error >> /opt/Xilinx/bin/lin/_pace: error while loading shared libraries: >> libXm.so.3: cannot open shared object file: No such file or directory >> I have installed openmotif, which should contain the file in question, >> but without any luck. >> >> Then i have tried executing different files in the /opt/Xilinx/bin/lin/ >> directory. (create_sdc, arwz, qtconfig) and a couple others all of them >> generates errors about missing libX?????.so files that actually are >> located in the same directory. >> >> How do i go about narrowing down the problem and getting it to work ? >> >> Henrik > > Make sure you have the compatibility libraries loaded. The Xilinx tools > are targeted at RHEL which is way behind Fedora so you need to load the > compatibility libraries. Sounds good and easy, but how do i go about doing that ? HenrikArticle: 110553
pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote: > ldconfig + setenv LD_LIBRARY_PATH Tried as root doing above. Response is ldconfig: relative path `+' used to build cache But it still does'nt work. HenrikArticle: 110554
On Tue, 17 Oct 2006 21:38:56 +0200, Henrik Pedersen wrote: > Josh Rosen wrote: > >> On Mon, 16 Oct 2006 20:14:07 +0200, Henrik Pedersen wrote: >> >>> Greetings >>> >>> How is this supposed to work ? >>> >>> I have installed webpack for Linux on my FC5 box, and that part is >>> working. I can compile my VHDL files, generate fitterrepports etc. >>> But the following does'nt work: >>> >>> "Assign Package Pins" >>> When i click it, it says >>Started : "Assign Package Pins".<< >>> But nothing happens. >>> I think that the executable is a file name "pace", and when i run pace in >>> a console window i get the error >>> /opt/Xilinx/bin/lin/_pace: error while loading shared libraries: >>> libXm.so.3: cannot open shared object file: No such file or directory >>> I have installed openmotif, which should contain the file in question, >>> but without any luck. >>> >>> Then i have tried executing different files in the /opt/Xilinx/bin/lin/ >>> directory. (create_sdc, arwz, qtconfig) and a couple others all of them >>> generates errors about missing libX?????.so files that actually are >>> located in the same directory. >>> >>> How do i go about narrowing down the problem and getting it to work ? >>> >>> Henrik >> >> Make sure you have the compatibility libraries loaded. The Xilinx tools >> are targeted at RHEL which is way behind Fedora so you need to load the >> compatibility libraries. > > Sounds good and easy, but how do i go about doing that ? > > Henrik Use Yumex. Search for compat and then install the compat-libstdc++-33 library. From paulu@sx4all.nl Tue Oct 17 12:52:52 2006 Path: newssvr21.news.prodigy.com!newsdbm04.news.prodigy.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!newsfeed1.ip.tiscali.net!tiscali!transit1.news.tiscali.nl!transit.news.xs4all.nl!xs4all!post2.news.xs4all.nl!newszilla.xs4all.nl!not-for-mail Message-Id: <45353494$0$5594$e4fe514c@dreader28.news.xs4all.nl> From: Paul Uiterlinden <paulu@sx4all.nl> Subject: Re: Synopsys's VMM and Mentor's AVM Newsgroups: comp.lang.verilog,comp.lang.vhdl,comp.arch.fpga Date: Tue, 17 Oct 2006 21:52:52 +0200 References: <1160967443.885458.176120@e3g2000cwe.googlegroups.com> <4533dbba$0$2574$e4fe514c@dreader16.news.xs4all.nl> <1161049990.881875.255360@i3g2000cwc.googlegroups.com> User-Agent: KNode/0.10.1 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 19 NNTP-Posting-Host: 213.84.176.29 X-Trace: 1161114772 dreader28.news.xs4all.nl 5594 213.84.176.29:10216 Xref: prodigy.net comp.lang.verilog:34043 comp.lang.vhdl:66880 comp.arch.fpga:121502 Davy wrote: > Hi Paul, > > Thanks a lot! > I also want to know does Cadence provide such verification > methodology like Synopsys and Mentor. Not that I know of. I haven't come across it, but I haven't actively been searching for it. > And what's Synopsys (IIRC)'s IIRC mean? IIRC is just an abbreviation for "If I remember correctly". Sorry for the confusion. -- Paul.Article: 110555
Virtex-5 Evaluation board ML501 Testing
=============================
Preloaded designs:
All CompactFlash demos worked
(did not check the WebServer as the IP address doesnt much my settings)
Demos from Platform flash started
Demos from Paralle flash also (can choose one of 4 configurations)
SPI Flash seems to be empty, eg no design starts (or I didnt find the
mode selection?)
MicroFpga LED show demo also worked GPIO LEDs at the left front corner
did blink.
After updating ChipScope the V5 sysmon did become visible in ChipScope
analyzer.
Testing PLL's and configuration clock - connected 50MHz config clock to
PLL, setting multiply to 7, then FX output to spare pin extension
header and voila 300+ MHz frequency measured.
u-Boot
======
After adding ML501 support for u-boot 1.1.4 verified that the images
worked with XSIM platform simulator. Then tried on ML501 and here it
did not work, created ACE file, copied to cfg6 position ("my ace")
selected cfg from boot menu, and nothing only ERR2 (OPB error) goes
red. Ok that was my fault, I had compiled the u-boot with barrel shift
enabled and ML501 reference design had no barrel shift enabled, and
unfortunatly XSIM 1.3 doesnt have option to disable barrel-shift so the
problem was found with simulator. After u-boot was recompile with
proper settings, well it still didnt start from system ACE, but started
ok when loaded from XMD. When generating the ACE file, well it did took
really long, and the files generated did appear to be too big over 3MB
(4MB for the u-boot), even after compression with Xilant's ace
compressed the ACE file size was still way over 2.5MB, the ACE files on
the CF card are however all about 1.6MB. So I had to force use fsl
option in genace.tcl, now the uboot.ace was also correct size and ACE
file generation was quick again.
Tried to download the ACE file over JTAG using ACE Player, failed, ah
sure the chain is not setup properly as it looks different from the
external connector to what the system ACE sees it.
Tried to generate some ACE file from the XPS GUI, first attempt created
file for v4FX12 ! This was due wrong version of genace.tcl being found
on the path, moved the genace.tcl from /data to project dir now the ACE
file was created properly for ML501 but it did also not work.
Ooopla the MDM FSL link option was not enabled in the hardware project,
thats why. Adding FSL (this had to be done in MHS as the FSL bus was
not visible in GUI) resynthesize, test - no luck either, the ERR2 LED
doesnt go RED, but nothing works. Starting XMD (while FPGA is loaded
from new bitstream via CF card), now XMD doesnt work - it almost
freezes after saying that FSL debug link is available, and gives error
stopping CPU when loading ELD files.
Ok, lets try the "golden" download.bit from the reference design.
Making ACE file - nothing! Trying XMD, it fails to connect to MDM or
see MicroBlaze in scan chain completly. Reloading the bootloader from
CF card, starting XMD - failed? Trying again, failed. Must be cable
driver stopped working. Switching cables from USB to Cable IV, trying..
works. Says Caches are enabled well in the reference design there are
no caches. Loading u-boot with XMD, run - ERR2 is RED. Trying to
download bitstream with XPS/impact loading u-boot.elf with XMD nothing.
Hm, maybe the problem is with exceptions - I had enabled all of them,
lets try disabling exceptions leaving barrel-shift and FSL debug link
enabled.
Maybe the downbload.bit from orignal ref design /implementatio/
directory works? Lets see - Design loaded from SPI memory ? I must
have messed up the mode switches. Yes so it was!
Ok, selecting ACE, selectin "my ace" still the RED ERR2 LED!
Ok, P&R finished lets try, no RED LED, but no loaded designs work. And
one timing constraint was not met.
Trying trying trying. Hm, lets start XMD from commandline not from GUI.
Using bootloader design, u-boot works, loading my bitstream, u-boot
works. Maybe the FSL link isnt working? Changing the tcl file back,
regenerating ACE file (this takes now looong time) done!
Loading from my ACE file, RED LED, no uart activity. But what happened?
The FPGA and DDR2 memory is now loaded with design that I compiled and
with the last u-boot, ok, lets see starting XMD from commandline,
looking at the u-boot base address looks ok, eg system ace software
loading was succesful. Starting from u-boot base address (without
reloading) and it works!
So the bitstream is OK, uboot is ok, the SW is loaded into memory but
when loaded from compact flash doesnt autostart (or starts and stalls
somewhere).
Power off, setting cfgaddr=6, power on, starting XMD looking at
registers looks like the CPU isnt started at all, ah there was a
warning about start address not being there in the ELF file! maybe I
fixed it badly? But when loaded with XMD the same ELF file loads ok,
and set start address also properly?
Oioiaai - I had the u-boot compiled to DDR2 memory base, and had the
genace patched to that address, but later I had changed the uboot to
load at different address so uclinux could be loaded at DDR2 base
address but had not fixed the genace to reflect the new address.
Lets try maybe now the FSL loading also works, nops nothing. Back to
the big ACE files without the use of fast FSL download link.
an NOW !!! u-boot works :) here is terminal log session:
****************************************************************************************
Welcome to the Xilinx Virtex-5 ML501 Evaluation Platform Bootloader
Menu!
Please choose a demo by typing in the number of the demo you want to
use
Or select a demo using the directional buttons and LCD or VGA display
(Then press the center button to start the selected demo)
1. Virtex-5 Slide Show
2. Web Server Demo
3. Simon Game
4. Chipscope Pro Demo
5. USB Demo
6. My own ACE file
7. Ring Tone Player
Rebooting to System ACE Configuration Address 6...
Using default environment
u-boot ML501
=> ver
U-Boot 1.1.4 (Oct 17 2006 - 21:45:50)
=> help
? - alias for 'help'
base - print or set address offset
bootm - boot application image from memory
cmp - memory compare
cp - memory copy
crc32 - checksum calculation
echo - echo args to console
fatinfo - print information about filesystem
fatload - load binary file from a dos filesystem
fatls - list files in a directory (default /)
go - start application at address 'addr'
help - print online help
loads - load S-Record file over serial line
loop - infinite loop on address range
md - memory display
mm - memory modify (auto-incrementing)
mtest - simple RAM test
mw - memory write (fill)
nm - memory modify (constant address)
printenv- print environment variables
reset - Perform RESET of the CPU
run - run commands in an environment variable
setenv - set environment variables
version - print monitor version
=>bye!
Antti
From paulu@sx4all.nl Tue Oct 17 13:33:20 2006
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Message-Id: <45353e11$0$6726$e4fe514c@dreader21.news.xs4all.nl>
From: Paul Uiterlinden <paulu@sx4all.nl>
Subject: Re: Synopsys's VMM and Mentor's AVM
Newsgroups: comp.lang.verilog,comp.lang.vhdl,comp.arch.fpga
Date: Tue, 17 Oct 2006 22:33:20 +0200
References: <1160967443.885458.176120@e3g2000cwe.googlegroups.com> <4533dbba$0$2574$e4fe514c@dreader16.news.xs4all.nl> <1161099114.718981.104290@m7g2000cwm.googlegroups.com>
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Xref: prodigy.net comp.lang.verilog:34044 comp.lang.vhdl:66882 comp.arch.fpga:121504
Ajeetha wrote:
> Hi,
>
>
> Paul Uiterlinden wrote:
>> Davy wrote:
>>
>> > Hi all,
>> > I don't know if Synopsys's VMM is open document and open source
>> > code.
>>
>> As far as I know the VMM book is not an open document:
>> http://www.vmm-sv.com/
>>
>
> I don't understand this - perhaps you are mixing "open" with
> "free"?
Yes, I am. What I meant it is not freely down-loadable.
> VMM is a published book so why is it not open? Infact we wrote a
> book on "pragmatic approach to VMM adoption" based on that book.
> (See www.systemverilog.us if interested). BTW, VMM also ships under
> $VCS_HOME/doc.
>
>> The AVM cookbook clearly is.
>>
>> The same goes for VMM and AVM itself. AVM is opensource, VMM source
>> is heavily licensed (word choice from Verification Horizons).
>>
>
> Quoting from:
>
>
http://www.synopsys.com/news/announce/press2005/snps_sourcode_licsvpr.html
>
> SNPS gives source code to VCS users if they request for the same.
"VCS customers may license the source code at no additional cost to
gain insight into the implementation details."
So that's for VCS users. I'm not a VCS user, so I do not have access
to the source code. In that way it _is_ licensed. The AVM source is
not.
> Now having said all this, given the status of SV implementation by
> major eda vendors, neither VMM nor AVM is truly "portable" as of
> today - tools support different subsets just to fit into their
> individual methodology, perhaps the tool development was driven by
> the methodology team. So when 100% SV implementation is available
> across vendors, users may not have an issue of AVM vs. VMM as both
> will work in any simulator.
>
> Now, I'm teaching myself AVM and am finding it quite similar to VMM.
> Sure VMM has much more stuff, also maturity (given their RVM
> legacy), AVM has some "new" concepts such as analysis ports etc.
I cannot comment on this. I haven't used or really studied neither of
them. I did find this quote from Verification Horizons quite potent:
"(...) I mention this story because it is similar to the thought
process that many of you may be going through in trying to decide how
to adopt a new verification methodology. You have a similar choice to
make - should you go with the AVM or take a look at the VMM? In my
minivan story, the VMM is the used car since it?s really based on old
technology, having simply been ported from OpenVera� to
SystemVerilog. The AVM is the new topof-the-line car that gives you
all of the latest features and the power and flexibility that you
need. Plus your tool and legacy investments are protected because it
is based on an open standard. Which would you rather use to carry
your precious cargo?"
Granted, this is by Mentor Graphics, so perhaps should be taken with a
grain of salt. I really do not have the knowledge to put a value on
quotes likes this. Perhaps you would like to comment on this.
> I asked Mentor if I can openly debate on AVM, no reply yet...
Call me naive, but I do not see why such a debate should not be
possible. It's a free world, "free" as in "free speech", not as in
"free bear".
--
Paul.
www.aimcom.nl
Article: 110556Ray Andraka wrote: > leeaby@gmail.com wrote: > >> Hi everyone, >> >> I am new to the FPGA, and would like to know more about how we can >> program an FPGA to do a complex task. >> >> Please suggest the steps or any website relevant to this which aids in >> studying. >> >> Thanks to all in advance >> > > You should probably start by realizing that "programming" the FPGA is > actually digital logic design. I hate the word "program" when it is > associated with FPGA design because it leads folks to think that > developing an FPGA application is similar to developing a computer > program. It is not, and if you attempt to treat it as if it was, you > will have a difficult time getting your design working reliably. > > With that in mind, the first step is to try to envision the logic > circuit that would accomplish your desired task, then use whatever tools > you are most comfortable with to capture that design, simulate it and > then synthesize it to the FPGA hardware. The FPGA vendors for the most > part have free or low cost tools to do all of that for smaller FPGAs. As noted, FPGAs realise hardware in a programmable way [although one might say processors do that, merely one step at a time ;)] That said, some decent resources on hardware would help. If you have not used a schematic capture tool, get one and use it. KiCad is free and works well. You'll learn about netlists and all those other fun things in the hardware world, to say nothing of connecting basic functions together to do something interesting. For HDL languages in books, there are a lot of resources, but I like HDL Chip design by Douglas J. Smith 0-9651934-3-8. Covers both Verilog and VHDL in a neutral way, and an excellent book for a beginner. Of course, as always, google is your friend. As to the thread about 'debug someone else's complex design' - that was actually the way I started in FPGAs :) Cheers PeteSArticle: 110557
In comp.arch.fpga bart <bart.borosky@latticesemi.com> wrote: >Lattice is holding a webcast tomorrow Wednesday, October 18, "Embedded >Design with LatticeMico32 Open, Free 32-bit Soft Processor." The >presenter will be Amr El-Shimi, from our IP marketing group. Specificly what kind of license is used..?, and what are the terms? Didn't find it at the site. http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/index.cfm "HDL codes are available through a unique open IP core licensing agreement."Article: 110558
"Bob" <rjmyers@raytheon.com> wrote in message news:4534F75A.45251BBE@raytheon.com... >I have a number of Dual-Port Rams and FIFOs that I've implemented with > Quartus II 6.0 sp#1, targeting a Stratix II device. Dual clock or single clock? I'll assume from here on down that it is single clock. If it's a dual clock memory then you go down a different path (I'll discuss this at the end of the post). > > When I simulate with my test bench in the "functional" world, everything > acts as > expected. Good > > When I compile the .vho/.sdo files and run against a slightly modified > test bench > (differences in output file names and the test bench calling out the > VITAL version > of the FPGA implementation), it appears that there is an additional > register delay > that has been introduced into the Dual-Port/Fifo implementations. > > Is this normal? No > Or do I need to make some type of adjustment for this > behavior? I don't quite know how to explain/justify the differences at > this > point. You don't justify them, you find the cause of them. The most likely explanation is that your testbench is not adhering to the setup timing of the final routed design. Check that the signals arrive at the input to the design with at least the amount of time specified in the timing report output file. If this is the problem then in essence your testbench is 'violating' the timing of the device. When that happens lots of things can go wrong, what you're seeing would be simply a symptom of that. If timing is not being violated and this is a single clock design then you'll find that pre-route and post-route simulations match clock for clock....without exception...regardless of what the actual design is. If you do have two clocks running around then where signals move from one clock domain to the other than the 'extra' delay that you're seeing is not unexpected and there isn't really anything that you can do about it. Just like in the real world where you can't count on two async clocks to have any phase relationship and clock domain crossing can cause an extra clock cycle delay you'll see the same thing at times when comparing pre/post-route sims. KJArticle: 110559
Hi, I'm currently working with the I2C core supplied by OpenCores.org. I have successfully got the design to work in an FPGA. However, all of the slave device I used may not have the clock stretching feature implemented. As a result, I am not sure if this I2C core uses the included clock stretching feature correctly. I tried looking at the code, but could not find any code that implies clock stretching logic. The documentation for this core also lacks information regarding the clock stretching. Has anyone used this core with a slave that performed clock stretching? If you're familiar with this core, my control logic for this core simply sends the instructions that's required for read/write and waits for interrupts, ack/nack, and TIP logic to assert/deassert. Do I need to add logic to detect clock stretching? Thanks, -MArticle: 110560
Ajeetha wrote: > Hi, > > > Paul Uiterlinden wrote: > > Davy wrote: > > > > > Hi all, > > > I don't know if Synopsys's VMM is open document and open source > > > code. > > > > As far as I know the VMM book is not an open document: > > http://www.vmm-sv.com/ > > > > I don't understand this - perhaps you are mixing "open" with "free"? > VMM is a published book so why is it not open? Infact we wrote a book > on "pragmatic approach to VMM adoption" based on that book. (See > www.systemverilog.us if interested). BTW, VMM also ships under > $VCS_HOME/doc. > > > The AVM cookbook clearly is. > > > > The same goes for VMM and AVM itself. AVM is opensource, VMM source is > > heavily licensed (word choice from Verification Horizons). > > > > Quoting from: > > http://www.synopsys.com/news/announce/press2005/snps_sourcode_licsvpr.html > > SNPS gives source code to VCS users if they request for the same. > > Now having said all this, given the status of SV implementation by > major eda vendors, neither VMM nor AVM is truly "portable" as of today > - tools support different subsets just to fit into their individual > methodology, perhaps the tool development was driven by the methodology > team. So when 100% SV implementation is available across vendors, users > may not have an issue of AVM vs. VMM as both will work in any > simulator. > > Now, I'm teaching myself AVM and am finding it quite similar to VMM. > Sure VMM has much more stuff, also maturity (given their RVM legacy), > AVM has some "new" concepts such as analysis ports etc. I asked Mentor > if I can openly debate on AVM, no reply yet... [snip] Hi Ajeetha, Thanks for the explanation. I think a lot of people will be interested in your openly comment on both VMM and AVM without biased opinion. For AVM, it use Apache licence. Is this licence forbid openly debate :) Best regards, Davy > > Regards > Ajeetha, CVC > www.noveldv.com > > > -- > > Paul.Article: 110561
Hey all I saw this on an example design (on Xilinx ISE): NET clkb PERIOD = 25ns; NET "clkb" LOC = A16; what does it mean when it mention about the period 25ns? in the design, the clock at location A16 is actually 40Mhz (25ns). is this necessary for UCF file? thxArticle: 110562
Hi Davy, > Hi Ajeetha, > > Thanks for the explanation. > I think a lot of people will be interested in your openly comment on > both VMM and AVM That's one of the reasons for me to hold back :-) As I have to be 100% correct else Mentor and/or SNPS folks will start pin pointing errors with my analysis. I would take some more time, but from quick analysis so far, both are very similar in concepts and I am even considering an "adaptor" for AVM users to VMM and vice versa - but all in thoughts, depends on market. > For AVM, it use Apache licence. Is this licence forbid openly debate :) > Honestly speaking I have NOT read through the license in full and am not a lawyer either. Hence I would be glad if someone clearly says "yes we can debate on it". Being an independent consutlant I want to be friendly to all vendors. Regards Ajeetha, CVC www.noveldv.comArticle: 110563
sutejok wrote: > Hey all > > I saw this on an example design (on Xilinx ISE): > > NET clkb PERIOD = 25ns; > NET "clkb" LOC = A16; > > what does it mean when it mention about the period 25ns? > in the design, the clock at location A16 is actually 40Mhz (25ns). is > this necessary for UCF file? > > thx > That's a timing constraint to make sure that the tools place and route the design with a solution that will work at your desired 40 Mhz clock rate. It is necessary if you want your design to meet timing (ie if you want your design to work over temperature, voltage and process).Article: 110564
Ajeetha wrote: > Hi Davy, > > Hi Ajeetha, > > > > Thanks for the explanation. > > I think a lot of people will be interested in your openly comment on > > both VMM and AVM > > That's one of the reasons for me to hold back :-) As I have to be > 100% correct else Mentor and/or SNPS folks will start pin pointing > errors with my analysis. I would take some more time, but from quick > analysis so far, both are very similar in concepts and I am even > considering an "adaptor" for AVM users to VMM and vice versa - but all > in thoughts, depends on market. > > > > > For AVM, it use Apache licence. Is this licence forbid openly debate :) > > > > Honestly speaking I have NOT read through the license in full and am > not a lawyer either. Hence I would be glad if someone clearly says "yes > we can debate on it". Being an independent consutlant I want to be > friendly to all vendors. [snip] Hi Ajeetha, I agree with you. And I have sent a mail to apache.org (Apache License V2 owner) to ask the problem. I will give out the result when got a replay. Best regards, Davy > > Regards > Ajeetha, CVC > www.noveldv.comArticle: 110565
I'm doing a new design with a SERDES at 1.6Gbps. For cost reasons, I'm using an FPGA without serial IO, so I'm looking at using one of the following TI parts: - TLK2501 - TLK2521 - TLK2701 I am having trouble choosing between them. They all look basically the same except that the 2521 is 18-bits using Start/Stop bits, while the other 2 use 8B/10B coding. The 2701 gives you direct access to the K-codes, while the 2501 just gives you sync and error signals. My question is this: Is there a reason I should prefer 8B/10B over 18-bit? I don't really need the additional 2 bits, but my concern is with maintaing sync. I need to burst packets through, but there is no way to retransmit anything if there is any kind of loss. It needs to be obvious when packets start and end. I'd also like to be able to eventually talk to one of these with a Rocket-IO, so that sort of compatibility is necessary. Any advice would be appreciated. Thanks, MattArticle: 110566
RocketIO uses 8B/10B encoding, so if you want to talk to them in the future probably better to use that scheme. Plus, in my opinion, 8B/10B is better than a high-speed RS-232 like protocol. Because of the encoding, it gives you extra control characters and maintains a balance of 0s and 1s on the line. ---Matthew Hicks "M E" <boyscout@gmail.com> wrote in message news:1161146454.608189.206580@k70g2000cwa.googlegroups.com... > > > I'm doing a new design with a SERDES at 1.6Gbps. For cost reasons, I'm > using an FPGA without serial IO, so I'm looking at using one of the > following TI parts: > > - TLK2501 > - TLK2521 > - TLK2701 > > I am having trouble choosing between them. They all look basically the > same except that the 2521 is 18-bits using Start/Stop bits, while the > other 2 use 8B/10B coding. The 2701 gives you direct access to the > K-codes, while the 2501 just gives you sync and error signals. > > My question is this: Is there a reason I should prefer 8B/10B over > 18-bit? I don't really need the additional 2 bits, but my concern is > with maintaing sync. I need to burst packets through, but there is no > way to retransmit anything if there is any kind of loss. It needs to > be obvious when packets start and end. > > I'd also like to be able to eventually talk to one of these with a > Rocket-IO, so that sort of compatibility is necessary. > > Any advice would be appreciated. > > Thanks, > Matt >Article: 110567
Hi everyone, I'm currently using a vitex-II pro FPGA, I've implemented an NCO frequency generator, which is supplied with a 64bit init & delta phase value. I'm currently using a local oscillator to clock the NCO ( must use specific local oscillator) but this does contain a margin of offset and drift thus influencing output frequency of NCO. A compensation circuit which includes another stable clock is used to correct the drift and offset by using a frequency counter on both clocks then calculating appropriate delta phase to compensate. My problem is that my equation to calculate adjusted delta which requires a 64 bit division Delta2 = (count2/count1) * delta1 Delta2 = new delta phase with correction Count2 = frequency counter for Local Oscillator Count1 = frequency counter for external Oscillator Delta1 = Original calculated delta phase to product output frequency What would be the most appropriate way of doing this calculation, especially with the division? also time constraints, everyone 1.6ms roughly this will occur. Maybe this could be done differently? Ideas I've been thinking about are on the lines of, Maybe reduces the counting resolution ? use internal PPC (CPU) Any advice would be appreciated :) Cheers LucaArticle: 110568
Some useful links for getting started in FPGAs off our webpage http://www.enterpoint.co.uk/techitips/techitips_useful_things.html. Also look at the parent page for TechiTips as there may be a couple of other items there that might be of interest although most things on that page are more advanced. John Adair Enterpoint Ltd. leeaby@gmail.com wrote: > Hi everyone, > > I am new to the FPGA, and would like to know more about how we can > program an FPGA to do a complex task. > > Please suggest the steps or any website relevant to this which aids in > studying. > > Thanks to all in advanceArticle: 110569
Hi Jens, I still have questions to ask you :) After completing the synthesis step and move to constraint step. When I run the ngdbuild to make the .ngd file, I meet this error: WARNING:Pds - Attempted to load old format .nmc file "D:\My_Researches\Workspace\PR1\Top/busmacro_xc2vp_r2l_async_enable_wide.nmc" , but this format is no longer supported. FATAL_ERROR:NgdBuild:Portability/export/Port_Main.h:127:1.5 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To resolve this error, please consult the Answers ... My ISE is now SP1 with PR. Is that the problem with bus macro, or sth else? And, do you have the source of example in the xapp255? Regards, Thang NguyenArticle: 110570
Isaac Bosompem wrote: > I am currently in my 3rd year of Electrical Engineering undergrad at > Ryerson University in Toronto, Ontario, Canada. The internship (if > acquired) is slated to start right after this academic year. > This effectively delays my graduation by 1 yr, but I think that is a > really small price to pay for the experience. > > Here is a rudimentary list of my skills, a more thorough one will be > submitted w/ my resume: > > Programming Languages: C, Java, Visual Basic, Assembly, Win32 > programming, Python > > Compilers/Environment: GNU tools, Microsoft Visual Studio > > Microprocessors/Microcontrollers: M680x0, Z80, x86, 8051, PIC, MSP430, > ARM7, HC11, Renesas SuperH series > > proemulator.sf.net > > I ported my Z80 emulator to this app some time ago. My M68000 emulator > is working and is tested to be quite accurate, but the author no longer > maintains it or updates it so I decided against porting it (even though > I can still get into the CVS). > > Programmable Logic: Xilinx Spartan3 series FPGA w/ Xilinx ISE WebPack > > I designed a simple VGA frambuffer 320x240x2-bit and a simplistic > 16-bit CPU in VHDL. > > Electronics: Basic analog electronics (FET's, OpAmps, BJT's, etc.) > Here all I did was some school projects. Simple stuff: VCO's, FET amps, > etc. > > Operating Systems: Linux, MS-DOS, Windows (effective w/ all). > Been doing installs on all OS's for quite some time now. Used MS-DOS > while I was growing up (had it first running on a 16Mhz 386SX). > > Most the stuff I have learned was from buying products containing the > previously mentioned items and playing around with them and their > associated tools and reading my dads old college books (he studied > electronics engineering technology at NAIT. They did extensive course > work in digital electronics). > > I really do not have any related engineering experience. I did work for > GO Transit this past summer, a major transportation company here in > Ontario, as general help. I was called on one day to look over some > computer scans of microfilm schematics of the trains (and electrical > systems) to make sure they were up to par. > > I would like to shadow some teams in the engineering sector to get a > feel of what you guys do in the industry. I would like to see how you > guys solve problems, tackle issues or shortcomings you come up in > development and the like. I'd also like to learn from the people > working in this industry in general since they have a wealth of > knowledge and experience. Sometthing I think can be invaluable to me in > my career. > > They have some listings at my school, but they are not exactly what I > am interested in. Thanks for listening to my story! Do not even take the nearest fit, you still need broadening. Take a low moderate fit, you will learn much more that way. > > Any companys you know of in Toronto? > I know Altera has some offices here. Might try and get a hold of them > later on. > > -Isaac > > (This is a reposting as suggested by a responder in the previous > posting) -- JosephKK Gegen dummheit kampfen die Gotter Selbst, vergebens. --SchillerArticle: 110571
I also could instantiate the Block RAM in HDL and put my initialization data there, but it would be nice if i could use my automatically generated *.ceo files for the initialization of the block ram. I also need this data in the simulation, so i can't use data2mem for just inserting it into the *.bit file.Article: 110572
Hi Luca,
<luca_grossi@hotmail.com> wrote in message
news:1161151712.672647.312730@m7g2000cwm.googlegroups.com...
> Hi everyone,
> I'm currently using a vitex-II pro FPGA, I've implemented an NCO
> frequency generator, which is supplied with a 64bit init & delta phase
> value. ....
> My problem is that
> my equation to calculate adjusted delta which requires a 64 bit
> division
>
> Delta2 = (count2/count1) * delta1
>
> Delta2 = new delta phase with correction
> Count2 = frequency counter for Local Oscillator
> Count1 = frequency counter for external Oscillator
> Delta1 = Original calculated delta phase to product output frequency
Why not design your circuit such that count1 is always a power of two? I
might not have understood your requirements correctly, and I'm not sure
exactly what frequencies you're dealing with... but if you can just "choose"
a convenient 2^N value for count1 to count up to, then calculating the ratio
of count2/count1 just means dropping N LSbits of the value measured for
count2.
Of course, if the external oscillator frequency is allowed to vary
significantly, then in this case the delta update period would vary at the
same rate.
This answer sounds way too simple, so I bet I've misunderstood what you're
trying to do... if so, sorry to waste your time! :)
Cheers,
-Ben-
Article: 110573> > > > Honestly speaking I have NOT read through the license in full and am > > not a lawyer either. Hence I would be glad if someone clearly says "yes > > we can debate on it". Being an independent consutlant I want to be > > friendly to all vendors. > [snip] Mentor Graphics encourages open discussion of anything we have published at www.mentor.com/go/cookbook. This is why we published it in that form. Any code or pseudo code that uses the AVM is fine. Questions refering to specific items in the documentation are fine. If you're going to post the contents of the library itself you already have permission under the license to do so provided you also copy the header at the top of the file which includes the copyright notice - although I would have thought this would be unecessary most of the time. Adam. Adam Rose Verification Technologist Mentor Graphics.Article: 110574
Hello all, I want to implement integrator using vhdl, all xilinx logic core, is it available or anyone worked on this topic? Jaywant
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