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Here are the details: All plastic easily absorbs moisture. When such a plastic package is suddenly heated up (chips used to be run straight through a solder bath), then the internal steam can blow up the package. Conscientious manufacturers, therefore, bake plastic parts for hours, before they solder them on the board (unless the chips come directly out of a moisture-controlled environment.) This is all pretty common practice, definitely not Xilinx-specific. Peter Alfke (from home) ======================== David Ashley wrote: > Hal Murray wrote: > >... > > Is there a mechanism to make a whole batch of chips go bad > > without visible damage? I'm assuming idiot or short cuts > > rather than malicious. The sort of thing that would happen > > in a startup about to go under. > > I thought I read Peter mention something about humidity -- > if the humidity isn't kept right during storage, something > bad can happen to the pads, so when the part is soldered > down to a PCB something won't be right...or something. > > -Dave > > -- > David Ashley http://www.xdr.com/dash > Embedded linux, device drivers, system architectureArticle: 109326
xyjiang@ncic.ac.cn wrote: > David Ashley wrote: > >>Ray Andraka wrote: >> >>>Partial reconfiguration itself is not new, but the tools' ability to >>>handle it is. The design flow for partial reconfiguration is not for >>>the faint of heart. Unless you have a reason to be swapping partial >>>bitstreams in and out in many different combinations, you are generally >>>better off using full bitstreams. >> >>What about just using 2 FPGA's? > Yes, I wonder when one FPGA is working and the other is configured at > the same time when they are working for the same module. > > Camwood Well you'd have the same problem with partial reconfiguration of a single fpga as well, wouldn't you? With 2 fpga's you use one that does the permanently required functionality. Then the other can be reconfigured as necessary. -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 109327
get an old one, or a PCMCIA card with a true parallel port. >> >> (- Or concentrate on the AVR stuff :-). >> I think AVR Studio now supports USB <-> Serial Bridges. >> > > They pretty much all do now. The coolest thing is that little EZ430 stick. > You can connect wires to it after cracking it open and then use it at a > client site. Slips right into a small pocket. Of course, airport security > will want to know what that thing is... > > -- The AVR Dragon has a nicer box :-) -- Best Regards, Ulf Samuelsson This is intended to be my personal opinion which may, or may not be shared by my employer Atmel Nordic ABArticle: 109328
Hi markus, O ya ,that has helped me a lot. actually i tried to test with a eeprom slave. But the test is not giving the correct results.may be there may be something wrong with the eeprom model.i got it from net. vits markus wrote: > Hi Vits, > > Opencores' files includes a model of an I2C slave device. I used this > model to test my modified Opencores' I2C. You connect the data and the > clock of the I2C master to the data and clock of the I2C slave. This is > where the I2C wires are located. > > One thing to note, the provided I2C slave device only has four > registers. You can change the I2C slave device to have more than four > registers. I thought I'd share this with you, because this one took me > by surprise. > > Per your question in regards to the Wishbone interface of the I2C > cores. The Wishbone interface is a backend interface that is defined by > the author of Opencores' I2C. The interface (in this core's case) is > used to control what action the I2C master need to do (e.g. send a > start, send data, look for acknowledge, etc). > > Hope this helps, > -Markus > > vits wrote: > > Thanks for the reply. > > First of all i want to test the i2c bus in verilog.For testing it i > > need a model of EEPROM(or anything else ,but i dont know much) to which > > i apply stimulus and apply the same stimulus to i2c bus and then > > compare the 2 outputs .In i2c rtl given in the opencores.org there are > > seperate signals for wishbone and i2c. i want to know why wishbone > > signals are there if i want to test only i2c bus. > > thanks, > > vitsArticle: 109329
To all,
I've develped a Master peripheral to connect to the Avalon Bus
which interfaces a custom slave peripheral. The Master writes to the
slave peripheral some data using the "writedata" line and by
deasserting the "write_n" signal and asserting "read_n". The Master is
a FSM, which has the following sequence; the first state was a
read-mode state in which I was requesting something from the slave and
then the following state is where I would like to write to the same
slave peripheral some data:
STATE#1
write_n = '1'
read_n = '0'
STATE#2
write_n = '0'
read_n = '1'
The Avalon Bus VHDL code generated by SOPC builder with produces a
VHDL stop error called: "vosq0_fifo_logic_avalonM_writedata did not
heed wait";
where vosq0_fifo_logic is the name of the Master peripheral.
I have extracted the segment of the VHDL code from within the
generated SOPC builder file to show exactly where this comes from. See
below.
process (active_and_waiting_last_time,
vosq0_fifo_logic_avalonM_writedata,
vosq0_fifo_logic_avalonM_writedata_last_time)
VARIABLE write_line3 : line;
begin
if std_logic'((active_and_waiting_last_time AND
to_std_logic(((vosq0_fifo_logic_avalonM_writedata /=
vosq0_fifo_logic_avalonM_writedata_last_time))))) = '1' then
write(write_line3, now);
write(write_line3, string'(": "));
write(write_line3,
string'("vosq0_fifo_logic_avalonM_writedata did not heed wait!!!"));
write(output, write_line3.all);
deallocate (write_line3);
assert false report "VHDL STOP" severity failure;
end if;
end process;
I am trying to figure out what this actually means and don't understand
why this error was generated. Anyone have any idea what this means?
Regards
Pino
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From: Phil Hays <spampostmaster@comcast.net>
Subject: Re: resets on synplicity inferred RAMs
Date: Sun, 24 Sep 2006 09:48:18 -0700
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Xref: prodigy.net comp.arch.fpga:120232
Andreas Ehliar wrote:
> On 2006-09-19, vssumesh <vssumesh_asic@yahoo.com> wrote:
>> One more doubt Ray, I am an FPGA based designer also a beginer. My doubt
>> is if due to some reasons i want a reset signal for a RAM block for
>> which i am ready to sacrifice the area and fanout problem is it possible
>> to create one in ASIC.
>> Sumesh
>
> Suppose you want to reset a RAM memory of 512 kilowords with one reset
> signal and you are writing to it in chunks of 32 bits.
>
> You could design a wrapper around it where you could have one flip flop
> per word that signifies if that particular word is valid or not. Once the
> wrapper gets the reset signal, all flip flops are set to zero. As soon as
> you write to a certain word, the corresponding flip flop is set to 1. Once
> you read from the RAM memory, the wrapper will output all zeroes if the
> signal from the valid flip flop corresponding to the read address is zero,
> otherwise it will output the value from the RAM memory.
>
> This is of course rather hardware intensive because you have to keep track
> of 512 flip flops. It will also increase the critical path of your memory
> readout by quite much. But it will work regardless of how often your
> reset signal is asserted.
A similar scheme would be to use smaller memories (such as 16 bit LUT
RAMs) for the valid bits. The clear will take the number of clock
cycles equal to the size of the smaller memories. This takes rather less
hardware than an array of FFs.
--
Phil Hays (Xilinx, but speaking for myself)
Article: 109330Two more ideas: 1=2E Look at the CCLK signal integrity (double edges) 2=2E You might append a few extra bytes of all-ones to the very beginning and the very end of the bitstream, without changing anything else. But, checking Dout would find all these problems anyhow. It is unbeatable as an analysis tool. Fixing the problem is then another matter. Peter Alfke =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Peter Alfke wrote: > I still remember what we used to suggest 10 years ago: > > Look at the Dout pin. There, the serial bitstream is passed on to the > next device, but only after the device otself has received its > configuration. > So you should see the preamble' length count etc, and then a continuous > High level, until the end of the internal configuration. And then the > remainder of the concatenated bitstream is passed on to the next > device. > > You have one advantage: You have a working board. So poke around on > CCLK and Dout-Din-Dout and observe the traffic, and compare the boards. > You claim that these should be identical devices (although Xilinx made > several different sub-families, they are clearly marked) > There is still the possibility that you bought grey-market or bogus > parts. Do you know the source? > > Bon chance (isn't that what they say?) > Peter Alfke, from home. > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > Jacques GENIN wrote: > > Peter Alfke a =E9crit : > > > I think it's time for you to describe the "badness". > > > The thread gets a bit long in the tooth. :-( > > > Peter Alfke > > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > I designed a PCI board with 3 XC4010E on it > > (PCI with AMCC part, not in FPGA). > > The first FPGA is configured asynchronous peripheral. > > The other FPGA are daisy chained and configured slave > > peripheral (cf. Data book p. 4-74). > > During ten years, I had had no problem with that design. > > Since the beginning of this year, as XC4010 is a > > discontinued part, I buy it more and more often from brokers. > > I got three deliveries of "bad" parts. > > Using those "bad" parts, configuration pins M0, M1, M2, if > > left floating, do not all polarize high as they should, > > because of internal pull-ups. Then, the parts do not enter > > the configuration mode implied by my design. > > If I set external pull-ups, configuration pins polarize > > correctly and configuration process seems to be successful, > > but the behaviour of the part is wrong, ie my board does not > > work. I did not investigate much at this time, but the pins > > seem to remain floating and the parts do not start working. > > Though, these "bad" parts are not counterfeits, as would be > > empty cases, because configuration process progresses > > correctly : DONE raises on time, with no external pull-ups, > > parts may enter master serial with address pins toggling. > > > > The only difference is that "good" parts had mainly been > > delivered in sticks and "bad" parts had always been delivered > > in tapes. > > > > Further, "bad" parts were recent, but seemed older > > (oxyded pins). > > > > I'd like to know whether someone else experienced same > > problem. > >=20 > > Jacques GENINArticle: 109331
I've come to FPGAs from CPLDs and am rapidly realising that a
reasonable (but not complete) knowledge of Verilog is not enough!
So tonight's question is:
How do I set up a balanced input?
I can write (a minimal example to make the point)
############
module top(Q, in, clk);
output Q;
input in;
input clk;
reg Q;
always @(posedge clk)
Q<=in;
endmodule
################
and in PACE I can specify that I want "in" to be- let's say- LVDS_25-
a balanced input type; I can put that input on pin 2- one of a pair.
(Diff Type and Pair Name are not writeable in the Design Object List).
However, when the design has been fitted and routed, I find that pin
3- the other of the pair- is not connected.
What am I missing?
Thank you in anticipation,
Colin
--
Per ardua ad nauseam
Article: 109332OK, I've read the xilinx blurb but I still don't understand the difference between 3 and 3E. If I have enough gates and I/O's for my application, is there any other reason for preferring one over the other - like speed or cost ? regards, DaveArticle: 109333
I'm having trouble getting some lines in a UCF file to be accepted by ISE. The lines are: NET Inst_rio_fo2_top/aurora_module_i/lane_0_mgt_i/RXRECCLK PERIOD=6.4 ns; NET Inst_rio_fo2_top/user_clk_i PERIOD = 6.4 ns HIGH 50 %; INST Inst_rio_fo2_top/aurora_module_i/lane_0_phase_align_i/phase_align_flops_r* AREA_GROUP="PHASE_ALIGN_FO2_GRP"; AREA_GROUP "PHASE_ALIGN_FO2_GRP" RANGE=SLICE_X26Y72:SLICE_X27Y73; INST Inst_rio_fo2_top/aurora_module_i/lane_0_mgt_i LOC=GT_X1Y1; which is for an Aurora core on a 2VP7. Much of this is copied from the sample Aurora stuff generated by the Core Generator. Has anyone else had any issues with this or can anyone see anything obvious. The error occurs on the INST Inst_rio_fo2_top/aurora_module_i/lane_0_phase_align_i/phase_align_flops_r* AREA_GROUP="PHASE_ALIGN_FO2_GRP"; line when it's claimed it could not find the instance of the phase align flops but which are definitely there. TIA, Rog.Article: 109334
"Dave" <dave.garnett@metapurple.co.uk> schrieb im Newsbeitrag news:TZGdnVxMkOOSR4vYnZ2dnUVZ_vmdnZ2d@giganews.com... > OK, I've read the xilinx blurb but I still don't understand the difference > between 3 and 3E. > > If I have enough gates and I/O's for my application, is there any other > reason for preferring one over the other - like speed or cost ? > > regards, > Dave > > Spartan3E is advertised as FPGA with 25% more logic ressources and 25% less cost than Spartan3. Check your distri or digikey about that. Some hidden facts: - Spartan3E has less I/O's than Spartan3, but has additional input only pins. If your application can use these inputs - e.g. for adc's - you have more available user pins than on S3. - Spartan3E has fewer packaging options, e.g. the XC3S500E is not availlable in a TQ144 package. The S3 XC3S400 has a TQ144 option. - Spartan3E has muxed configuration pins which can be advantage or disadvantage, depending on design. The spi flash support is a main advantage for system cost savings. Further on parallel memory is supported for configuration. - Spartan3E has improved multipliers. Check a simple design with a*b (2 72 bit vectors), the logic ressources on Spartan3E are less. There are other differences, like configuration bit stream length, etc., they should be collected, and put in the FAQ. MIKE -- www.oho-elektronik.de OHO-Elektronik Michael Randelzhofer FPGA und CPLD Mini Module Klein aber oho !Article: 109335
rickman wrote: > I am trying to look at a failed timing path in the floorplanner and I > expected to be able to click on a link in the timing report and be > taken to a selected net, logic or the entire path depending on the > link. Instead it reports some errors about not being able to open a > socket and crashes with the following error message... > > FATAL_ERROR:GuiUtilities:WinApp.c:710:$Revision - This application has > discovered an exceptional condition from which it cannot recover. > Process will terminate. ... > > The timing analyzer terminates. Anyone know what this is about? ISE (like a lot of other tools) uses IPC between it's various tools. I noted that in an earlier thread you had certain things blocked at the firewall - ISE can croak if it doesn't have sufficient access rights (because rather than use the localhost convention they use your actual IP - gethostbyname and so forth - this is very common [1]) then it will just die because the code does not trap for the failure. You may need to permit it some internet access even though it really want to merely communicate with some other process on the same system. [1]. The Cadence tools (OrCad, Allegro, Spectra) do exactly the same. In fact, these need to be *internet servers* to operate properly - a real pain. Cheers PeteSArticle: 109336
Things I like about Spartan-3E V Spartan-3 Config from SPI or Flash. - Cheap and usually only needs one device. The differential terminator. Cost is slightly better? - Does depend on project needs which is best. The magicbox gate to speed up PCI. What I don't like No DCI The number of input only pins. Why could these not have been clock pins and left us more general I/O. There are only 4 banks of I/O that limit combinations when you have a multvoltage I/O system. For example you could have Flash at 3.3V, DDR2 at 1.8V, LVDS at 2.5V in a system. In this kind of system you can't always use the left overs on a bank on one particular voltage. Spartan-3 wins because it has 8 banks and less lossy in this situation. The general architecture and internal speeds are essentially the same and if it were available I would love a Spartan-3 with a SPI load. Unless I am totally penny pinching then my choice would almost always be Spartan-3. John Adair Enterpoint Ltd. Dave wrote: > OK, I've read the xilinx blurb but I still don't understand the difference > between 3 and 3E. > > If I have enough gates and I/O's for my application, is there any other > reason for preferring one over the other - like speed or cost ? > > regards, > DaveArticle: 109337
Hi Alfmyk, Alfmyk wrote: > I have seen that related to uBlaze configuration (HW/SW FPU, Barrel shifter ON/OFF, and so on...) there are different directives to inform compiler.Example "-mhard-float" (using HW floating point). My question: these type of directives are ONLY for target (I mean used) that is for the linker command or the directives are also used in compiling time? I mean obj code are different if different are condition of "-m<..>" ? For me is important to know if I must use this compile setting also in my external library. It is important to pass all CPU-specific flags (soft/hard float, HW mul/div/shift) to both the compiler *and* the linker. If you are doing a compile and link in one pass, then it's not a problem. But Makefiles that do seperate compile and link phases need to be careful. mb-gcc uses the multilib mechanism with different versions of libc and libgcc compiled for all possible CPU-flag combinations. If you don't pass the CPU options to the linker, it defaults to linking against fully SW versions, which is not what you want. Regards, JohnArticle: 109338
<pinod01@sympatico.ca> wrote in message news:1159114942.865932.288610@i42g2000cwa.googlegroups.com... > To all, <snip> > The Avalon Bus VHDL code generated by SOPC builder with produces a > VHDL stop error called: "vosq0_fifo_logic_avalonM_writedata did not > heed wait"; > > where vosq0_fifo_logic is the name of the Master peripheral. > It means that the master changed the state of the Avalon 'writedata' output (even if only a glitch) while the 'waitrequest' input was still active....can't do that, address, command (i.e. read and write) and writedata must all remain stable if waitrequest coming in is active KJArticle: 109339
Handy link for this entire thread: http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/6d594b2ab04beb4b/e39055a323c18cd6#e39055a323c18cd6 Xilinx tech. support said to separately register each level of logic, since I have some lines of up to four xor statements being assigned to a signal. I tried that, but it didn't help. However, the sub-module in which the mapper is connecting two of my output registers together, works on its own in in a separate project in post-map simulation when those output registers are treated as port signals. It works on its on without or without the added registers that do one xor at a time, but still cross-connects with or without the added registers when used as a submodule of user_logic. Clearly I am dealing with undocumented features of the mapper; certain coding techniques are required in order for it to accomplish my intent. Xilinx really should be documenting these requirements; it's not fair to tell people that "the problem is with the way you write your VHDL" otherwise. Documentation for synthesis and translate is much better. -JamesArticle: 109340
Hi I'm trying to make my XtremeDSP board non-volatile. http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=DO-DI-DSP-DK4&BV_SessionID=@@@@0949117064.1159147457@@@@&BV_EngineID=cccjaddillkdjjgcefeceihdffhdfjf.0 Since the board does not come with any platform flash to load configuration on power up, i'm currently looking at the system ACE to solve this problem. I have gone thru the System ACE CF solution and have some question about this. i guess the first question is: is this possible? i mean, can i just wire up the pins from the chip of the system ACE to the JTAG port on the board (provided i have all other connection right)? Also, I saw that I may need to wire up the ~PROGRAM and ~INIT pins to the System ACE. Is this necessary? i'm not too familiar with the JTAG port's specification. I ask this because I own other FPGA board and to program this board, these are the only pins connected: TMS, TDI, TDO, TCK, GND, VDD. lastly, is there any ready-made board that does this? a small pcb with mounted:System ACE chip, Compact Flash socket, voltage regulators, etc, such that i can just plug it into my jtag port? I couldnt find it anywhere.. Alright, thank you very very very much tejoArticle: 109341
I think the concept is really simple. They provide you the precompiled hw bit file, so you don't need any vhdl development (ISE or EDK). The only thing you need is a free mb-gcc to generate the elf file and use dat2mem to merge elf with the precompiled hw bit file. Of course you can only use the predefined peripherials, and Antti must provide this precompiled hw bit file for every single supported device. You save a bunch of money spent on EDK and time not to worry about setting up the peripherials As Antti said this is a alternative to people who wants to use the FPGA as a uC (and keep the option open to implement hw related stuff in the FPGA later on). But maybe I'm wrong because I haven't tried it yet. :) Zoltan rickman wrote: > ziggy wrote: > > In article <1158822468.138975.247720@h48g2000cwc.googlegroups.com>, > > "Antti" <Antti.Lukats@xilant.com> wrote: > > > > > ziggy schrieb: > > > > > > > In article <1158770147.385889.73830@m73g2000cwd.googlegroups.com>, > > > > "Antti" <Antti.Lukats@xilant.com> wrote: > > > [snip] > > > > If so, people like me will need to stick to other 'free' cores. > > > > > > Hi ziggy, > > > > > > all people like you can stick to any cores of your liking when doing > > > HDL or FPGA designs as the MicroFpga can *NOT* be used with > > > any kind of HDL flow at all. No synthesis, no place and route! > > > > > > Just take an FPGA and GCC compiler. > > > No FPGA vendor tools involved in the process flow: > > > 1) write your C program > > > 2) compile with GCC > > > 3a) merge ELF or bin into BIT or > > > 3b) download over JTAG or serial > > > > > > 4) your C programs runs > > > > > > in any supported FPGA > > > on any board or hardware it is in. > > > > > > Antti > > > > Ah, i think i understand now.. its running c-code directly on the > > hardware.. > > I don't think it is that simple. At least I don't think this is the > equivalent of Handel C which can compile your C code to a bit file to > load into the FPGA just like an HDL bit file. That would require a lot > of knowledge about the internals of the FGPA and would be different for > every single one! I expect they are doing something where they load a > fixed set of gateware into the FPGA which is perhaps like a > reconfigurable processor rather than a fixed instruction set. But I am > speculating. I just don't believe they have obtained all the info to > generate bit files for FPGAs. That is sort of the "Holy Grail" of open > source FPGA development software. Instead they use JBITs on Xilinx and > something equivalent on Altera devices. I believe each of these > programs have some limitations for this sort of thing and licensing may > be the major issue for open source people.Article: 109342
Antti wrote: > MicroFpga makes an FPGA to look like an MCU, and makes it programmable > as it would be a normal MCU without requiring any HDL knowledge or FPGA > implementation tools. Cute idea Antti !! Pregenerated, placed, and routed FPGA MCU's with a tool to install the program binary into the bitstream, editing the ROM image for the MCU. Hobby level access to cheap FPGA parts and boards, and even useful for embedded HW designers gun shy about FPGA development. .... certainly Have Fun with this one!!Article: 109343
Handy link for this entire thread: http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/6d594b2ab04beb4b/e39055a323c18cd6#e39055a323c18cd6 I tried adding a separate level of registering in my main line VHDL code and was trying to test it when the ModelSim simulator died. No clock; therefore no signal processing. The transcript (output window) looks normal and ends up with: # ** Failure: Simulation successful (not a failure). No problems detected. # Time: 1320 ns Iteration: 0 Process: /user_logic_tb/line__94 File: user_logic_tb.vhw # Break at user_logic_tb.vhw line 273 # Simulation Breakpoint: Break at user_logic_tb.vhw line 273 # MACRO ./user_logic_tb.fdo PAUSED at line 16 Both post-Map and behavioral simulation show no clock and no signal processing; all flat lines all of a sudden. I'm looking at reinstalling. I'm using the ModelSim XE III 6.1e starter edition. Does anyone know how to fix this without reinstalling? Also in regards to my previous message: Xilinx tech. support said to separately register each level of logic, since I have some lines of up to four xor statements being assigned to a signal. I tried that, but it didn't help. ...but still cross-connects with or without the added registers when used as a submodule of user_logic. Would anyone have some suggestions about how to write the VHDL so it won't do that? Thanks in advance, -JamesArticle: 109344
Hello , I was wondering if anyone has any ideas on how I would got about generating a core. I've currently having a problem attaching my nco component to my top level entity, after running the nco by itself , everything seems to work successfully , but after I attach it, i'm experiencing strange behavior and was wondering it the synthesizing stages isn't meeting proper constrains. If generating a core isn't possible , how can I optimize the way the nco is implemented into the design ? Thanks in advanceArticle: 109345
On 19 Sep 2006 21:58:30 -0700, "Ali" <sadatakhavi.ali@gmail.com> wrote:
>What id the defference between CPLD and FPGA ?
>
>Except Speed ?
Maybe the FAQ can help:
http://www.fpga-faq.org/FAQ_Pages/0007_Device_type_comparisons.htm
===================
Philip Freidin
philip.freidin@fpga-faq.org
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Article: 109346sutejok schrieb: > Hi > > I'm trying to make my XtremeDSP board non-volatile. > http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=DO-DI-DSP-DK4&BV_SessionID=@@@@0949117064.1159147457@@@@&BV_EngineID=cccjaddillkdjjgcefeceihdffhdfjf.0 > > Since the board does not come with any platform flash to load > configuration on power up, i'm currently looking at the system ACE to > solve this problem. I have gone thru the System ACE CF solution and > have some question about this. > > i guess the first question is: is this possible? i mean, can i just > wire up the pins from the chip of the system ACE to the JTAG port on > the board (provided i have all other connection right)? > > Also, I saw that I may need to wire up the ~PROGRAM and ~INIT pins to > the System ACE. Is this necessary? i'm not too familiar with the JTAG > port's specification. I ask this because I own other FPGA board and to > program this board, these are the only pins connected: TMS, TDI, TDO, > TCK, GND, VDD. > > lastly, is there any ready-made board that does this? a small pcb with > mounted:System ACE chip, Compact Flash socket, voltage regulators, etc, > such that i can just plug it into my jtag port? I couldnt find it > anywhere.. > > > Alright, thank you very very very much > > tejo basically, yes. if you dont have prog_b connected then pushing reconfig button on the base board will not force systemACE to reconfigure systemACE chips cost 45USD and are not obtainable in less quantity then 90, so your best bet is to buy memec (now avnet) systemACE P160 module, it costs some 160 USD optionally you can write systemACE player for some small micro and connect that JTAG port. if you are interested in that solution please contact me AnttiArticle: 109347
Hi. Thanks Zara & Vasanth.
Now I'm using EDK 8.1.02i and so I assume it's possible run C++ routines. Nevertheless using a very simple class: class Cliente { public: char name[20]; char surname[20]; void insert_name( ); };
and generating an object with new keyword: Client *client; client = new Client( );
I get this error: undefined reference to `operator new(unsigned long)' collect2: ld returned 1 exit status make: *** [Application/executable.elf] Error 1
should I use the mb-g++ compiler instead of mb-gcc? What else?
Thanks again.
Regards, Al.
Article: 109348
On Mon, 25 Sep 2006 00:55:34 -0700, Alfmyk <alfmyk@hotmail.com> wrote:
>Hi. Thanks Zara & Vasanth.
>
>Now I'm using EDK 8.1.02i and so I assume it's possible run C++ routines. Nevertheless using a very simple class: class Cliente { public: char name[20]; char surname[20]; void insert_name( ); };
>
>and generating an object with new keyword: Client *client; client = new Client( );
>
>I get this error: undefined reference to `operator new(unsigned long)' collect2: ld returned 1 exit status make: *** [Application/executable.elf] Error 1
>
>should I use the mb-g++ compiler instead of mb-gcc? What else?
>
>Thanks again.
>
>Regards, Al.
Either you tell the compiler to use the correct libraries, or you
provide the new functions. I do the second, but the first is easier.
mb-gcc will call mb-g++ when the input is *.cpp, and the proof is that
it is telling you that operator new is not found. If it had been
compiled as C (ant not C++), the problem would be a simple syntax
error.
zara
Article: 109349Hello experts, I am a final year student and working on my senior design project. I need PCI Master core and unfortunately I cannot buy any licensed core because of their high price. I have seen opencores.org PCI bridge but it has few problems 1. Its test bench is too complex to understand. I was expecting some black box sort of interface. 2. Its driver is written in linux, but I have developed my software part in MS Visual C-6, soI need windows driver. If someone has cleaned and simple version of opencores PCI core or someother PCI core please send me that at madnan.rashid@gmail.com. I also need driver preferrably for windows. Your timely help will enable me to solve my problems. And yes, I will acknowledge source of this PCI core and driver in my project report. with best regards Adnan
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