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>> does somebody know a distributor for Spartan3e 500 in a pq208 or a >> tq144 housing? >> >> thanks >> urban >Why, oh why, doesn't Xilinx offer these parts in *any* quantity? I can >think of lots of neat projects for FPGA's, but finding non-BGA parts is >next to impossible. As it is, I find ways to lash eval and demo boards >together. Maybe Actel have something nice ;)Article: 108626
Sandeep Dutta schrieb: > In most cases the memory has to be of a certain size for the > tool to infer a BlockRAM. Smaller memories are implemented as > distributed RAM >=20 > Sandeep Hi Sandeep, of what size are you talking ? Andr=E9Article: 108627
Ben.Nader@gmail.com wrote: > Hi > > I am trying to programm a XC2S300E through a microcontroller using the > Slave p mode. > I make a ufp file ( which is just a hex file) of my program using > xilinx ISE 8.1 and then using the microcontroller and and slave mode > signals I send it to the fpga. > I have all this working for another design, which is exactly the same > micro but Xc2S150E FPGA. but I can not get this to work on XC2S300E. > > here is what happens: > > 1. I pulsed the ~prog line low and then high. ( to start the clearing > configuration memory) > 2. I see FPGA lowers INIT line ( it shows it is busy clearning the > memory) > 3. INIT goes high > 4. I am sending Clock along with 8bit data on D[7:0] and CCLK. > 5. I see INIT stays high ( so I thought CRC check was okay) > 6. DONE stays low, I never see it coming up. > > after extensive search on the Xilinx website I read something that I > could have a timing problem and I should keep sending CCLK till DONE > goes high. so I tried just running CCLK for like a full SECOND after I > was done sending my real data, and I still never saw DONE going high. > > I purposly changed my hex file to see if I the CRC error happens and > INIT goes low. but I never saw this. INIT was high the entire time > after the initial memory clearning process( FPGA pulled it low then) > so this means I am not as far as CRC test on the flow chart. I am > wondering If FPGA thinks that it is not at the end of the file yet or > if it is reading anything at all. > I also checked the number of bits on hex file and it matches the > number on the Xilinx Datasheet. so I know I build the correct hex > file. > > I have 3 different boards with XC2S300E that I have this problem with. > so I doubt I have a connectivity issue or anything like that. > > I also double checked my pull up and downs like 100 times by now. they > all makes sense and match my board with XC2S150E( which I can > configure with no problem) > > Do you guys have any ideas where the problem coming from?.. what other > things I should look at? > > I appreciate you taking the time and reading my long email and helping > me > > Ben I use a similar scheme for an XC2S200E and a '50E, except that I use a single bit wide data path. Initially I had similar problems. I found that the power supply rise was not monotonic, and this seemed to upset things. I also found that sometimes if the configuration process failed then the fpga needed to be power cycled before it would behave - so I implemented a series fet to do precisely that :-] The whole system is in a distributed noisy environment, and now I basically turn on the main power with the fpgas powered off, wait for everything to settle, then turn on and configure fpgas in a staggered sequence. Crude it may be, but it works in the field ... DaveArticle: 108628
Hi, In article <1158142703.3706.0@demeter.uk.clara.net>, removethisthenleavejea@replacewithcompanyname.co.uk says... Commercial bit - If you don't find what you need we > specialise in doing derivatives quickly too. The best example, in the public > domain of what we do in fast turn, is our MINI-CAN board that had a design > cycle, manufacture, 5 days of bench test and boards delivered to the > customer in 18 calendar days. That's pretty impressive! Can you comment on what schematic capture/board layout progarms you're using? John.Article: 108629
Thank you very much for the explantions. The explantions I read here are better than most electronics text books! :) > JJ, > most voltage regulator can only drive current into the load. They > cannot regulate the voltage when the current flows"backwards" into the > regulator. (But, as mentioned, there are some "DDR" regulators that can > source and sink,) > > Yhe National guy looked at this as a regulator protection question, and > answered accordingly. He did not understand the real issue, that we > need to prevent the regulator output from going higher than specified, > even when the current is reversed. > > The primitive cure is a bleeding resistor to ground, as Austin > suggested. A more sophisticated solution is a "bidirectional" > regulator, apparently called DDR regulator as described in this thread. > > If you have a EE degree, this should really be clear by now... > Peter Alfke, Xilinx > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > jidan1@hotmail.com wrote: > > Thanks all for your replies. > > Peter, Austin, > > > > I will be using voltage regualtors from national semiconducter and so I > > posted my question to one of the national engineers. I posted a quoted > > passage from xilinx database answer which says that xilinx recommends a > > parallel resistor for power regualtion purposes. He recommended using a > > diode rather than a parallel resistor and he doesnt understand why > > xilinx prefers using a parallel resistor, although a diode is more > > power efficient. > > You can read our conversition here: > > http://wwwd.national.com/national/powermb.nsf/8178b1c14b1e9b6b8525624f0= 062fe9f/ea579526ac937540882571e60071f60a?OpenDocument > > > > > > Peter Alfke schrieb: > > > > > The resistor value is a compromise between speed and current forced > > > into the pin. > > > The driver output impedance is probably below 10 Ohm. With a total lo= ad > > > capacitance of 30 pF that creates an output time constant of 300 ps, > > > pretty fast. > > > With a 1 kilohm resistor directly attached to the FPGA pin, that pin > > > has a capacitance of 10 pF. Times 1 kilohm that is a time constant of > > > 10 ns, which is too slow in some cases, but probably fast enough in > > > your case. And it limits the per-pin current forced into the FPGA to > > > about 2 mA. > > > > > > The regulator usually cannot absorb current flowing backwards, so you > > > must make sure that the current maintains its direction when the > > > largest number of interfaces is High. > > > When the current reverses direction, the voltage would rise, and might > > > destroy the FPGA (unlikely, but possible). > > > These are some of the nitty-gritty considerations that pay your (and > > > my) salary... > > > Peter Alfke > > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > > jidan1@hotmail.com wrote: > > > > Thank you Austin and Peter for you replies. > > > > > > > > I still have 2 questions > > > > > > > > 1)a) So, you suggest using a 1k ohm serial resistor to interface th= e 5V > > > > signal to 2.5V input. May I know how you came to this number? > > > > b) For the 5V -> 3.3V interface, xilinx application suggests a > > > > Rser=3D300Ohm. Should I also replace this with a Rser=3D1kohm? > > > > > > > > 2)Why use a parralell resistor to the voltage regulator and waste p= ower > > > > to handle the reverse current. Why not just add a reverse biased > > > > schotkey diode from the output to the input of the voltage regulato= r? > > > > > > > > Austin Lesea schrieb: > > > > > > > > > jidan, > > > > > > > > > > Peter makes a good point: if the resistance is too low, then you= are > > > > > injecting current into the 2.5 V supply, and it may begin to drif= t up, > > > > > and out of regulation. > > > > > > > > > > One way to avoid that, and to avoid any rail supply being driven = above > > > > > its intended output, is to balance the injected current with a si= mple > > > > > resistor across the power supply, present all the time. > > > > > > > > > > So, if you think you will inject 100 mA worst case into the 2.5V = rail, > > > > > then plan on having a load of at least 100 mA on the 2.5 volt sup= ply. > > > > > If the 2.5 volt supply has a minimum normal load of 50 mA, then y= ou will > > > > > need an additional 50 mA load, just in case. 2.5V/.05=3D50 ohms = (51 ohms, > > > > > nearest 5% value). > > > > > > > > > > All this because regulators are good at regulating a load, but in= capable > > > > > of regulating when you source current into there output terminal. > > > > > > > > > > Austin > > > > > > > > > > Peter Alfke wrote: > > > > > > jidan1@hotmail.com wrote: > > > > > >> Hi, > > > > > >> > > > > > >> I would like to configure a spartan-3 FPGA with an 5V CMOS > > > > > >> microcontroller. I have read xilinx database answer regarding = how to > > > > > >> make 3.3V I/O input pins 5V tolerant with a serial resistor (3= 00Ohm). > > > > > >> > > > > > >> 1) Can also the confg. dedicated pins made 5V tolerant through= a serial > > > > > >> resistor although they are powered from 2.5V? (I calculated th= is an I > > > > > >> came to Rser=3D220OHM) > > > > > >> 2) The VIH of my microcontroller is 3V, that of spartan-3 I/O'= s is > > > > > >> (VCCO=3D3.3V) is 2.9V. Do I need level-shifters to drive my = =B5C? If yes, > > > > > >> what IC's would you recommend? > > > > > >> > > > > > >> Regarding 1: > > > > > > I would use 1 kilohm. No need to push more current than necessa= ry. > > > > > > Regarding 2: > > > > > > You quote worst-case numbers that assum lowest Vcc on the FPGA = and > > > > > > higest possible Vcc on the uP. > > > > > > Keep the FPGA fed with at least 3.2 V, and you will see that sa= me > > > > > > voltage on the output (this is CMOS !), and keep the uP Vcc sli= ghtly > > > > > > below 5V. > > > > > > But you will not have much noise immunity. > > > > > > Peter Alfke > > > > > >Article: 108630
Thanks a lot for your replies, I could solve this problem by implementing some Multipliers as LUTs like Brian proposed. Now this occurs not any more, but the Routing lasts for 16 Hours until now :) Regards, Peter Ray Andraka schrieb: > Ray Andraka wrote: > > > > > ...thus if the > > multiplier is used it must take its inputs from those block ram bits. > > > > To clarify: if both the block RAM and multiplier are used at a site, and > the block Ram has 36 bit outputs, the multiplier must use those outputs > as its input.Article: 108631
David Ashley wrote: > However this is very easy, you just create module3 that > instantiates module1 and module2. > Some IO-multiplexing will have to be done too, I suggest. what kind of modules are you thinking of, requiring partial downloading ?Article: 108632
"David Ashley" <dash@nowhere.net.dont.email.me> wrote in message news:Ec2dnRnHFpHMYpXYnZ2dnUVZ_qKdnZ2d@adelphia.com... >>>ieee.numeric_std is an honest standard, and won't give you grief if you >>>have a mix of signed and unsigned in the same entity, and behaves the >>>same regardless of whose tools you use. Use that. > > Help! > > The new code I'm working up uses: > > A) > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all > > fine. But when I try to integrate it with code that uses: > > B) > library ieee; > use ieee.std_logic_1164.all; > use ieee.std_logic_arith.all; > use ieee.std_logic_unsigned.all; > > Everything goes to crap. I use unsigned in my new code, but > the existing code's "unsigned" doesn't match, they don't > link up. Meaning I can't port map entities from my code > using (A) into the project that uses (B). > > There is a lot of existing code, such as a model for a > ddr: mt46v16m16.vhd > > which I need for simulation. That all uses (B). > > How can I get around this problem? I tried converting > the code that uses (B) into using (A), but it's over my head > and was just creating one compile error after another... > > To get it to build I converted my code to (B) and that > works fine (and is easy) but I don't want to start > down the dark path... > > Thanks-- > -Dave > > -- > David Ashley http://www.xdr.com/dash > Embedded linux, device drivers, system architecture Probably you can try to change the interfaces between modules to use only std_logic (or std_ulogic, depending on what you want to do) and only use signed/unsigned for the internal signals. In fact, some people insist on this approach/style emphasizing that the interfaces only carry logical values and the "interpretation" of what these logical values actually mean, should only be done inside the modules. Regards, Arash SalarianArticle: 108633
It seems we are all struggling the same problems. When you want to do it yourself you are limited to small FPGAs, which are very hard to get. Guru u_stadler@yahoo.de wrote: > hi > > does somebody know a distributor for Spartan3e 500 in a pq208 or a > tq144 housing? > > thanks > urbanArticle: 108634
An affordable and VERY compact solution is a Avnet Virtex-4FX12 MiniModule with a PowerPC, Giga LAN, 64MB DDR, 4MB flash and a price of 250$. There might be also enough logic for a simple DSP to preprocess data for a final processing in the PPC. Cheers, Guru Markus Fuchs wrote: > In the company I'm working for we're using DSPs and FPGAs to develop motion > controllers. Since we're doing all the position, speed, torque and current > control stuff in software, we're in need of powerful devices. > > We're considering to get rid of the DSP and change to a SoC design in > future. Therefore I would be interested if anyone can suggest an affordable > SoC development board with an ambedded (digital signal) processor to > evaluate the possiblities of SoC. I'm especially interested in Altera boards > as we're already using them in our old designs. What FPGA should we choose? > Cyclone, Cyclone II, Stratix? What embedded processor fits best to motion > control needs? NIOS, ARM, PowerPC? > > I'm looking forward to your suggestions. TIA. > > Markus > > -- > Markus Fuchs - http://www.yeahware.comArticle: 108635
A am also a Virtex-4 MiniModule user. I also want to use Linux on it. Where did you get this Linux reference design? Cheers, Guru Anonymous wrote: > I have a memec mini-module board. I've loaded and run the reference design > and I am able to boot all the way into the Linux prompt. However, my design > doesn't need ethernet so I deleted it. Now it doesn't even run the code in > the initial BRAM successfully. I've traced the code and it seems to end up > at the _exit crt function. (BTW, is there a way to get the c symbols in > XMD?) > > Any ideas why removing the ethernet would clobber the system to the point > that even the uart doesn't work? > > Thanks, > ClarkArticle: 108636
I agree with Arash, it's the best method IMHO. If you're stuck, make a wrapper entity that converts them. Ben "Arash Salarian" <arash.salarian@epfl.ch> wrote in message news:1158233155_15@sicinfo3.epfl.ch... > "David Ashley" <dash@nowhere.net.dont.email.me> wrote in message > news:Ec2dnRnHFpHMYpXYnZ2dnUVZ_qKdnZ2d@adelphia.com... >>>>ieee.numeric_std is an honest standard, and won't give you grief if you >>>>have a mix of signed and unsigned in the same entity, and behaves the >>>>same regardless of whose tools you use. Use that. >> >> Help! >> >> The new code I'm working up uses: >> >> A) >> library ieee; >> use ieee.std_logic_1164.all; >> use ieee.numeric_std.all >> >> fine. But when I try to integrate it with code that uses: >> >> B) >> library ieee; >> use ieee.std_logic_1164.all; >> use ieee.std_logic_arith.all; >> use ieee.std_logic_unsigned.all; >> >> Everything goes to crap. I use unsigned in my new code, but >> the existing code's "unsigned" doesn't match, they don't >> link up. Meaning I can't port map entities from my code >> using (A) into the project that uses (B). >> >> There is a lot of existing code, such as a model for a >> ddr: mt46v16m16.vhd >> >> which I need for simulation. That all uses (B). >> >> How can I get around this problem? I tried converting >> the code that uses (B) into using (A), but it's over my head >> and was just creating one compile error after another... >> >> To get it to build I converted my code to (B) and that >> works fine (and is easy) but I don't want to start >> down the dark path... >> >> Thanks-- >> -Dave >> >> -- >> David Ashley http://www.xdr.com/dash >> Embedded linux, device drivers, system architecture > > Probably you can try to change the interfaces between modules to use only > std_logic (or std_ulogic, depending on what you want to do) and only use > signed/unsigned for the internal signals. In fact, some people insist on > this approach/style emphasizing that the interfaces only carry logical > values and the "interpretation" of what these logical values actually > mean, should only be done inside the modules. > > Regards, > Arash Salarian >Article: 108637
Antti Lukats wrote: > "John Williams" <john.williams@petalogix.com> schrieb im Newsbeitrag > news:newscache$q14h4j$xmi$1@lbox.itee.uq.edu.au... > > Hi David, > > > > David wrote: > > > >> i am looking for any step by step guide to use uclinux on the starter > >> kit. > > > > A Linux-ready reference design for the Spartan3E500 starter kit is > > available now > > from PetaLogix: > > > > http://www.petalogix.com/news_events/Spartan3E500-ref-design > > > > Regards, > > > > John > > -- > > Dr John Williams > > www.PetaLogix.com > > (p) +61 7 33652185 (f) +61 7 33654999 > > > > PetaLogix is a trading name of UniQuest Pty Ltd > > Thanks Jihn > > the 1600 thing was really useless, as you seem to be only one havng those > s3e-1600 > boards despite the fact that Xilinx website says that 'coming in June' > > Antti Digilent has a 3S1600E board out right now: http://www.digilentinc.com/Products/Detail.cfm?Prod=S3E1600&Nav1=Products&Nav2=Programmable The best part is, they actually fixed some of the gripes I had about the previous 3S500E board.Article: 108638
David Ashley wrote: > jrgodara@gmail.com wrote: > >>Hi all, >>i am beginner in FPGA and i have a query about downloading FPGAs. >>i have a module1 and downloaded on device. now my question is that a >>module2 can be downloaded >>on same device(if free space available), then how. >>also i want to see result of both module simultaneosly. >>Regards >>J.Ram >> > > > I think partial reconfiguration aside, you can only download > one module at a time onto an fpga, and your module would have > to be the merging of module1 and module2 together. > However this is very easy, you just create module3 that > instantiates module1 and module2. > > Regarding partial reconfiguration, I don't know firsthand, just > theory. The idea is part of the fpga keeps its programming, > and you can reprogram some other part. So the part that > remains constant can be doing the critical system stuff, > and the other part can be swapped in and out as needed for > the task at hand. > > My impression partial reconfiguration is a relatively new > development, and not all devices support it, but a whole lot > of people want it. > > -Dave > Partial reconfiguration itself is not new, but the tools' ability to handle it is. The design flow for partial reconfiguration is not for the faint of heart. Unless you have a reason to be swapping partial bitstreams in and out in many different combinations, you are generally better off using full bitstreams.Article: 108639
David Ashley wrote: >>>ieee.numeric_std is an honest standard, and won't give you grief if you >>>have a mix of signed and unsigned in the same entity, and behaves the >>>same regardless of whose tools you use. Use that. > > > Help! > > The new code I'm working up uses: > > A) > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all > > fine. But when I try to integrate it with code that uses: > > B) > library ieee; > use ieee.std_logic_1164.all; > use ieee.std_logic_arith.all; > use ieee.std_logic_unsigned.all; > > Everything goes to crap. I use unsigned in my new code, but > the existing code's "unsigned" doesn't match, they don't > link up. Meaning I can't port map entities from my code > using (A) into the project that uses (B). > > There is a lot of existing code, such as a model for a > ddr: mt46v16m16.vhd > > which I need for simulation. That all uses (B). > > How can I get around this problem? I tried converting > the code that uses (B) into using (A), but it's over my head > and was just creating one compile error after another... > > To get it to build I converted my code to (B) and that > works fine (and is easy) but I don't want to start > down the dark path... > > Thanks-- > -Dave > Change the ports on all the entities to std_logic or std_ulogic and std_logic_vector or std_ulogic_vector, then assign the signed/unsigned inside, that way they are compatible with either library.Article: 108640
Hi Andre >> of what size are you talking ? In your example "ls_fifo_reg" must be declared as some sort of array. If the size is very small (not sure of the exact number) then it will synthesize as distributed ram (LUTs). You will need to follow the template very closely, the "reset" on "DataOut" may prevent BlockRAM inferencing as well. One other point, your "attribute" is attached to "FIFO_r" not ls_fifo_reg. SandeepArticle: 108641
Nevermind. When I deleted the ethernet phy I also deleted my serial port pin constraints. So it was working, I just couldn't see the output. Thanks, Clark "Anonymous" <someone@microsoft.com> wrote in message news:wISNg.33306$lk6.17017@tornado.southeast.rr.com... > I have a memec mini-module board. I've loaded and run the reference design > and I am able to boot all the way into the Linux prompt. However, my design > doesn't need ethernet so I deleted it. Now it doesn't even run the code in > the initial BRAM successfully. I've traced the code and it seems to end up > at the _exit crt function. (BTW, is there a way to get the c symbols in > XMD?) > > Any ideas why removing the ethernet would clobber the system to the point > that even the uart doesn't work? > > Thanks, > Clark > >Article: 108642
Handy link for this entire thread: http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/6d594b2ab04beb4b/e39055a323c18cd6#e39055a323c18cd6 Thank you for your advice! I'll try to keep this thread posted if and when I find answers. Best regards, -JamesArticle: 108643
Hi all, Is there any general tips of reading Verilog code. I want to collect these tips to accelerate code reading speed. For example, shall I read the input signal first and trace them until output? And shall I read from top to bottom or from bottom to top? And shall I read the 'always' block first? Any questions and comments are welcome :) Best regards, DavyArticle: 108644
hi i had the same problem, but i solved it following the instruciont in the answer 23541 in the xilinx support database the link: http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=23541 Andreas Ehliar wrote: > On 2006-09-13, Christian Metzler <cpmetz@usenet.cnntp.org> wrote: > > Anyone got an Idea? Please don't tell to switch to Windows (everything > > works under XP 32bit, so no bad Cable), since we currently only have > > XP-x64 for this machine which is not supported by the Xilinx-Tools... > > Unfortunately your experience in Linux mirrors mine. My workaround is to > boot windows to download the cypress firmware and then reboot into Linux. > But this won't work for you since you only have XP-x64... > > I'm guessing now but the following workaround might work for you: > * Connect the cable to a powered USB hub. > * Connect the USB hub to a Win XP 32bit machine. > * Wait until the firmware is loaded. > * Reconnect the USB hub to your Linux machine and hope that the firmware > is still loaded. > > I haven't tried this myself so I don't know if it will work for you. > > I would be really interested in hearing someone from Xilinx saying that > "Yes, the USB platform cable is really working in Linux even if you > don't load Windows first." Because in that case I could try the same > kernel version and same fxload version they are using to see if that > is the problem we are having. > > /AndreasArticle: 108645
Arash Salarian wrote: > "David Ashley" <dash@nowhere.net.dont.email.me> wrote in message > news:Ec2dnRnHFpHMYpXYnZ2dnUVZ_qKdnZ2d@adelphia.com... > >>>>ieee.numeric_std is an honest standard, and won't give you grief if you >>>>have a mix of signed and unsigned in the same entity, and behaves the >>>>same regardless of whose tools you use. Use that. >> >>Help! >> >>The new code I'm working up uses: >> >>A) >>library ieee; >>use ieee.std_logic_1164.all; >>use ieee.numeric_std.all >> >>fine. But when I try to integrate it with code that uses: >> >>B) >>library ieee; >>use ieee.std_logic_1164.all; >>use ieee.std_logic_arith.all; >>use ieee.std_logic_unsigned.all; >> >>Everything goes to crap. I use unsigned in my new code, but >>the existing code's "unsigned" doesn't match, they don't >>link up. Meaning I can't port map entities from my code >>using (A) into the project that uses (B). >> >>There is a lot of existing code, such as a model for a >>ddr: mt46v16m16.vhd >> >>which I need for simulation. That all uses (B). >> >>How can I get around this problem? I tried converting >>the code that uses (B) into using (A), but it's over my head >>and was just creating one compile error after another... >> >>To get it to build I converted my code to (B) and that >>works fine (and is easy) but I don't want to start >>down the dark path... >> >>Thanks-- >>-Dave >> >>-- >>David Ashley http://www.xdr.com/dash >>Embedded linux, device drivers, system architecture > > > Probably you can try to change the interfaces between modules to use only > std_logic (or std_ulogic, depending on what you want to do) and only use > signed/unsigned for the internal signals. In fact, some people insist on > this approach/style emphasizing that the interfaces only carry logical > values and the "interpretation" of what these logical values actually mean, > should only be done inside the modules. > > Regards, > Arash Salarian > > Right...that makes sense. All the trouble is appearing because my interface uses unsigned. That will do very nicely, and all I need to do is modify my interface. Thanks very much everyone who responded! -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 108646
Dave wrote: > Ben.Nader@gmail.com wrote: > > Hi > > > > I am trying to programm a XC2S300E through a microcontroller using the > > Slave p mode. > > I make a ufp file ( which is just a hex file) of my program using > > xilinx ISE 8.1 and then using the microcontroller and and slave mode > > signals I send it to the fpga. > > I have all this working for another design, which is exactly the same > > micro but Xc2S150E FPGA. but I can not get this to work on XC2S300E. > > > > here is what happens: > > > > 1. I pulsed the ~prog line low and then high. ( to start the clearing > > configuration memory) > > 2. I see FPGA lowers INIT line ( it shows it is busy clearning the > > memory) > > 3. INIT goes high > > 4. I am sending Clock along with 8bit data on D[7:0] and CCLK. > > 5. I see INIT stays high ( so I thought CRC check was okay) > > 6. DONE stays low, I never see it coming up. > > > > after extensive search on the Xilinx website I read something that I > > could have a timing problem and I should keep sending CCLK till DONE > > goes high. so I tried just running CCLK for like a full SECOND after I > > was done sending my real data, and I still never saw DONE going high. > > > > I purposly changed my hex file to see if I the CRC error happens and > > INIT goes low. but I never saw this. INIT was high the entire time > > after the initial memory clearning process( FPGA pulled it low then) > > so this means I am not as far as CRC test on the flow chart. I am > > wondering If FPGA thinks that it is not at the end of the file yet or > > if it is reading anything at all. > > I also checked the number of bits on hex file and it matches the > > number on the Xilinx Datasheet. so I know I build the correct hex > > file. > > > > I have 3 different boards with XC2S300E that I have this problem with. > > so I doubt I have a connectivity issue or anything like that. > > > > I also double checked my pull up and downs like 100 times by now. they > > all makes sense and match my board with XC2S150E( which I can > > configure with no problem) > > > > Do you guys have any ideas where the problem coming from?.. what other > > things I should look at? > > > > I appreciate you taking the time and reading my long email and helping > > me > > > > Ben > > I use a similar scheme for an XC2S200E and a '50E, except that I use a > single bit wide data path. Initially I had similar problems. I found that > the power supply rise was not monotonic, and this seemed to upset things. I > also found that sometimes if the configuration process failed then the fpga > needed to be power cycled before it would behave - so I implemented a series > fet to do precisely that :-] The whole system is in a distributed noisy > environment, and now I basically turn on the main power with the fpgas > powered off, wait for everything to settle, then turn on and configure fpgas > in a staggered sequence. Crude it may be, but it works in the field ... > > Dave Have you checked the obvious stuff like pin-out and power supply voltages? Even though the XC2S300E and XC2S150E come in the same packages there are slight differences in the pin usage. In the larger packages the 300E has more power pins, for example. Also check that the hex file was generated with the correct format (not bit-swapped vs. the 150E file that worked). I would suggest trying to load the working bitstream of the 150E to see if you can make the INIT go low that way. If the device doesn't see the correct preamble it will not start loading code. Are you using the same version of tools that prepared the hex file for the 150E? There was a bug in the 8.1i iMpact GUI that cased raw hex files to come out bit-swapped whether you checked the box or not. HTH, GaborArticle: 108647
All, I was recently asked to do a course, which involves actually showing folks real hardware, with real software. So, like a good teacher, I went and personally purchased the Digilent pcb (this is not for work!), the USB programming cable, and went at it. I also downloaded 8.2 webpack, and the service pack. Actually trying to use your own product can be very educational. First, I was never able to use the small "boot" loader for webpack (perhaps firewalls, virus checkers, etc. wouldn't let me). Instead, I had to download the 900 Mb full file. Since at home is 144 Kb/sec, I went somewhere where I had 100 Mb/sec access. My recommendation, get the DVD. Then I had to download the service pack, which is 300 Mb. OK. Now I just install and go? YES! I am using Windoze XP, not Linux, so I can't say how easy that route would be. Then I asked a few friends to send me links to projects that run on the pcb. Building very simple (one VHDL module, one ucf file) to more complex projects went well. As long as I did not try to move any files around (never do that: project navigator believes it 'owns' the file system), everything is just fine. Since the last time I actually had to sit down and make bit streams (6.3), the tool (to me) is greatly improved. I also took a while to find FPGA_Editor, as most people don't care about it anymore, it is relegated to a sub-bullet in the tree of tools. Most of what I do at work involves FPGA_Editor, as I am usually verifying hardware functions, and I do not want the software to "get in my way." But, that is no way to do a real design. OK. So, I didn't make the pcb, and I didn't have to debug any hardware, but I was able to modify vhdl, compile, place, route, and make bit streams (and they worked). So, for those who don't know anything, or know a lot and want to know more, I can personally suggest going the Digilent 3S200 $99 pcb route: it is simple, easy, and works. The pcb has a 50 MHz clock, a socket for another clock oscillator, SDRAM for soft processor apps, flash with extra area in it, VGA interface, RS232C interface, pc keyboard interface, and a slew of IOs brought out. Oh, and a 3S200. Which is huge (to me). I usually always try to verify the smallest part (things happen faster). I begin to have an appreciation for someone trying to compile a xcv5lx330 design... Find the zipped projects for this board, and have at it. Start with something small that already works (like the simple seconds/minutes "clock" -- really a stopwatch), and play around and get more exotic. San Jose State University, and many other schools and colleges use this platform, so there is a lot of 'underground' stuff there, along with more hardware (if you need it) from Digilent (like A/D, D/A, IO, etc). It is also quite nostalgic for me, as the Spartan 3 is the old Virtex II in a completely new 90nm cost reduced form (so it feels like an old friend). For those who are reading this for the first time, Virtex II was the part that I was personally involved in. Because I was in the Virtex II DCM team, I also did some of the pre-tapeout verification for the Spartan 3 DCM. http://www.digilentinc.com/Products/Detail.cfm?Nav1=Products&Nav2=Programmable&Prod=S3BOARD AustinArticle: 108648
Ray Andraka wrote: > Partial reconfiguration itself is not new, but the tools' ability to > handle it is. The design flow for partial reconfiguration is not for > the faint of heart. Unless you have a reason to be swapping partial > bitstreams in and out in many different combinations, you are generally > better off using full bitstreams. What about just using 2 FPGA's? -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 108649
Austin Lesea wrote: > ... > I was recently asked to do a course, which involves actually showing > folks real hardware, with real software. > > So, like a good teacher, I went and personally purchased the Digilent > pcb (this is not for work!), the USB programming cable, and went at it. >... This was a good post, thanks. -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architecture
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