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jacko wrote: > hi > > just wondering if grey code (1 bit change) addressed stack memory might > be useful for cutting down carry chain logic for pre-post dec/inc > addressing?? Why bother? On FPGAs carry chain logic is free, fast and the easy path. I guess you are thinking custom chip, eh? Even then is it a real issue for the stack counter to be binary? How large will this be, 4 bits, 6 bits, 8 bits? From removethisthenleavejea@replacewithcompanyname.co.uk Tue Sep 05 08:31:46 2006 Path: newssvr25.news.prodigy.net!newsdbm05.news.prodigy.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!newsfeed.freenet.de!solnet.ch!solnet.ch!news.clara.net!wagner.news.clara.net!monkeydust.news.clara.net!iris.uk.clara.net From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> Newsgroups: comp.arch.fpga Subject: Raggedstone1 PCI Shipping Build Date: Tue, 5 Sep 2006 16:31:46 +0100 Lines: 20 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.2869 X-MIMEOLE: Produced By Microsoft MimeOLE V6.00.2900.2962 X-RFC2646: Format=Flowed; Original X-Complaints-To: abuse@clara.net (please include full headers) X-Trace: 363200c2633322c024027c16d38135327e1e5848003032243120e09044fd985f NNTP-Posting-Date: Tue, 05 Sep 2006 16:31:43 +0100 Message-Id: <1157470303.74727.0@iris.uk.clara.net> Xref: prodigy.net comp.arch.fpga:118988 Finally at last for all Raggedstone1 owners that have been asking there is now a new PCI shipping build available on our website here http://www.enterpoint.co.uk/moelbryn/raggedstone1_builds.html. The free version of the our core used in this build will be available to Raggedstone1 owners later this month once we sort out the licensing terms and mechanism. Similar builds coming soon for our other PCI boards. Current version is a beta release but is looking stable on our testing. Find anything wrong please let us know. The Tarfessock1 competition close date has been extended to lift the the post holiday blues. You have until the 15th September to enter. John Adair Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 PCI Development Board. http://www.enterpoint.co.ukArticle: 108101
Ray Andraka wrote: > rickman wrote: > > > Peter Alfke wrote: > > > >>Rickman, the SRL16 (or SRL32 in Virtex-5) really is a "physical" shift > >>register that transfers all data bits to their respective neighbors. So > >>it will probably consume more power than a pointer-addressed RAM. > >>But you don't need the pointer, and it's also a neat way to load a LUT > >>with its 16 bits. > > > > > > I wasn't aware of that. Is this only true for the V5 parts, or has > > this always been true for SRLs in Xilinx parts that have them? > > > Rickman, > > The SRLs do move the data, and always have. The shift register in > pre-V5, as I understand it is latches rather than master-slave FFs. > Maybe that is what caused the confusion. The SRL16's do move the data > though. > > Think of the structure as a 16 bit shift register with a 16:1 mux on the > outputs. The LUT address goes to the 16:1 mux select lines. The > shift register is not shifted when used as a LUT, but is shifted when > used as an SRL16. Somewhere along the way I guess I mixed up the configurable tap with just moving the pointers. Knowing the structure of the SRL is not important to using them and I guess I forgot how they really worked. In terms of power it may be simpler to move the pointers, but I guess that's not free either. I am sure the guys making the chips know exactly what to optimize and what not.Article: 108102
Eric schrieb: > Thanks Antti, > > But were is a document that talks about xil_printf and other predone > xilinx specific C routines. > > I know what printf does and I know how to toggle GPIO, but does > xil_printf support > %c, %d, %i.... etc. > > Altera did up a very nice Nios Programmers Reference Guide, I gues I > assumed Xilinix did something similar, but I can find it on there > website. > > Eric no, not all % things are supported. whats is unsupported will just be skipped in printout so you need to figure it out by trial and error what is there and whats not. complete EDK documentation is *NOT* downloadable from Xilinx website so if you want to read EDK documentation you need to install it first. AnttiArticle: 108103
During the synthesis process, Quartus reports "Ignoring invalid Fast-IO-Timing Assignments" which I am not able to discover, since Quartus does not say WHERE or WHICH assignment is set incorrectly. Any Idea ?Article: 108104
Harry Stello schrieb: > Hello all, > > Does anybody have a simple dma example that dma's from a custom peripheral > to the SRAM or SDRAM on the ML403 board? I really only need the VHDL for > the custom peripheral & the source code for the example. > > Thanks, > > Harry Harry, DMA is usually not sinmple, you have to live with that. Try it out and by the time you have it working you have already learned something. AnttiArticle: 108105
alterauser wrote: > During the synthesis process, Quartus reports "Ignoring invalid > Fast-IO-Timing Assignments" which I am not able to discover, since > Quartus does not say WHERE or WHICH assignment is set incorrectly. Any > Idea ? Did you try - Double clicking on the message? - Right click to pull up a menu that says 'Locate in..."? Usually one of those two methods locates the source of the error. Don't recall if it works for the particular error message that you've posted though KJArticle: 108106
If you are using the wizard, study the user_logic.vhd Then take a look at IPIF (proper version) DMA/SG engine about registers. Remember that DMA input data are a peripheral internal register. I tried this route with OPB bus and the DMA engine does not work properly. Maybe you have more luck with PLB and use EDK 8.2 (they say some modifications were made regarding this issue). For a realy high performance system you better use MPMC2 (www.xilinx.com/mpmc2) and connect your peripheral to NPI interface. The only MPMC2 drawback is a large logic and BRAM consumption. Cheers, Guru Harry Stello wrote: > Hello, > > I need to create a custom peripheral that DMA's data to the DDR SDRAM on the > ML403 board. My custom componet & the DDR SDRAM reside on the PLB bus. > Does anybody have an example of how to do this? The template that XPS > generates does not provide any details and as everyone knows, the xilinx > documentation is pretty poor. > > Thanks in advance > > HarryArticle: 108107
Have you tried "address++" which increments only one addr (byte), NOT 4 (word). Cheers, Guru Andy wrote: > Hi, > Iam using Xilinx EDK 7.1 and have integrated a 4-bit adder as a custom > ip. For the adder ip i have made use of 4 software addressable > registers, 8 bits wide (the only options are of 8, 16, 32 bits). Iam > not quite sure of how to access the consecutive registers using > pointers. but when i point to the 32-bit base address of the adder and > increment it with an offset it would point to a address 32 bits away > when i actually want to access the slot 8 bits away. i know iam not > doing the coding logic right ,Any suggestions would be great. > Thanks > AndyArticle: 108108
I think there is also a section "ignored timing assignments" in the timing-report. Thomas www.entner-electronics.com "alterauser" <fpgaengineerfrankfurt@arcor.de> schrieb im Newsbeitrag news:1157471016.274755.295470@d34g2000cwd.googlegroups.com... > During the synthesis process, Quartus reports "Ignoring invalid > Fast-IO-Timing Assignments" which I am not able to discover, since > Quartus does not say WHERE or WHICH assignment is set incorrectly. Any > Idea ? >Article: 108109
Antti, I know how complicated DMA usually is, I've been working with DMA to/from the PCI bus with xilinx parts for about 8 years, so I really do understand. I have not, however, used the PPC to perform dma and this is why I have posted this question. So maybe my question should have been does anybody have an examlpe of how to dma single or multiple transactions between a custom peripheral on the OPB or PLB bus to one of the onboard memories on the ML403 development kit. The xilinx documentation is not straight forward and the only example that I have come across using dma is the gigabit ethernet example, which is not by any stretch of the imagination simple. Harry "Antti" <Antti.Lukats@xilant.com> wrote in message news:1157471063.946679.101960@e3g2000cwe.googlegroups.com... > Harry Stello schrieb: > >> Hello all, >> >> Does anybody have a simple dma example that dma's from a custom >> peripheral >> to the SRAM or SDRAM on the ML403 board? I really only need the VHDL for >> the custom peripheral & the source code for the example. >> >> Thanks, >> >> Harry > > Harry, > > DMA is usually not sinmple, you have to live with that. > Try it out and by the time you have it working you have already learned > something. > > Antti >Article: 108110
"rickman" <gnuarm@gmail.com> wrote in message news:1157470465.500897.5000@m79g2000cwm.googlegroups.com... > Somewhere along the way I guess I mixed up the configurable tap with > just moving the pointers. Knowing the structure of the SRL is not > important to using them and I guess I forgot how they really worked. > > In terms of power it may be simpler to move the pointers, but I guess > that's not free either. I am sure the guys making the chips know > exactly what to optimize and what not. Moving pointers would require an addressable load and an addressable read - what's available with dual-ports. A fixed entry with single addressable output mux gives everything needed for an addressable serial-in shift register without the need for extra bits. Maintaining the in pointer and calculating the out pointer from the "I want the 5th bit" control to the output mux is a sincere amount of logic above and beyond the normal LUT structure. The SRL's output MUX is the same as used for providing the LUT output in normal operation requiring no additional logic beyond the shift through the 16 memory cells. There are many applications where a FIFO structure is best handled with separate in/out pointers, particularly when changing between time domains. The SRLs ar restricted to the same time domain for the input and output but don't need the extra pointers. As a FIFO, the SRLs have a slightly more complicated single pointer (adds and subtracts for write and read, respectively) but ends up more compact in the end.Article: 108111
from the Xilinx Virtex4 spec: =B7 XtremeDSP=99 Slice - 18x18, two's complement, signed Multiplier - Optional pipeline stages - Built-In Accumulator (48-bits) & Adder/Subtracter i'm not too familiar with dsp on fpga - what does it mean when it says 18x18 multiplier? is it a hardware multiplier? is there anywhere i can get informations on and how to use them? something specific to virtex4 would be nice thx=20 tejoArticle: 108112
hi how do i enter the 16 bit number of a 4 input 1 output lut to get a compact block design file for easy use?? is this possible, as editing the bits like constants would be much easier than trying to trace out the logic as primitives. i would have thought a lut was primitive. oh well. :-( cheers p.s. does altera ever do .bsf updates?Article: 108113
Click on http://www.xilinx.com/bvdocs/userguides/ug073.pdf for an extensive User Guide. Peter Alfke, Xilinx =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D sutejok wrote: > from the Xilinx Virtex4 spec: > > =B7 XtremeDSP=99 Slice > - 18x18, two's complement, signed Multiplier > - Optional pipeline stages > - Built-In Accumulator (48-bits) & Adder/Subtracter > > > i'm not too familiar with dsp on fpga - what does it mean when it says > 18x18 multiplier? is it a hardware multiplier? is there anywhere i can > get informations on and how to use them? > something specific to virtex4 would be nice >=20 > thx=20 > tejoArticle: 108114
Anonymous wrote: > I have a xilinx soc that is running 2.4 of the PPC linux fine. To run 2.6 is > it just a matter of copying the arch directory over to the 2.6 tree and > compiling? (Assuming I keep the configuration options the same.) > > Thanks, > Clark If you're starting from scratch I'd strongly recommend going with a 2.6 kernel. 2.6 is very easy to get a serial port driver working, which is crucial for debug output while bringing up the kernel. Google will bring up some step by step instructions for doing this. The xilinx free uart-lite core is easy to get working. I brought up 2.6 on a virtex-2 pro with the embedded PPC cores. u-boot boots from a small bootloader embedded in one of the BRAMS, which chains to a NAND flash, which contained u-boot. Finally u-boot read out linux-2.6 from a different area of the NAND flash. I submitted a patch to the u-boot group bringing up u-boot on the Memec Design FF1152 board some months ago, I doubt if it has been included in the main source tree of u-boot though. That included support for the uart lite. Once you've got u-boot linux gets easy to bring up. If you look at the u-boot archive you can find my post of the patch. Why 2.6? It's the future, man. If you pick 2.4 someday you'll have to upgrade anyway. Pick the latest first. To answer your specific question, code from 2.4 does not just drop in to 2.6. There are lots of little differences. You can recognize the same basic code flow from a driver for 2.4 vs 2.6, but a lot of the low level details are tweaked. It's fairly easy to adapt 2.4 code to 2.6 code though. Xilinx has ethernet cores. I haven't found an out of the box linux driver, 2.4 or 2.6, for any of Xilinx's cores. u-boot supports the xilinx ethernet cores. Montevista has drivers for xilinx cores, but presumably you'd need to pay for their linux version. BTW I wasn't able to compile 2.6 under the windows EDK 8.1 cygwin environment. The build process complains that the versions of binutils and the compiler don't match, or something, and that either one or the other has to be upgraded or downgraded. This was very frustrating, I spent a lot of time trying to get a working setup, without success. In the end I just built linux-2.6 from a linux host and stopped trying to build software under windows. Finally one more note. I found it pointless to use Xilinx's source code in any form, or their EDK, for the software side of things. I was always struggling with their includes + IDE + point and click interface. I invested the time in getting a linux build environment up where I could build the software side under linux, and export the ELF executables over to the windows box which would then integrate into the FPGA bitfile. Once I did that development went *fast*. Xilinx software is a nest of fishhooks -- try to get one thing, and it includes more, and that includes more...pretty soon your 100 byte bootloader doesn't fit into the 16K bytes you've allocated out of BRAMs for the PPC init code at FFFFC000... -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 108115
CALL . This because CALL is too slow . New Forths jump indirect at worst and at best ( Chucks NS4000 ) dont pay any price at all , they JUMP direct to next executable !!! There is no way to salvage the function "CALL" It is a bad idea . Why return when thats not what you want to do ? BTW NewForth has to simulate a fast "executable to excuatble" cause ARM is slow in all branches . NF does next best thing , Indirect jump directly to next executable . There is no faster way . _____________________________________________________________ Jecel wrote: > If you are going to compile Forth then CALL is probably the first > instruction you want to optimize and I didn't even see it or an > equivalent in your list......................... . And in general it > isn't very good to allow the stack to get very deep with temporary > values when programming stack machines. [[[[[[[[ STACKS are trouble , use modern programming pls ]]]]]] > -- JecelArticle: 108116
Tejo, http://direct.xilinx.com/bvdocs/userguides/ug073.pdf Yes, the 18X18 multiplier/accumulator is a hardened block, so that performing this function results in from 8 to 20 times less power than performing this function would if it was done in the logic of the FPGA (luts, dff, interconnect, etc.) The above guide details use of the V4 for "extreme" DSP uses. FPGAs are useful for tasks that DSP processors are too slow for, otherwise, DSP processors are generally far easier and better suited for DSP. For example, a video conference processor, where multiple streams must be encoded, decoded, combined, along with all audio processing is one such task where a FPGA would excel for both cost, power, and performance. http://www.demosondemand.com/clients/xilinx/001/page/index_dsp_review.asp Austin sutejok wrote: > from the Xilinx Virtex4 spec: > > · XtremeDSP™ Slice > - 18x18, two's complement, signed Multiplier > - Optional pipeline stages > - Built-In Accumulator (48-bits) & Adder/Subtracter > > > i'm not too familiar with dsp on fpga - what does it mean when it says > 18x18 multiplier? is it a hardware multiplier? is there anywhere i can > get informations on and how to use them? > something specific to virtex4 would be nice > > thx > tejo >Article: 108117
Jim Thompson wrote: > On Tue, 5 Sep 2006 10:02:40 -0400, "mc" > <look@www.ai.uga.edu.for.address> wrote: > >> "mc" <look@www.ai.uga.edu.for.address> wrote in message >> news:EmfLg.47233$e9.7114@bignews4.bellsouth.net... >>> "CBFalconer" <cbfalconer@yahoo.com> wrote in message >>> news:44FD685C.9311F3B1@yahoo.com... >>> >>>> "I'm the commander--see, I don't have to explain -- I don't need >>>> to explain why I say things. That's the interesting thing about >>>> being the President. Maybe somebody needs to explain to me why >>>> they say something, but I don't feel like I owe anybody an >>>> explanation." - George W. Bush, 2002-11-19 >>> Just out of curiosity, what is the source of that quote? If I quote it, >>> people are going to ask me how I know it's genuine. >> Found it. CBS News, dated 2002/11/17: >> http://www.cbsnews.com/stories/2002/11/17/60minutes/main529657.shtml >> > > Yep. CBS/Wallace/Woodward... the kind of source that makes the > stomach turn. > > ...Jim Thompson Surprisingly he gave the context for that statement. But I'm sure it will be used out of context. -- Cecil KD5NWA www.qrpradio.com www.hpsdr.com "Sacred Cows make the best Hamburger!" Don Seglio BatunaArticle: 108118
Harry - If you create a system that has PPC + plb_ethernet using BSB, it will generate TestApp_Peripheral that will show you how to use the ethernet core in DMA mode. /Siva Harry Stello wrote: > Antti, > > I know how complicated DMA usually is, I've been working with DMA to/from > the PCI bus with xilinx parts for about 8 years, so I really do understand. > I have not, however, used the PPC to perform dma and this is why I have > posted this question. So maybe my question should have been does anybody > have an examlpe of how to dma single or multiple transactions between a > custom peripheral on the OPB or PLB bus to one of the onboard memories on > the ML403 development kit. > > The xilinx documentation is not straight forward and the only example that I > have come across using dma is the gigabit ethernet example, which is not by > any stretch of the imagination simple. > > Harry > > "Antti" <Antti.Lukats@xilant.com> wrote in message > news:1157471063.946679.101960@e3g2000cwe.googlegroups.com... > >>Harry Stello schrieb: >> >> >>>Hello all, >>> >>>Does anybody have a simple dma example that dma's from a custom >>>peripheral >>>to the SRAM or SDRAM on the ML403 board? I really only need the VHDL for >>>the custom peripheral & the source code for the example. >>> >>>Thanks, >>> >>>Harry >> >>Harry, >> >>DMA is usually not sinmple, you have to live with that. >>Try it out and by the time you have it working you have already learned >>something. >> >>Antti >> > > >Article: 108119
On 5 Sep 2006 09:42:49 -0700, "jacko" <jackokring@gmail.com> wrote: >hi > >how do i enter the 16 bit number of a 4 input 1 output lut to get a >compact block design file for easy use?? > >is this possible, as editing the bits like constants would be much >easier than trying to trace out the logic as primitives. > >i would have thought a lut was primitive. oh well. :-( http://groups.google.com/group/comp.arch.fpga/msg/21b0570d750484feArticle: 108120
ALuPin@web.de wrote:
> I have tried to synthesize the synchronous fifo example "FIFO.vhd"
> from Ben Cohen's book "Real Chip Design and Verification Using Verilog
> and VHDL" on a Lattice EC15 (Synplicity compiler)
> For the FIFO registers declaration I add the following
> attribute :
>
> attribute syn_ramstyle : string;
> attribute syn_ramstyle OF FIFO_r : SIGNAL IS "block_ram";
>
> And yet the synthesis results show that no Embedded RAM
> blocks are used.
If the target fpga has block ram, and if you
use the recommended code template, no
attribute hints are required.
> Is the used attribute not appropriate or is Synplify not able
> to implement the registers as EBR in that hardware description?
Attributes and commented directives
are vendor specified, and only work
for tools that recognize them.
-- Mike Treseler
Article: 108121CBFalconer wrote: > "Michael A. Terrell" wrote: > >>Steve at fivetrees wrote: >> >>>"Michael A. Terrell" <mike.terrell@earthlink.net> wrote in message >>> >>>>Luhan wrote: >>>> >>>>>The famous N.E.D. (noise emitting diode) - goes bang just one time! >>>> >>>>Install a 1N34 across a light switch with the power off an d the >>>>switch is on. Turn the power back on and wait for someone to >>>>shut it off. Then there is a loud bang, but the light still >>>>works when they turn it back on. I used to have 5000 spares. ;-) >>> >>>My kinda guy ;). >> >>I got some people more than once. Anyway, what else would you use >>unmarked germanium diodes for? You can only use so many in >>prototypes. > > > I used to install a roughly 68 ohm 1/2 watt carbon resistor across > the AC mains (110 volt) after the power switch. This was usually > done at lunch time, while someone else was preparing for his > initial smoke test on a new instrument (back in the days of > tubes). The result was a satisfactory grrr-bang and smoke. Modern > resistors don't work as well, they just fizzle. > Ahh... You forgot the most important ingredients! A 5wats resistor somewhere dissipating 10 or 20 wats, and smeared with a liberal coat of grease. Its important that said resistor should turn cherry red in 2 or 3 seconds.......Oops, should not have told this.Article: 108122
werty wrote: > CALL . > This because CALL is too slow . > New Forths jump indirect at worst and > at best ( Chucks NS4000 ) dont pay any price at all , they JUMP > direct to next executable !!! If by NS4000 you mean the Novix NC4016 then it is exactly an example of what I was talking about - subroutine call is the most optimized instruction with its opcode taking up a single bit. http://www.ece.cmu.edu/~koopman/stack_computers/sec4_4.html There are several kinds of Forth implementations, but at least Chuck Moore's recent efforts seem to favor the subroutine threaded model. Even for models where you don't need an actual call instruction the equivalent functionality is included in the kernel (you need to save stuff to the return stack at some point). With subroutine threading it is indeed a great idea to replace tail calls with jumps. > There is no way to salvage the function "CALL" It is a bad idea . > Why return when thats not what you want to do ? Sometimes it isn't what you want to do, but sometimes it is. > BTW NewForth has to simulate a fast "executable to excuatble" > cause ARM is slow in all branches . > NF does next best thing , Indirect jump directly to next executable . > > There is no faster way . What is fast or not depends on the processor architecture and even more on the implementation of the memory hierarchy. -- JecelArticle: 108123
I need to recover data from a serial LVDS I/O stream running at over 300 MHz. A reference 26 MHz clock is provided by the data source. So that clock needs to be bumped up to the data rate. The fast data is NOT phase aligned with the reference (or derived) clock. There is a 16-bit sync pattern at the start of every 'frame' of data. There is guarenteed to be at least one bit of '0' before the sync pattern starts - between frames or from reset. It starts with a '1'. So a zero to one tansition will start the sync pattern if the 'logic' is 'searching' for the sync. I have implemented some hardware that will work by using 4 phases of the fast clock. And I basically built a serial-to-parallel logic block that takes the data and deserializes it. The sync is searched for and detected. Once detected, the data is passed from the best phased clock domain. This all works fine and well at 100 MHz. I knew I would never get it up to the speed I need (Virtex4 LX25 -10) using the fabric. So I've looked in to using the SERDES IO technology. I've read the user guide and looked at some applications notes, but haven't found anything that really matches what I need. The logic that the app notes implement either rely on bit-syncronization techniques or a steady training pattern over a 'long' time. Those take too long to complete. I need to decide what phase of the clock to use (to ensure good data capture over a given frame) and pass that data on in less than the 16-bit sync pattern. I know there are many possible solutions, but I was just posting this while I mess around with this problem. Anyone have any ideas? Thanks!Article: 108124
"motty" <mottoblatto@yahoo.com> schrieb im Newsbeitrag news:1157480088.467287.234360@d34g2000cwd.googlegroups.com... >I need to recover data from a serial LVDS I/O stream running at over > 300 MHz. A reference 26 MHz clock is provided by the data source. So > that clock needs to be bumped up to the data rate. The fast data is > NOT phase aligned with the reference (or derived) clock. There is a > 16-bit sync pattern at the start of every 'frame' of data. There is > guarenteed to be at least one bit of '0' before the sync pattern starts > - between frames or from reset. It starts with a '1'. So a zero to > one tansition will start the sync pattern if the 'logic' is 'searching' > for the sync. > > I have implemented some hardware that will work by using 4 phases of > the fast clock. And I basically built a serial-to-parallel logic block > that takes the data and deserializes it. The sync is searched for and > detected. Once detected, the data is passed from the best phased clock > domain. This all works fine and well at 100 MHz. I knew I would never > get it up to the speed I need (Virtex4 LX25 -10) using the fabric. So > I've looked in to using the SERDES IO technology. I've read the user > guide and looked at some applications notes, but haven't found anything > that really matches what I need. The logic that the app notes > implement either rely on bit-syncronization techniques or a steady > training pattern over a 'long' time. Those take too long to complete. > I need to decide what phase of the clock to use (to ensure good data > capture over a given frame) and pass that data on in less than the > 16-bit sync pattern. I know there are many possible solutions, but I > was just posting this while I mess around with this problem. Anyone > have any ideas? > > Thanks! > it depends, if the clock derived from 26MHz stays in 'fixed' phase align during each frame, then its easy. if not then it can be rather complex. all you have todo is to have 4 phase captures per bit and choose the best - you can achive this by having 4 clock phases, as you are doing or you can use 1 or 3 IDELAYs calibrated and adjusted to have samples at about the equal time slots to slice the input data properly. its still bit tricky as you can only have one IDELAY per iob, so you need some trick, like 3 pins in parallel, well you have to experiment a bit, but this should defenetly be doable in LXxx -10 the 300mhz clock domain part sure needs special care. but the Virtex-4 LUT and fabric is rather fast, I have measured in fabric actual clock rates up to 975MHz in slowest speed grade V-4 well 1GHz signals are not able to travel very long, but having small part of the design to run at 300MHz should not be rocket sience. ah, the MGTs can of course also be used, I have made some test using V2Pro MGTs as super-sampler at 3GHz sampling rate but the logic to recover date from behind MGT used as shift register isnt so trivial either. (not sure if SERDES was reference to MGTs or the V4 IDELAY/ILOGIC?) Antti
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