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"John Woodgate" <jmw@jmwa.demon.co.uk> wrote in message news:tBHd8NUc5H+EFwPK@jmwa.demon.co.uk... > claimed a boot/trunk capacity in cubic litres. Hmm were string theorists in on that ad, you think? Nine dimensional volume must be something to behold... Tim -- Deep Fryer: a very philosophical monk. Website: http://webpages.charter.net/dawill/tmoranwmsArticle: 107901
"John Woodgate" <jmw@jmwa.demon.co.uk> wrote in message news:uQ7N4CntJK+EFwfa@jmwa.demon.co.uk... >>Our drill sergeant used to say that the day has 24 hours and when that >>ain't sufficient then there is still the night. > > That's right; it's how consultants get to work 170 hours a week. And lawyers get to bill 180!Article: 107902
Joerg wrote: > Hello Bill, > > >> > >>>>Then, for whatever reason, several days later it would be obviously > >>>>wrong if proofed again. > >>> > >>>Even skilled proof-readers find that. But even at first reading, it's > >>>almost as if the errors are printed in a different colour, they are so > >>>obvious. And this can extend to poor sentence construction, like 'only' > >>>being in the wrong place. > >> > >>That can also happen if you regularly have to switch between languages > >>several times a day. > > > > Doesn't work for me, but my Dutch grammar isn't quite what it ought to > > be - I failed the Dutch as a Second Language exam on my written Dutch > > with a score off 499 against a pass mark of 500, after comfortably > > passing the tests of mmy capacity to read. hear and speak Dutch. > > > > Did they make you do that test for citizenship or something? No, I'd been living here for ten years when I got around to taking the test - at one point it looked as if I might be able to do the computer science course at the local university for not-unreasonalbe fees if I demonstrated that I had mastered Dutch, which is what NT2 II (Dutch as a Second language option 2) is all about, but by the time I'd jumped through the hoops they'd changed the rules and the fees were back up to 6,000 euros per year. > I lived > there over 6 years and never took any tests. Now about 20 years later > it's mostly gone but my Dutch comes back after 2-3 pintjes of Grolsch. > However, as with you only the read-hear-speak portions of it. Writing is > definitely gone. > > It's hard to practice out here in the west. Except for Radio Nederland > Wereldomroep plus one friend who was born in NL there isn't much of a > chance. Even in the Netherlands it is getting difficult - I've got an obvious English accent, and many people will reply to my Dutch in English, just to exercise their English. -- Bill Sloman, NijmegenArticle: 107903
Nial Stewart wrote: > I need to interface some 12 and 24V signals to an FPGA/CPLD, > it'll probably be one of the low end Spartans or Cyclones. > > These are _very_ low bandwidth signals, 10's of hz at the most. > > Because of the signal density, cost and restrictions of board > space I am unable to implement any voltage regulation/clamping > pre the FPGA inputs. > > I am planning to using a very large in line resistor (100K ?) to > limit current into the device pins. > > I know that one of the recommended techniques for interfacing to > 5V PCI signals is to use an in-line current limiting resistor. > What I'm planning is an extension of this but I've previously > always used quickswitches to clamp higher volates to safe limits > and intuitively don't like applying these higher voltages to the > pins. > > Should this be OK? Yes, with some caveats : Ideally, you should use Schmitt pin option (if there is one ) If no schmitt option is available, be aware that transistion oscillations can occur, and they can do nasty things to the system reliability. A single resistor will give you whatever threshold the device has, and that might be appx 1.2V : on a 24V signal, that's rather close to GND ?! So, at the least a resistive divider is advisable, to shift that threshold to give you better noise immunity ( even 10Hz signals need a level margin ) Some devices have hot socketing, with optional clamp diodes. In those, you should enable the clamp diode. Take care with the design to ensure solder splashes cannot drop the 24V onto a FPGA pins - that WILL be curtains :) -jgArticle: 107904
Hi, Iam using Xilinx EDK 7.1 and have integrated a 4-bit adder as a custom ip. For the adder ip i have made use of 4 software addressable registers, 8 bits wide (the only options are of 8, 16, 32 bits). Iam not quite sure of how to access the consecutive registers using pointers. but when i point to the 32-bit base address of the adder and increment it with an offset it would point to a address 32 bits away when i actually want to access the slot 8 bits away. i know iam not doing the coding logic right ,Any suggestions would be great. Thanks AndyArticle: 107905
John Woodgate wrote: > > In message <1157138487.522552.281170@h48g2000cwc.googlegroups.com>, > dated Fri, 1 Sep 2006, fpga_toys@yahoo.com writes > > >I quickly changed my schedule and started working midnight to 2PM to > >avoid the afternoon/evening parties. > > I remember sitting in a British Standards meeting while pairs of pigeons > were busy mating on the window sill of the committee room. At least SOMETHING productive happened during your meeting. ;-) -- Service to my country? Been there, Done that, and I've got my DD214 to prove it. Member of DAV #85. Michael A. Terrell Central FloridaArticle: 107906
Jim Granville wrote: > > So, at the least a resistive divider is advisable, to shift that > threshold to give you better noise immunity ( even 10Hz signals need > a level margin ) I should add, that when you do use a divider, then over-drive of the pins 'goes away'. If you set the divider to give 3.3V Vih, then the threshold will be somewhere around 8V, which is a better sounding level. ie Two resistors, appx 8:1, and no diodes needed. Use multipack resistors. -jgArticle: 107907
Homer J Simpson wrote: > > "John Woodgate" <jmw@jmwa.demon.co.uk> wrote in message > news:uQ7N4CntJK+EFwfa@jmwa.demon.co.uk... > > >>Our drill sergeant used to say that the day has 24 hours and when that > >>ain't sufficient then there is still the night. > > > > That's right; it's how consultants get to work 170 hours a week. > > And lawyers get to bill 180! I worked seven months of 112 hours per week, and got paid for 148 hours (16 hours/day with time and a half for anything over 40 hours) except for Christmas Day and New Years Day when I got paid an extra 16 hours per day. On top of that, my boss was bitching that I should be willing to work even more hours. -- Service to my country? Been there, Done that, and I've got my DD214 to prove it. Member of DAV #85. Michael A. Terrell Central FloridaArticle: 107908
Symon wrote: > > Hi Nial, > If the signal goes from 0V to 24V and if you've got room for a resistor, > you've probably got room for a diode. Point the sharp end at the 24V signal, > the blunt end towards the FPGA. Turn on the FPGA pin's internal pullup > resistor. Viola! Problem with this is, now your noise immunity is about half the already poor 1.2-1.5V.. - plus you have an ESD path straight into the FPGA pin :( -jgArticle: 107909
In message <12fhfqhekrb5f70@corp.supernews.com>, dated Fri, 1 Sep 2006, Joel Kolstad <JKolstad71HatesSpam@yahoo.com> writes >That was the same school where I was allowed to run the 16mm film >projector until one day I accidentally knocked it off the ~4' tall >rolling cart it was on, sending it tumbling onto a hard floor and >mangling the reel support arms, causing hundreds of dollars in damage. .... because someone didn't foresee that happening and fixed the project down. -- OOO - Own Opinions Only. Try www.jmwa.demon.co.uk and www.isce.org.uk 2006 is YMMVI- Your mileage may vary immensely. John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UKArticle: 107910
Austin Lesea schrieb: > cs_posting, > > http://direct.xilinx.com/bvdocs/publications/ds060.pdf > > Is still right there, online, and up front. So yes, a new design with a > 5V Spartan 4K part is not only do-able, but supported. 5V Instrumentation busses can also be interfaced to with a Spartan-II. Albeit using 3.3V as VCCIO the inputs are 5V tolerant and 5V TTL only requires the output to be driven to 2.4V so you get full TTL compliance. While the 3.3V are not 5V CMOS compliant, the resulting 0.8V noise margin should be enough for most applications. Kolja SulimmaArticle: 107911
In message <pan.2006.09.02.00.15.21.934513@doubleclick.net>, dated Sat, 2 Sep 2006, "Rich Grise, Plainclothes Hippie" <eatmyshorts@doubleclick.net> writes >On Fri, 01 Sep 2006 12:26:26 -0700, fpga_toys wrote: >> Spehro Pefhany wrote: >>> You had him executed by the Spanish Inquisition, didn't you, Mr. WOOD >>> of GATE? >> >> As Mister, he is not of the court. The title would be Lord Wood, of >> Gate if he had that power. > >I'd have thought that a "WOOD GATE" would be more like a "GATE of WOOD". > The Inquisition was a church court, so it consisted of one or more bishops, canons, priests and deacons. I wouldn't want to be any of them. 'Gate of the wood', indicating the place where the original Woodgate lived, is probably the correct derivation. -- OOO - Own Opinions Only. Try www.jmwa.demon.co.uk and www.isce.org.uk 2006 is YMMVI- Your mileage may vary immensely. John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UKArticle: 107912
In message <pan.2006.09.02.00.08.58.136818@doubleclick.net>, dated Sat, 2 Sep 2006, "Rich Grise, Plainclothes Hippie" <eatmyshorts@doubleclick.net> writes > "You're a better man than I am, Gunga Din!" That's another Kipling poem worth reading, indeed. -- OOO - Own Opinions Only. Try www.jmwa.demon.co.uk and www.isce.org.uk 2006 is YMMVI- Your mileage may vary immensely. John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UKArticle: 107913
"Joerg" <notthisjoergsch@removethispacbell.net> schreef in bericht news:_f0Kg.13960$1f6.3341@newssvr27.news.prodigy.net... > fpga_toys@yahoo.com wrote: > >> John Woodgate wrote: >> >>>Indeed. For a certain transportation project, around GBP5 billion, I >>>believe, questions are asked about my fixed-price fee for 'two days' >>>work. I've actually put in about four days so far, and it isn't over >>>yet. >> >> So ... was "two days" bid as 16 hrs, or 48 hrs? >> > > Our drill sergeant used to say that the day has 24 hours and when that > ain't sufficient then there is still the night. Hahaha, that's a good one ;) -- Thanks, Frank. (remove 'q' and '.invalid' when replying by email)Article: 107914
zwsdotcom@gmail.com wrote: > Is it actually possible to download WebPACK? > > I tried using my existing xilinx.com account to download it, and I get > into an endless loop where I'm shown a button that says "click here to > register" then another button that says "click here to download if > you're already registered". The second button just takes me to the same > page again, over and over. > > I tried creating a new account on xilinx.com and with this account I > can't even log into the abovementioned infinite-loop page; it doesn't > accept the new username/password. > > Has anyone ever worked out the magic combination of browser versions > and whatever other magic the PITAs at xilinx require? I recently had this problem downloading the latest version at home. If you have a standalone firewall in place, and you are running a Win32 platform, then check the 'generic host process' permissions. I normally turn off all access as 'servers for internet' (because I am not actiing as a server for anyone or anything), but the download requires *you* to act as a server. Stupid, really. In addition, for some features, you need to turn on Java (which is even more stupid - I never use Java on websites, and if a vendor requires it, they are usually dropped from any designs I may be doing). I am using Win32 (W2KPro), Firefox with NoScript (but Xilinx.com enabled) and ZoneAlarm Pro for the firewall, and once I tweaked the firewall settings the download worked. Don't try to download the 'web install'. The xilinx servers go up and down like YoYos and the install will complain about *your* internet connection, when in fact it's the Xilinx servers. The full install, though, is almost 1GByte (that's not a typo). I put it in simplistic terms as I expect the email went to a marketdroid, because permitting servers can be ok with precautions, of course. Here's the email I sent: --------------------------------------------------------------------- I am installing the webpack on my home system so I can work on projects while here. Whilst trying to do this, one first reaches this page: http://www.xilinx.com/ise/webpack_access_help.htm There is a button for the download which accesses a webpage at: http://www.xilinx.com/webpack/index.htm I was continually being redirected back to the access page (above). It turns out that the page involved requires Generic Host process for Win32 services to be enabled as a server for the internet. This is an incredibly bad practice, as it is the method by which many drive-by virii, trojans and various malware are intalled. On this system I do not permit that particular service to be a server in the internet zone under normal conditions. Indeed, there are virtually no services permitted to be internet servers by default on this system; it is, after all, used by my family, including a teen who might click on items he should not, and a wife who is not technically savvy. You should change the web access to not require this, but in the meantime, at least put a note on the page that this needs to be enabled in the local firewall. By requiring this, you force advanced users to open up their systems to all forms of attack that otherwise they are protected from. I note that I have never needed to give this permission to the Generic Host service for *any other download from any other vendor*. --------------------------------------------------------------------------------------- Cheers PeteSArticle: 107915
PeteS wrote: > I recently had this problem downloading the latest version at home. If > you have a standalone firewall in place, and you are running a Win32 My Internet access, like most peoples', goes through a hardware router that NATs my local network onto a single real IP address. I can't connect directly to the Internet because there is other hardware that requires 24/7 connectivity - alarms will ring and pain will occur if I unplug the cable. > platform, then check the 'generic host process' permissions. I normally ... where? I've never seen a checkbox like this I don't use Windows Firewall. I use Norton Antivirus. But even on a machine where I have no software firewall, I get the same symptom. Xilinx's webmaster should be shot. His manager should be shot too, for not keeping the situation under control. And HIS manager should be boiled in oil, twice. They never test anything. As a data point, I've spent 38 billable hours just trying to get to the point of getting a simple tutorial example to build and run. (Not counting this WebPACK shenanigan). > In addition, for some features, you need to turn on Java (which is even > more stupid - I never use Java on websites, and if a vendor requires > it, they are usually dropped from any designs I may be doing). I have to have Java installed because I do some development in that language, so that's not a problem.Article: 107916
Kolja Sulimma wrote: > Austin Lesea schrieb: > > cs_posting, > > > > http://direct.xilinx.com/bvdocs/publications/ds060.pdf > > > > Is still right there, online, and up front. So yes, a new design with a > > 5V Spartan 4K part is not only do-able, but supported. > > 5V Instrumentation busses can also be interfaced to with a Spartan-II. > Albeit using 3.3V as VCCIO the inputs are 5V tolerant and 5V TTL only > requires the output to be driven to 2.4V so you get full TTL compliance. > While the 3.3V are not 5V CMOS compliant, the resulting 0.8V noise > margin should be enough for most applications. I want to actually drive it at close to 5v - otherwise yes there are many choices. The problem with using a Spartan "0" is figuring out how far back in the history of the tools one must delve to find support...Article: 107917
Hi, I am new to VHDL. I write the following simple counter program in ISE webpack 8.2. Both two can be behavior simulated. But, the simulation of the second (without Reset control) is not correct after synthesis. This example is just an exercise to me. What I care is: Is there other pitfalls I have to know in order to avoid it cannot synthesis? Thank you very much. -- First architecture Behavioral1 of smallComp is --signal clk: clk in std_logic; signal count : INTEGER range 0 to 15; begin cp1: process (clk, RESET) begin if RESET='1' then count <= 0; elsif (clk='1' and clk'event) then if count >= 15 then count <= 0; else count <= count + 2; end if; end if; end process; cnt <= CONV_STD_LOGIC_VECTOR(count,4); end Behavioral1; --Second architecture Behavioral2 of smallComp is --signal clk: clk in std_logic; signal count : INTEGER range 0 to 15; begin cp2: process (clk) begin if (clk='1' and clk'event) then if count >= 15 then count <= 0; else count <= count + 2; end if; end if; end process; cnt <= CONV_STD_LOGIC_VECTOR(count,4); end Behavioral2;Article: 107918
On 1 Sep 2006 12:17:13 -0700, zwsdotcom@gmail.com wrote: >Is it actually possible to download WebPACK? > >I tried using my existing xilinx.com account to download it, and I get >into an endless loop where I'm shown a button that says "click here to >register" then another button that says "click here to download if >you're already registered". The second button just takes me to the same >page again, over and over. You're using Mozilla, yes? If so, this may be a long-standing Xilinx webpage bug. You can either get creative about finding or guessing the actual download URL (works for me for most "register first" app notes and associated files, but might not work for Webpack) or try using another browser, if you can work out which one Xilinx test their webpages with. - Brian.Article: 107919
Maybe the "ability" is not correct or accurate. After synthesis, the simulation should reflect the reality of FPGA. But, the initial value of counter is "0000". After the first clock rising edge, its content is "00X0". It seems the simulation does not know the correct value even it did know the first value is "0000". Thanks. fl wrote: > Hi, > I am new to VHDL. I write the following simple counter program in ISE > webpack 8.2. Both two can be behavior simulated. But, the simulation of > the second (without Reset control) is not correct after synthesis. This > example is just an exercise to me. What I care is: Is there other > pitfalls I have to know in order to avoid it cannot synthesis? > > > Thank you very much. > > > -- First > architecture Behavioral1 of smallComp is > --signal clk: clk in std_logic; > signal count : INTEGER range 0 to 15; > begin > cp1: process (clk, RESET) > begin > if RESET='1' then > count <= 0; > elsif (clk='1' and clk'event) then > if count >= 15 then > count <= 0; > else > count <= count + 2; > end if; > end if; > end process; > cnt <= CONV_STD_LOGIC_VECTOR(count,4); > end Behavioral1; > > > > --Second > architecture Behavioral2 of smallComp is > --signal clk: clk in std_logic; > signal count : INTEGER range 0 to 15; > begin > cp2: process (clk) > begin > if (clk='1' and clk'event) then > if count >= 15 then > count <= 0; > else > count <= count + 2; > end if; > end if; > end process; > cnt <= CONV_STD_LOGIC_VECTOR(count,4); > end Behavioral2;Article: 107920
Brian Drummond wrote: > or try using another browser, if you can work out which one Xilinx test > their webpages with. Yes, and the they should write on their page "install Windows, to download the Linux version with Internet Explorer" :-) -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 107921
Brian Drummond wrote:
> You're using Mozilla, yes?
I tried Firefox, Internet Explorer and Safari.
> If so, this may be a long-standing Xilinx webpage bug.
Yes: Their webmaster is incompetent and should be fired. At least their
webmaster is not a trained monkey. Trained monkeys would do a better
job.
> You can either get creative about finding or guessing the actual
> download URL (works for me for most "register first" app notes and
It's not in the page with the download button. When you click the
download button, you go to http://www.xilinx.com/webpack/index.htm but
the server immediately redirects you back to the "register or download"
page. However, as I was writing this message I had a sudden idea, and
it worked.
#define SARCASM_LEVEL BITING | (BITTER << 4)
Oh, I am SO STUPID. CLEARLY the thing I should have done FROM THE START
was:
wget --user={username} --password={password}
http://www.xilinx.com/webpack/index.htm
then poke in the HTML file to get the direct download links (you can't
really read the HTML file easily without the CSS). And here they are:
Web install:
<http://direct.xilinx.com/direct/webpack/82/WebPACK_82i_WebInstall.exe>
<http://direct.xilinx.com/direct/webpack/82/WebPACK_82i_WebInstall.sh>
Full download:
<http://direct.xilinx.com/direct/webpack/82/WebPACK_82i_SFD.exe>
<http://direct.xilinx.com/direct/webpack/82/WebPACK_82i_SFD.sh>
Programming tools only:
<http://direct.xilinx.com/direct/webpack/82/WebPACK_82i_ProgTools.exe>
<http://direct.xilinx.com/direct/webpack/82/WebPACK_82i_ProgTools.sh>
ModelSim Xilinx Edition-III
<file:///ise/mxe3/license.htm>
(That last one is not a typo on my part. Yes, the ModelSim link in the
HTML file is a direct link to a file on the local hard drive of the
incompetent fool who gets paid to maintain this particular corner of
hell on the Internet).
> or try using another browser, if you can work out which one Xilinx test
> their webpages with.
Evidence at hand would suggest that Xilinx never tests anything -
neither their software, nor their documentation, nor their web site.
Someone hears a rumor that the current version kinda worked once on
some particular PC, and that's good enough to go live.
Article: 107922
zwsdotcom@gmail.com schrieb:
> #define SARCASM_LEVEL BITING | (BITTER << 4)
> Oh, I am SO STUPID. CLEARLY the thing I should have done FROM THE START
> was:
>
> wget --user={username} --password={password}
> http://www.xilinx.com/webpack/index.htm
I am sure that qualifies as hacking an effective copy protection
technology under the DMCA.
Kolja
Article: 107923I like to start FPGA but I have access to a CPLD traning kit . I would like to know : 1-If I start with CPLD (XC9572 the training kit has it ) can I later work with FPGA (Spartan 2,3) ? 2-Does these two have much defferent Hardware design ? 3-Are ISE & VHDL have much defference ?Article: 107924
Ali wrote: > 1-If I start with CPLD (XC9572 the training kit has it ) can I later > work with FPGA (Spartan 2,3) ? Yes. > 2-Does these two have much defferent Hardware design ? Yes, they use different low-level blocks to implement a design. > 3-Are ISE & VHDL have much defference ? As long as you use VHDL, only, without special entities of the hardware (like block RAM or DCM), it compiles for every CPLD and FPGA, if there are sufficient number of logic elements to synthesize it. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.de
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