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In message <hTYJg.7310$q63.4412@newssvr13.news.prodigy.com>, dated Fri, 1 Sep 2006, Joerg <notthisjoergsch@removethispacbell.net> writes >Brain: "Oh drat, now I'm not going to make the meeting in Denver on >time". Don't, whatever you do, take a trip on 'old 97'! -- OOO - Own Opinions Only. Try www.jmwa.demon.co.uk and www.isce.org.uk 2006 is YMMVI- Your mileage may vary immensely. John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UKArticle: 107826
> Oh, tell me about it. In a previous existence, that sort of thing > was the bane of my life. Mind-numbingly simple stuff, but > there's no well-integrated support for it; it costs space, > components, PCB trackery, power supply fuss and bother, > and all manner of general horribleness. You've been here then :-( Made worse by the fact I work for/by myself so there's no one to talk this sort of stuff over with (that's where 'you lot' come in). > I would be very nervous of adding 100K-ish resistors in > series with an FPGA input; the very slow rise times you > would thus get sound to me like a recipe for nasty stuff > to happen on the inputs. (Note to self: must check > data sheet; how much hysteresis do they have on > FPGA inputs these days?) Of course you will be > applying all sorts of filtering, debouncing and other > good stuff to the signals once inside the FPGA, but... They are deliberately slugged and will have a couple of ms debouncing inside the FPGA as you've guessed. These could be reduced after initial system tests. > You can get clamp diode arrays in reasonably small > packages; would that help? I think I've convinced myself that omitting some sort of voltage clamp will be a false economy, I'll look into the smallest/cheapest way of implementing it. >>Because of the signal density, cost and restrictions of board >>space I am unable to implement any voltage regulation/clamping >>pre the FPGA inputs. > > That statement bothers me a little. If these are the usual 24V > industrial sensor type inputs, then each input has a cost and > space penalty associated with it (connectors, wiring, EMC > filtering gubbins like clamp-on ferrites...) that > vastly outweighs the cost and area of a couple of small SM > components. I know that sometimes we poor electronics > grunts are squeezed into absurdly tight spaces because > "the electronics doesn't take up much room, does it?". > But there's also the small matter that these > 24V signals probably come from badly-shielded wiring > that's spent most of its life in close proximity to a 5kW > electric motor, or an arc welding set, or some other > macho equipment. I used to reckon that effort spent > on dealing with those risks in a paranoid way *always* > paid for itself in reduced hassle later. > If your electrical environment is much kinder than > I was used to, then please forgive my irrelevant > ramblings. It should be a bit less noisy (hopefully), but you're right the filter/clamping is going in, reliability in service is important. Thanks for the feedback guys, it's been useful. NialArticle: 107827
The site seems to be working as it appears to me http://www.easics.be/webtools/crctool brucenutbrown@yahoo.com wrote: > Does anyone know what happened to the easics.com site ? I wanted to > use their CRC equation generator. This was working great a couple of > months ago, but now I realized I needed equations for a 64 bit wide > CRC-32 for ethernet, and the site seems to be missing. > > Alternatively does anyone have these equations handy, or know of > another equation generator ? Thanks, -BruceArticle: 107828
Hello John, >> Then, for whatever reason, several days later it would be obviously >> wrong if proofed again. > > Even skilled proof-readers find that. But even at first reading, it's > almost as if the errors are printed in a different colour, they are so > obvious. And this can extend to poor sentence construction, like 'only' > being in the wrong place. That can also happen if you regularly have to switch between languages several times a day. -- Regards, Joerg http://www.analogconsultants.comArticle: 107829
Jonathan Bromley schrieb: > On Fri, 1 Sep 2006 16:13:19 +0100, "Nial Stewart" > <nial@nialstewartdevelopments.co.uk> wrote: > > >I need to interface some 12 and 24V signals to an FPGA/CPLD, > >it'll probably be one of the low end Spartans or Cyclones. > >These are _very_ low bandwidth signals, 10's of hz at the most. > > Oh, tell me about it. In a previous existence, that sort of thing > was the bane of my life. Mind-numbingly simple stuff, but > there's no well-integrated support for it; it costs space, > components, PCB trackery, power supply fuss and bother, > and all manner of general horribleness. > > I would be very nervous of adding 100K-ish resistors in > series with an FPGA input; the very slow rise times you > would thus get sound to me like a recipe for nasty stuff > to happen on the inputs. (Note to self: must check > data sheet; how much hysteresis do they have on > FPGA inputs these days?) Of course you will be > applying all sorts of filtering, debouncing and other > good stuff to the signals once inside the FPGA, but... > > You can get clamp diode arrays in reasonably small > packages; would that help? > > >Because of the signal density, cost and restrictions of board > >space I am unable to implement any voltage regulation/clamping > >pre the FPGA inputs. > > That statement bothers me a little. If these are the usual 24V > industrial sensor type inputs, then each input has a cost and > space penalty associated with it (connectors, wiring, EMC > filtering gubbins like clamp-on ferrites...) that > vastly outweighs the cost and area of a couple of small SM > components. I know that sometimes we poor electronics > grunts are squeezed into absurdly tight spaces because > "the electronics doesn't take up much room, does it?". > But there's also the small matter that these > 24V signals probably come from badly-shielded wiring > that's spent most of its life in close proximity to a 5kW > electric motor, or an arc welding set, or some other > macho equipment. I used to reckon that effort spent > on dealing with those risks in a paranoid way *always* > paid for itself in reduced hassle later. > > If your electrical environment is much kinder than > I was used to, then please forgive my irrelevant > ramblings. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.bromley@MYCOMPANY.com > http://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. good points! if the inputs come from anywhere outside the closure then special care should be taken. this may be much more than the worry about the 3.3V inputs. I had even more bad problem - a wire about 1.5Meter long carrying 12V signal switched with a relay was "just in the same cable bundle" as a wire going to the reset input of Atmel AVR. and the result? the AVR microcontroller entered into a mode that allowed it to completly self erase itself - this is something Atmel claims not to be possible at all. Still it happened! Twice! The second time I asked someone else to verify my actions as I was testing the damaged silicon. The thing was inline flash programmer for Ericson mobile phone accessories (planned 500,000 yearly throughput). As project manager back then - brr, that explains why project managers are those who get gray hair! so if you have the FPGA connected to some external cable-bundle carrying 24V switching signals, then well all your client setup may call for trouble. So be as paranoid as you can, as already suggested. AnttiArticle: 107830
"Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message news:4lr10iF394osU1@individual.net... > I need to interface some 12 and 24V signals to an FPGA/CPLD, > it'll probably be one of the low end Spartans or Cyclones. > > These are _very_ low bandwidth signals, 10's of hz at the most. > > Because of the signal density, cost and restrictions of board > space I am unable to implement any voltage regulation/clamping > pre the FPGA inputs. > > I am planning to using a very large in line resistor (100K ?) to > limit current into the device pins. > > I know that one of the recommended techniques for interfacing to > 5V PCI signals is to use an in-line current limiting resistor. > What I'm planning is an extension of this but I've previously > always used quickswitches to clamp higher volates to safe limits > and intuitively don't like applying these higher voltages to the > pins. > > Should this be OK? > > Hi Nial, If the signal goes from 0V to 24V and if you've got room for a resistor, you've probably got room for a diode. Point the sharp end at the 24V signal, the blunt end towards the FPGA. Turn on the FPGA pin's internal pullup resistor. Viola! HTH, Syms.Article: 107831
I really must stop confusing French words with stringed instruments... :-(Article: 107832
> so if you have the FPGA connected to some external cable-bundle > carrying 24V switching signals, then well all your client setup may > call for trouble. So be as paranoid as you can, as already suggested. Don't worry, I am, I _know_ they're all out to get me. Why can't people come to me with nice simple jobs where someone else has done all the board design and they just want the FPGA internals configured? Clients, baaah, they're the bane of my life :-) NialArticle: 107833
Hello John, > > Don't, whatever you do, take a trip on 'old 97'! Or down the Feather River Canyon. Lots of derailments there but it's been quiet lately. -- Regards, Joerg http://www.analogconsultants.comArticle: 107834
John Woodgate wrote: > It's more rare in females. But there are 57 varieties of 'dyslexia'. Are > you left-handed? Tough call ... my mom trained me to be right handed. I'm nearly ambi. Twice (at 9 and 12) I dislocated my right arm and wore a cast for 3 months, learning to write left handed, and function left handed. Today, I tend to still favor right hand for writing and some tasks. My mom and son are both left handed. In 7th grade my son finally had a teacher that had a clue what my son was struggling with. Her daughter about the same age was also dyslexic, so she did her masters thesis on it. I was amazed at the long list of related "dysfunctional traits" that dyslexics share ... better than half I relate to. In that list are ADD and ADHD, which I share with both my mom and son, but didn't learn that much about until I needed to learn more about my son's "disabilities" (or gifts), which are worse than mine. I tend to self medicate with caffine when I need focus around distractions. But, I've never been able to function well in distractive environments, which included school and most cubical office environments, as I can not tune out the clatter of other people unless I'm "hyperfocused", at which point everything disappears in my world except the project I'm focused on (including phones, people trying to talk to me, etc). I've compensated over the years by working off-shift, frequently late afternoon into late evening, or from midnite to noon, so I have enough time with a less disruptive environment. In hyperfocus mode, I used to work 72 hours straight without caffine, then crash for a 12-18 hour sleep as soon as the task was completed. Some times 72 on, 18 off, for monthss at a time. I've never been "solar", even today. At 55, three day days wear me down, but I still knock off 48hr days a few times a year with little trouble. You learn not to do new design on the 2nd or 3rd day, as that skill does get impaired, but I can still debug and correct problems on the 2nd/3rd day with little impairment. There are advantages to easily knocking off 100+ hr weeks with extreme focus and productivity, which offset struggling with a normal 8-5 schedule in the clatter of a normal work environment. I just don't expect the rest of my team to pull this off, they are not wired that way, and need to keep a solar clock to remain productive. I'm also analytically functional when asleep, frequently answering the phone and talking coworkers thru a several hour disaster recovery without waking up, and being unaware of it the next day. I've also driven asleep, and was pulled over once in california at 5am asleep. It took the officer over 10 minutes to get me to pull over, and several minutes more to get me to roll down the window, and answer his questions. At one point, he screamed at me "tired hell", and I woke up, to full alert in seconds. It took him a while to realize I was asleep and not DUI. This used to drive my college girl friend nuts, as she would "wake me" to go on a date, I would get dressed, talk with her, and never wake up. Certainly, from this prospective, we are certainly not all created equal. And our weaknesses are just as likely to be our assets.Article: 107835
Rohini wrote: > Why is logic partioning considered better on pre mapped design only and > not on post mapped netlists ..... > > one reason i can see is that probbaly clustering will give good results > on pre mapped design ..... > > any inputs >?? You'ld be dead in the water without clustering the local signals. The mapper usually destroys any hint at what is local and what is not. The reason we have issues with this are simple: the languages don't allow the user to easily specify and group those signals that are not local. (The mapper would need to maintain that information.) The languages people use to code their logic are lame in this respect. They don't allow people to contextualize their nets or groups of nets. This is the main area HDL producers seem to forget. You want local signals mapped in with local objects. Current languages treat all nets as local signals really, even though the mapper can extract some of this from the name hierarchy. However, if you want to go between partitions (be it a single object/core, groups of objects/cores, chips, groups of chips, boards, groups of boards, etc.) you need to be able to define a net structure as a protocol set. That structure needs to include all the clock signals and every such thing that is necessary for synchronizing that data between partitions. You also need to be able to attach communication cores to it that are automatically inferred by the partitioning software. The other thing we do here by making this user-defined is that we drastically reduce the search space for the partitioning software. Consider that you want to split your algorithm across multiple chips. (Or you want to design software to do this.) Consider how fantastic it would be if you had a limited network of a synchronous data set that included enables, clocks, stalls, etc. More importantly, you would need to be able to specify a data rate for that data set. You also had a selection of communication cores to use to break that apart: one for the V2outgoing, one for S3 incoming, one for x86 host driver, etc. The possibilities are endless. The point is, that by having a breakable data set with known rates, we could partition our algorithm to take full advantage of the available hardware, without having to code each chip (or corner of the chip) individually. Cray has pretty much given up on the FPGA market because nobody produces tools to do this in a mixed-language, mixed-host fashion. I'm quite sad about that. I had hoped that they and SGI would push this issue into the main HDL table.Article: 107836
Joerg wrote: > Know what? What really bad typos indicate? Pretty clear, if someone > affords his or her resume that little attention to detail I assume it'll > be the same for a design. Can't use that. Anyway ... I hope the side discussion on dyslexia and related "gifts" will put a slightly different perspective on this point. I don't think it's correct or fair to assume the same will happen in a design, and you may well have just dismissed the best canidate. As a hiring manager, I've frequently rescued company "stars" from the discarded screened pile of other managers by looking past the resume, and focusing on the person behind it by using a much less restrictive "box" that people had to fit. I tend to inteview for work ethic, values, demonstrated ability to function well with project failures, diverse experiences, and a number of other factors which determine the person can easily learn the job at hand, or any other job I give them. I tend to write reviews the same way ... less concerned about their ability to handle 8-5 than their ability to deliver on schedule, and/or when things are VERY difficult. I also build teams with a diverse mix of personalities and skills, from those that can ONLY function in a well defined world, to those that CAN NOT function in a well defined world. It's a managers job to learn their people, and how to best use them. That includes being adaptive in work schedules and assignments based on the person, training, and oversight required. Some people need to be in way over their heads to be productive, others panic as soon as they are outside their safe zone and require much closer management when things are poorly defined. As a consultant, most project failures where caused by the manager being unable to assemble a diverse team, or manage it.Article: 107837
Mak wrote: > Can I use Block RAM for data storage in a system involving > micro-controller which writes into Block RAM as a buffer? I am bothered > about the timing as 8051 does not have data clock combination as is > required by block RAM. > Or Block RAM is just for local FPGA starage? Yep, you can interface Block RAM to an 8051. I have a SiLabs C8051F340 design that does just that -- it uses the block RAM as a display buffer for a simple LCD controller. Actually, the BRAM is implemented as a true dual port, and the sides have different clocks and different port widths. Works fine. The "micro" side of the memory is clocked by the '340's SYSCLK output at 48 MHz. -aArticle: 107838
In message <1157129794.829211.51030@i3g2000cwc.googlegroups.com>, dated Fri, 1 Sep 2006, fpga_toys@yahoo.com writes >Tough call ... my mom trained me to be right handed. I'm nearly ambi. >Twice (at 9 and 12) I dislocated my right arm and wore a cast for 3 >months, learning to write left handed, and function left handed. Today, >I tend to still favor right hand for writing and some tasks. How do you bat at baseball? > >My mom and son are both left handed. That figures. > >In 7th grade my son finally had a teacher that had a clue what my son >was struggling with. Her daughter about the same age was also dyslexic, >so she did her masters thesis on it. Yes, it's shockingly under-recognized. >I was amazed at the long list of related "dysfunctional traits" that >dyslexics share ... better than half I relate to. In that list are ADD >and ADHD, which I share with both my mom and son, but didn't learn that >much about until I needed to learn more about my son's "disabilities" >(or gifts), which are worse than mine. That goes with only some of the 57 varieties; others show opposite traits. > >I tend to self medicate with caffine when I need focus around >distractions. But, I've never been able to function well in distractive >environments, which included school and most cubical office >environments, as I can not tune out the clatter of other people unless >I'm "hyperfocused", at which point everything disappears in my world >except the project I'm focused on (including phones, people trying to >talk to me, etc). I've compensated over the years by working >off-shift, frequently late afternoon into late evening, or from midnite >to noon, so I have enough time with a less disruptive environment. I had one VERY good design engineer who could only work in a cubicle; in an open lab he was really stressed. > >In hyperfocus mode, I used to work 72 hours straight without caffine, >then crash for a 12-18 hour sleep as soon as the task was completed. >Some times 72 on, 18 off, for monthss at a time. I've never been >"solar", even today. At 55, three day days wear me down, but I still >knock off 48hr days a few times a year with little trouble. You learn >not to do new design on the 2nd or 3rd day, as that skill does get >impaired, but I can still debug and correct problems on the 2nd/3rd day >with little impairment. There are advantages to easily knocking off >100+ hr weeks with extreme focus and productivity, which offset >struggling with a normal 8-5 schedule in the clatter of a normal work >environment. I just don't expect the rest of my team to pull this off, >they are not wired that way, and need to keep a solar clock to remain productive. Quite. That waking pattern can stress family life. You have an understanding partner. > >I'm also analytically functional when asleep, frequently answering the >phone and talking coworkers thru a several hour disaster recovery >without waking up, and being unaware of it the next day. I've also >driven asleep, and was pulled over once in california at 5am asleep. It >took the officer over 10 minutes to get me to pull over, and several >minutes more to get me to roll down the window, and answer his >questions. At one point, he screamed at me "tired hell", and I woke up, >to full alert in seconds. It took him a while to realize I was asleep >and not DUI. This used to drive my college girl friend nuts, as she >would "wake me" to go on a date, I would get dressed, talk with her, >and never wake up. WOW! > >Certainly, from this prospective, we are certainly not all created >equal. And our weaknesses are just as likely to be our assets. You must have the courage to exploit them as assets and NOT take the mob's view of them as 'handicaps'. -- OOO - Own Opinions Only. Try www.jmwa.demon.co.uk and www.isce.org.uk 2006 is YMMVI- Your mileage may vary immensely. John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UKArticle: 107839
What would people's opinion on using a 5V FPGA (or possibly large-I/O-count CPLD) for a new, but limited run in-house-product in this day and age be? This would be a USB-tethered lab/ATE/field-service/etc "universal interface" intended to replace some aging parallel-port driven devices not supported by modern PCs (especially laptops). The reason for a 5V part is that performance demands are very low, but it needs to interface with up to about 100 bits of 5v instrumentation control bus, driving as well as receiving. If I use a part with a 3.3v I/O voltage I need level translators. That means a much more complicated board. I realize not using translators exposes the FPGA to greater risk of damage from the outside world, but now that we have a good rework station changing out one blown FPGA isn't that much worse than changing out multiple blown translators. I'd also like to avoid the level translators to ease reconfiguration - I believe I can use the same FTDI USB chip to JTAG program the FPGA in addition to talking to it, and that would let my device driver download an appropriate FPGA configuration for any of our applications, which might need to change which pins are inputs or outputs on a bit-by-bit basis rather than the byte-by-byte basis most translators would support. Other than making sure to buy enough chips + spares up front, any reason not to use an older part like an original spartan? Any particular 5v devices with 100+ I/O's in non-BGA packages that might be more likely than others to hang around?Article: 107840
fpga_toys@yahoo.com wrote: > >>Know what? What really bad typos indicate? Pretty clear, if someone >>affords his or her resume that little attention to detail I assume it'll >>be the same for a design. Can't use that. > > Anyway ... I hope the side discussion on dyslexia and related "gifts" > will put a slightly different perspective on this point. I don't think > it's correct or fair to assume the same will happen in a design, and > you may well have just dismissed the best canidate. > With non-proofed stuff I agree, I'd never judge someone based on that. However, a resume sent in to a company where you really would like to work is such an important advertising medium that I can't understand why someone wouldn't have it proofed by at least one other person. After all, it's the one and only thing that a potential employer initially has from you. Almost like what an expensive newspaper ad is to a manufacturer. The CEO there would go ballistic if that contained typos, and rightfully so. > As a hiring manager, I've frequently rescued company "stars" from the > discarded screened pile of other managers by looking past the resume, > and focusing on the person behind it by using a much less restrictive > "box" that people had to fit. I tend to inteview for work ethic, > values, demonstrated ability to function well with project failures, > diverse experiences, and a number of other factors which determine the > person can easily learn the job at hand, or any other job I give them. > Same here. But under work ethics I also count the ability to recognize when to hold'em and when to fold'em. IOW to see when it's time to call in a pro or someone who can double-check your work (or your resume if applying). [...] > > As a consultant, most project failures where caused by the manager > being unable to assemble a diverse team, or manage it. > Most failures that I see where caused by a team trying to avoid the expense for a consultant and going it alone. Once that had cost a company its very existence because the financial backers had lost faith in it after they couldn't make the product work. -- Regards, Joerg http://www.analogconsultants.comArticle: 107841
Joerg wrote: > With non-proofed stuff I agree, I'd never judge someone based on that. > However, a resume sent in to a company where you really would like to > work is such an important advertising medium that I can't understand why > someone wouldn't have it proofed by at least one other person. After > all, it's the one and only thing that a potential employer initially has > from you. Almost like what an expensive newspaper ad is to a > manufacturer. The CEO there would go ballistic if that contained typos, > and rightfully so. I make sure external documents are proofed by a professional. At the same time, I am who I am, and having a perfectly written resume doesn't necessarly reflect on who I am, does it? If someone is going to be anal about it, best get it over right away ... and there are some people that really are.Article: 107842
cs_posting, http://direct.xilinx.com/bvdocs/publications/ds060.pdf Is still right there, online, and up front. So yes, a new design with a 5V Spartan 4K part is not only do-able, but supported. Not sure what software supports it, but we always have the last version of software available for folks through our support web pages. I suggest you be careful about what schematic editor you choose, as I remember that we had a schematic editor that we needed to obsolete, as the vendor no longer would support license for its use. If you look through the notifications of "end of life" or "discontinue" http://www.xilinx.com/bvdocs/notifications/pdn2004-01.pdf You will find that there are some part/packages you should avoid. Given that, I think you can negotiate your way to obtaining sufficient supply, and support for a product without fear of getting caught in a situation of "no parts" for quite awhile (perhaps more than five years). When you choose a part, then you can register for any notifications, so that you will have an opportunity to place a "last time buy" order before you are in trouble. Sometimes, the whole world is not the right voltage. Hope this helps. Austin cs_posting@hotmail.com wrote: > What would people's opinion on using a 5V FPGA (or possibly > large-I/O-count CPLD) for a new, but limited run in-house-product in > this day and age be? This would be a USB-tethered > lab/ATE/field-service/etc "universal interface" intended to replace > some aging parallel-port driven devices not supported by modern PCs > (especially laptops). > > The reason for a 5V part is that performance demands are very low, but > it needs to interface with up to about 100 bits of 5v instrumentation > control bus, driving as well as receiving. If I use a part with a 3.3v > I/O voltage I need level translators. That means a much more > complicated board. I realize not using translators exposes the FPGA to > greater risk of damage from the outside world, but now that we have a > good rework station changing out one blown FPGA isn't that much worse > than changing out multiple blown translators. > > I'd also like to avoid the level translators to ease reconfiguration - > I believe I can use the same FTDI USB chip to JTAG program the FPGA in > addition to talking to it, and that would let my device driver download > an appropriate FPGA configuration for any of our applications, which > might need to change which pins are inputs or outputs on a bit-by-bit > basis rather than the byte-by-byte basis most translators would > support. > > Other than making sure to buy enough chips + spares up front, any > reason not to use an older part like an original spartan? Any > particular 5v devices with 100+ I/O's in non-BGA packages that might be > more likely than others to hang around? >Article: 107843
fpga_toys@yahoo.com wrote: > At the same time, I am who I am, and having a perfectly written resume > doesn't necessarly reflect on who I am, does it? > > If someone is going to be anal about it, best get it over right away > ... and there are some people that really are. I should also note that in nearly 40 years of interviews, I've never interviewed in a suit. That was casual dress western for 20 years, and jeans and a tee for the last 15. Both for W-2 work, and as a consultant. I've closed nearly every job I've interviewed for in person. Those that I haven't, have nearly always been interviewing for a less skilled/experienced manager that was late 20's to early 30's and worried about his job. I have ran into a few interviewing managers that was a turnoff for ... and we had a brief talk and parted. One hired me anyway, and was stressed that I would only dress to visit external customers when they needed engineering backup for Marketing/Sales. I tend to respect that sense of someone knowing who they are, and what they are good at when I inteview canidates as well. Those that are presenting a "fluffed up image" don't make it far with me.Article: 107844
In message <1157131840.061901.174970@m79g2000cwm.googlegroups.com>, dated Fri, 1 Sep 2006, fpga_toys@yahoo.com writes >Anyway ... I hope the side discussion on dyslexia and related "gifts" >will put a slightly different perspective on this point. I don't think >it's correct or fair to assume the same will happen in a design, and >you may well have just dismissed the best canidate. The point here is epitomized in Kipling's 'If', from which I think I will be extensively quoting, under a mild affluence of incohol. Point 1: 'If you can trust yourself when all men doubt you, **but make allowance for their doubting too** It's that second bit that matters. They WILL doubt you can do electronics if you can't spell. > >As a hiring manager, I've frequently rescued company "stars" from the >discarded screened pile of other managers by looking past the resume, >and focusing on the person behind it by using a much less restrictive >"box" that people had to fit. I tend to inteview for work ethic, >values, demonstrated ability to function well with project failures, >diverse experiences, and a number of other factors which determine the >person can easily learn the job at hand, or any other job I give them. Point 2: 'If all men count with you, but none too much.' > >I tend to write reviews the same way ... less concerned about their >ability to handle 8-5 [What is '8-5'?] >than their ability to deliver on schedule, and/or when things are VERY >difficult. Point 3: 'If you can fill the unforgiving minute/With sixty seconds' worth of distance run...' > >I also build teams with a diverse mix of personalities and skills, from >those that can ONLY function in a well defined world, to those that CAN >NOT function in a well defined world. Pint 4: 'If you can talk with crowds and keep your virtue..' > >It's a managers job to learn their people, and how to best use them. >That includes being adaptive in work schedules and assignments based on >the person, training, and oversight required. Some people need to be in >way over their heads to be productive, others panic as soon as they are >outside their safe zone and require much closer management when things >are poorly defined. Point 5: 'If you can dream, and not make dreams your master/If you can think, and not make thoughts your aim,/ If you can meet with Triumph and Disaster/ and treat those two impostors just the same.' > >As a consultant, most project failures where caused by the manager >being unable to assemble a diverse team, or manage it. Point six: 'Yours is the Earth, and everything that's in it/And what is more, you'll be a Man, my son.' -- OOO - Own Opinions Only. Try www.jmwa.demon.co.uk and www.isce.org.uk 2006 is YMMVI- Your mileage may vary immensely. John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UKArticle: 107845
fpga_toys@yahoo.com wrote: > Joerg wrote: > >>With non-proofed stuff I agree, I'd never judge someone based on that. >>However, a resume sent in to a company where you really would like to >>work is such an important advertising medium that I can't understand why >>someone wouldn't have it proofed by at least one other person. After >>all, it's the one and only thing that a potential employer initially has >>from you. Almost like what an expensive newspaper ad is to a >>manufacturer. The CEO there would go ballistic if that contained typos, >>and rightfully so. > > > I make sure external documents are proofed by a professional. > > At the same time, I am who I am, and having a perfectly written resume > doesn't necessarly reflect on who I am, does it? > > If someone is going to be anal about it, best get it over right away > ... and there are some people that really are. > Well, ok then, we just have different opinions here and that's fine. I consider a resume an "external document" because it does go external ;-) -- Regards, Joerg http://www.analogconsultants.comArticle: 107846
In message <hs_Jg.7349$q63.2180@newssvr13.news.prodigy.com>, dated Fri, 1 Sep 2006, Joerg <notthisjoergsch@removethispacbell.net> writes >Almost like what an expensive newspaper ad is to a manufacturer. The >CEO there would go ballistic if that contained typos, and rightfully so. I don't know whether the CEO went ballistic, but I can tell you that an ad for a Swedish sporty car (what a give-away - please disregard) in, of all places 'New Scientist', claimed a boot/trunk capacity in cubic litres. it was changed rather quickly, so ballistics may indeed have occurred. -- OOO - Own Opinions Only. Try www.jmwa.demon.co.uk and www.isce.org.uk 2006 is YMMVI- Your mileage may vary immensely. John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UKArticle: 107847
In message <hs_Jg.7349$q63.2180@newssvr13.news.prodigy.com>, dated Fri, 1 Sep 2006, Joerg <notthisjoergsch@removethispacbell.net> writes >Most failures that I see where caused by a team trying to avoid the >expense for a consultant and going it alone. Once that had cost a >company its very existence because the financial backers had lost faith >in it after they couldn't make the product work. Indeed. For a certain transportation project, around GBP5 billion, I believe, questions are asked about my fixed-price fee for 'two days' work. I've actually put in about four days so far, and it isn't over yet. -- OOO - Own Opinions Only. Try www.jmwa.demon.co.uk and www.isce.org.uk 2006 is YMMVI- Your mileage may vary immensely. John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UKArticle: 107848
On Thu, 31 Aug 2006 07:40:35 -0700, brucenutbrown wrote: > Does anyone know what happened to the easics.com site ? I wanted to > use their CRC equation generator. This was working great a couple of > months ago, but now I realized I needed equations for a 64 bit wide > CRC-32 for ethernet, and the site seems to be missing. > > Alternatively does anyone have these equations handy, or know of > another equation generator ? Thanks, -Bruce It looks like www.easics.be works but not www.easics.com.Article: 107849
Joerg wrote: > Well, ok then, we just have different opinions here and that's fine. I > consider a resume an "external document" because it does go external ;-) Agreed. The agreement to disagree is pretty rare in this forum of late. I suspect this is partly cultural too. My "style" has worked well in the western US. I'm aware that there are many places where it would be less than acceptable. It's been only reciently, that a dress code for professionals (including engineers) has been relaxed in some part of the US industry. Discussions with engineers in some other parts of the world, suggest that dress for success is still a critical asset in some work places. Have fun!
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