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Has anyone gotten Xilinx Impact to work under 64-bit Linux? Has Xilinx released Linux kernel 2.6 drivers for 64-bit? Thanks, -Chris -- | Christopher Cole, Cole Design and Development cole@coledd.com | | Embedded Electronics and Software Design http://coledd.com |Article: 108276
adress is not decoded ( BASE_HIT = 0 always ). Way?Article: 108277
> where I can read about use PCI-core user application signals? I use > this core in target mode. I whant to do standart microprocessor > protocol from userside of PCI-core. I'd start with the manual that comes with the core: it's the "documentation" checkbox on the core download page. When you realize that you need to understand PCI in general in order to read Xilinx's documentation on their PCI core, then I'd suggest you turn to the PCI spec, which you'll probably have to purchase from pci-sig.Article: 108278
"Why?" Has the memory space been configured in your cfg.v file? Has your system configured the FPGA's PCI BAR? If you are *brand* new to PCI, the Xilinx training on that core might do you a *world* of good. The next class appears to be November in San Jose, CA, USA. Just go to the Xilinx home page, Education and Training, then search on PCI. <axalay@gmail.com> wrote in message news:1157640708.818664.235670@b28g2000cwb.googlegroups.com... > adress is not decoded ( BASE_HIT = 0 always ). Way?Article: 108279
Hi, Please clarify me about blocking and nonblocking statement difference in RTL design. CODE1: always@(X or Y or Z) begin Q1 = X & Y; Q2 = Q1 & Z; end CODE2: always@(X or Y or Z) begin Q1 <= X & Y; Q2 <= Q1 & Z; end Theoritically Q2 in CODE 2 is assigned with the previous value of Q1&Z and Q2 in CODE 1 is assigned with the updated value of Q1&Z. But RTL design generated (after synthesis) for both codes are obsolutely same. If the RTL design mapped in to core is same then how these two codes function differently? In simulation we can see the difference because the compiler stores the previous value of Q1 in to temperory buffer and assigns to Q2. But in RTL design no buffer is available, so how can the functionality difference occurs in practicle? Thanks in advance. Regards, SruthiTeja.Article: 108280
Hi, Kindly clarify the following doubts on Two FF synchronizer. Most of the material available in net says the two flip-flop synchronizer is sufficient to remove all likely metastability. The first flip-flop samples the asynchronous input signal and waits for a full clock cycle to permit any metastability output signal to come to stable either 1 or 0. How can the ouput of the first FF will becomes stable before the next clock cycle? On what factors it will depend? (Theoritically it not guarenteed that Two FF synchronizer avoids metastability but proctically it is, how?) Whats vendors approach for the first FF to go to stable state before next sampling edge arrives? Whats information/insructions the vendor can provide designers regarding first FF settling time etc....? What are all the options available in the designer hand to make the two ff synchronizer work properly? Please make me clear. Thanks in advance. Regards, SruthiTeja.Article: 108281
himassk - Do some Googling. This topic is well covered in many papers that are available on the web. As you read, remember this rule of thumb: For synchronous logic, use non-blocking. For combinatorial logic, use blocking. Also - why are you posting this Verilog specific question to the FPGA newsgroup? John Providenza himassk wrote: > Hi, > > Please clarify me about blocking and nonblocking statement > difference in RTL design. > > CODE1: > always@(X or Y or Z) > begin > Q1 = X & Y; > Q2 = Q1 & Z; > end > > CODE2: > always@(X or Y or Z) > begin > Q1 <= X & Y; > Q2 <= Q1 & Z; > end > > Theoritically Q2 in CODE 2 is assigned with the previous value of > Q1&Z and Q2 in CODE 1 is assigned with the updated value of Q1&Z. > > But RTL design generated (after synthesis) for both codes are > obsolutely same. > If the RTL design mapped in to core is same then how these two codes > function differently? > > In simulation we can see the difference because the compiler stores > the previous value of Q1 in to temperory buffer and assigns to Q2. > But in RTL design no buffer is available, so how can the > functionality difference occurs in practicle? > > Thanks in advance. > > Regards, > SruthiTeja.Article: 108282
>>a 8 bit "=" needs at maximum 7 AND2 and 7 INV not 15 XOR2. And of course This threw me for a bit, then I realized you're comparing 8 bits with a constant value, not two 8 bit registers. -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 108283
>>>a 8 bit "=" needs at maximum 7 AND2 and 7 INV not 15 XOR2. And of course > > > This threw me for a bit, then I realized you're comparing > 8 bits with a constant value, not two 8 bit registers. Actually wouldn't you need 7 AND2 and 8 INV if you're comparing to 0? -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 108284
Read the Xilinx appnote XAPP094. http://direct.xilinx.com/bvdocs/appnotes/xapp094.pdf#search=%22xapp094%22 It gives you a feel for the probability of the first flip-flop reaching a stable state within a given time (in your case a whole clock period). As you will note, mettbility is a probabilistic event, there is no "guaranteed" solution. But when the Mean Time Between Failure (MTBF) is billions of years, the design can be considered pretty safe... Peter Alfke, Xilinx himassk wrote: > Hi, > > Kindly clarify the following doubts on Two FF synchronizer. > Most of the material available in net says the two flip-flop > synchronizer is sufficient to remove all likely metastability. > > The first flip-flop samples the asynchronous input signal and waits > for a full clock cycle to permit any metastability output signal to > come to stable either 1 or 0. > > How can the ouput of the first FF will becomes stable before the > next clock cycle? On what factors it will depend? > (Theoritically it not guarenteed that Two FF synchronizer avoids > metastability but proctically it is, how?) > > Whats vendors approach for the first FF to go to stable state before > next sampling edge arrives? > Whats information/insructions the vendor can provide designers > regarding first FF settling time etc....? > > What are all the options available in the designer hand to make the > two ff synchronizer work properly? > > Please make me clear. > > Thanks in advance. > > Regards, > SruthiTeja.Article: 108285
Andreas Ehliar wrote: > For fun I just created some graphs that show this at > http://www.da.isy.liu.se/~ehliar/stuff/place_and_route.html . The design Right arount 3.5ns constraint the PAR is able to succeed, and the time it takes to do so drops to a constant. The data seem to indicate the program is floundering around with no hope of success, and it finally gives up in failure. If it can succeed in meeting the constraints, it does so immediately. The more realistic situation is there are constraints that are attainable, just hard (and time consuming) for the PAR to accomplish. It's interesting in the PAR problem itself, that if you give it impossible constraints, it doesn't sit there forever trying. So either the program has some sort of timeout, or can conclusively prove to itself it has exhausted all possibilities. I'll bet PAR code would really benefit from getting moved to open source, if it's all closed-source + proprietary right now. -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 108286
Are you using ModelSIM or the Quartus internal SIM? Which "software" do you mean, when speaking about "created the .v file"?Article: 108287
Rob wrote: > Funny you should mention this. We came across the same issue, but we found > out the limitations of the memory interface before we decided to spin > boards. We ultimately went with an FPGA. You can't be an FPGA for parallel > processing. In our particular application an FPGA running at 67MHz out > performed the BlackFin running at 500MHz, all because of the FPGA's inherent > power of parallel processing. No argument here. In this particular project we outsourced the hardware design, but did all the software in house. We had limited time to review the hardware designer's choice for chips -- he did some digging and we were content to trust his instincts. Getting to the point where we would have studied the datasheet in terms of memory bandwidth...there's just no way we would have invested the time in that then. There would have been an element of faith that AD would have designed their memory controller efficiently. Realistically their SDRAM controller seems to be just an afterthought. I can't really see how it would be *that* hard to add in bursting...and it would completely solve the bottlenecks... Note AD = Analog Devices + this discussion is in regards to their blackfin line of DSP products. Not really FPGA's. :) -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 108288
Christopher Cole wrote: > Has anyone gotten Xilinx Impact to work under 64-bit Linux? > > Has Xilinx released Linux kernel 2.6 drivers for 64-bit? > > Thanks, > -Chris > 64 bit Linux support will be available early next year.Article: 108289
Hi , I am looking at tools to partition design onto Multiple FPGAs. Please let me know if anyone used/uses Certify and its pros/cons. Are there any other tools available ? Thanks, - sandeshArticle: 108290
Has your host configured the core? and have you checked that host isn't locked in a cycle waiting for a response? That's very easy to do if your backend logic isn't correct. If none of the latter and you can boot to Win 2K or XP try a utility called PCI32 and it will show you if you card is being "seen". Look for the vendor ID and device ID to identify your card in the list. If it hasn't changed the file cfg.vhd or equivalent has the vendor and device IDs in it. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 PCI Development Board. http://www.enterpoint.co.uk <axalay@gmail.com> wrote in message news:1157640708.818664.235670@b28g2000cwb.googlegroups.com... > adress is not decoded ( BASE_HIT = 0 always ). Way? >Article: 108291
Thank you very much for the tip. I realised my mistake. It works fine now. -DArticle: 108292
"John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote: >Has your host configured the core? and have you checked that host isn't >locked in a cycle waiting for a response? That's very easy to do if your >backend logic isn't correct. > >If none of the latter and you can boot to Win 2K or XP try a utility called >PCI32 and it will show you if you card is being "seen". Look for the vendor >ID and device ID to identify your card in the list. If it hasn't changed the >file cfg.vhd or equivalent has the vendor and device IDs in it. Pcitree is also a very good tool to do PCI diagnostics. I've used it extensively to test my design. Pcitree can also write to the configuration registers and access I/O and memory on the card. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 108293
Sylvain Munaut <SomeOne@SomeDomain.com> wrote: > Chao wrote: >> I am trying to use I2C to configure TI TFP410 DVI transmitter. I put >> differential clock input and VSYNC/HSYNC with the data. I suppose to get >> 1600x1200 image on the monitor. Basically, I just want to show a simple >> image and my hardware pins configuration is like below: >> >> DKEN (35) <--- GND >> /PD (10) <--- GND >> MSEN (11) <--- pull high >> EDGE (09) <--- float with a serial resistor 1k >> DE (02) <--- floating (since it should be ignored after I2C >> configured it as disabled) >> ISEL (13) <--- pull high >> Vref (03) <--- VDD >> >> I believe this chip should work with only input VSYNC/HSYNC, +/-CLOCK >> and 24bits DATA. Point me out if I am wrong. Thanks. > > Does the monitor display recognize the resolution but is all blank, or > does it just display "no signal" ? > > What values did you write in the I2C registers ? > > > Sylvain > The registers I set as: CTL_1_MODE (Addr 08H) <= 0xBF CTL_2_MODE (Addr 09H) <= 0x04 CTL_3_MODE (Addr 0AH) <= 0x90 DE_DLY (Addr 32H) <= 0x00 DE_CTL (Addr 33H) <= 0x70 DE_TOP (Addr 34H) <= 0x00 DE_CNT (Addr 37-36H) <= 0x06,0x40 DE_LIN (Addr 39-38H) <= 0x04,0xB0 H_RES (Addr 3B-3AH) <= 0x06,0x40 (1600) V_RES (Addr 3D-3CH) <= 0x04,0xB0 (1200) I am not sure do I need set DE_CNT, DE_LIN or not. But so far I set like above. The screen is all blank. It's not showing "no signal". However, I press the menu button on the monitor, it shows Resolution: 0x1@49Hz. I measured the DATA+/- on all three channels, they all are high with no sign of data or clocks. Regards, ChaoArticle: 108294
How do we apply a constrain to the Xilinx PAR tool to let it know that two clocks in the design are synchronous, and so the clock tree needs to be built with that in mind?Article: 108295
On Thu, 07 Sep 2006 03:19:32 GMT, "KJ" <kkjennings@sbcglobal.net> wrote: >I've long since found that more extensive simulation is many times much more >productive in weeding out the bugs than trying to debug on actual hardware. [...] Many, many thanks for a delightfully clear exposition of a vital idea. Just occasionally, the orders-of-magnitude faster throughput of tests that you win from a hardware prototype outweighs the pathetically bad observability and controllability of the physical hardware as compared with a simulation. Only occasionally, though. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 108296
Hi, I have about 4 different independent things that each need to access a ddr. On one hand it seems I can make them all wishbone compliant then just have a wishbone ddr interface. Would be workable/advisable to instead just have each device control the ddr itself, and use the ddr's own interface directly? I'd only need one complicated mechanism to initialize the ddr after reset, but from then on each of the user processes can just request access to the ddr, and when granted just take over the lines. One concern is that ddr timing at 100 mhz is pretty tight. Having the logic to combine 4 different sources into control signals for the ddr might add too much overhead. Of course it can be accomplished with a single LUT just doing a non-registered OR, if all 4 sources know to zero out their control lines when they're not the master... Any tips/advice welcome. Thanks-- Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 108297
Hi, I work on a board with an Altera 7128S part (5V quite old but still used ...). It seems the part is most of the time working just fine but depending on when it is powered on it overheats a lot and does not seem to be well configured : an input acts as an output, and the component is not working fine at all. Does anyone havea clue as to what could be going wrong ? It does not happen all the time. Thanks, JFArticle: 108298
On 7 Sep 2006 21:28:33 +0200, David Ashley <dash@nowhere.net.dont.email.me> wrote: >I have about 4 different independent things that each need to access >a ddr. > >On one hand it seems I can make them all wishbone >compliant then just have a wishbone ddr interface. > >Would be workable/advisable to instead just have each device >control the ddr itself, and use the ddr's own interface directly? Seems to me that your second idea would involve each device having a complete DDR access controller in it. That sounds like quite a bad idea to me; if you're going to make good use of SDRAM you need to keep track of the RAM's internal state to some extent (which banks are active, current row address, that sort of thing) and it would be very difficult for all four accessors to keep that kind of internal state in step. Of course, passing each client's requests to the RAM controller is sure to cost some latency if you use a common controller. If you have a custom controller (rather than a standard single-port controller on a common bus) then you can hide most of that latency in the arbitration delay, at the expense of some extra complexity. It's an interesting question, though. I need to deal with something quite similar in the immediate future, so any other ideas would be gratefully received! Oh, and does anyone have any strong opinions (positive or negative) about any of the available open-source DDR controllers? -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 108299
"Charlie Edmondson" <edmondson@ieee.org> wrote in message news:44ff2839$1@news.cadence.com... > Had a similiar situation when I worked on the 91 Express lanes toll road. > My boss was a real A-hole, who would do things like, pull out a knife and > shave his arms, commenting on how sharp it was, while asking for the > status of your assignments. The threat was very thinly veiled... That's when you pull out a mini butane torch and comment on how hot it is.
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