Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
"oopere" <oopere@netscape.net> wrote in message news:1163007119.654717.219530@m73g2000cwd.googlegroups.com... > > Of course, there is the possibility that I am missing some point. Any > hint? Do you have any idea *why* your cicuit doesn't work when it doesn't? That would be a useful clue. I've had a design break after a Quartus upgrade, but it was only because it was a bad design and a subtle change in timing caused it to break. (Inadequate use of timing constraints on the design concealed this.) I've also had one which wouldn't run when the FPGA was cold - I had to ship the equipment to a factory in the Pacific North West to find that one. That was an unsynchronised state-machine input - again, just subtle timing changes in an already-broken design. There are lots of things which make FPGA designs flakey, and despite what we'd like to believe, many of us are at least as unreliable as the toolchain... You only have to read this group for a couple of weeks to see how often people get the 'async input' stuff wrong, for example. Unless you're using 'incremental compilation' in Quartus, I think it always does start from scratch at the earliest phase necessary (I'm assuming 'smart compilation'). If you're really suspicious then delete the 'db' directory below your design. WillArticle: 111701
On Wed, 8 Nov 2006 04:51:24 -0800, Phil <mountaineering@web.de> wrote: >Hi, > >I would like to ask if somebody has come across the same problem: I need to convert a picture (bmp format) to a .hex or .mif file which will go into ROM's in a Stratix-2 FPGA. Do you know of any conversion utility which translates .bmp to .hex suitable for FPGA's? > >Thanks! Paint Shop Pro will save raw image bitmaps with no headers. You could load these into a device (eprom) programmer software and then save as a hex file (Assuming the hex file you mention is the same as the sort used for porgramming eproms etc. Some programmer makers do evaluation SW that works without the hardware present. I'm sure teher must also be binary to hex converter utils out there.Article: 111702
Will Dean wrote:
> "oopere" <oopere@netscape.net> wrote in message
> news:1163007119.654717.219530@m73g2000cwd.googlegroups.com...
> >
> > Of course, there is the possibility that I am missing some point. Any
> > hint?
>
> Do you have any idea *why* your cicuit doesn't work when it doesn't? That
> would be a useful clue.
>
No idea why it did not work:
Part of the original design:
signal[14..0]--|-----
| XOR >----DFF------out[14..0]
PN[14..0]------|-----
Even though "PN" changed at 15Mbit/s, "out" changed only at 1Mbit/s
(signal data rate)
I added a single xor for the MSBs of each:
signal[14]--|-----
| XOR >-----dummy_out
PN[14]------|-----
and routed dummy_out outside of the block and to an output pin. Then
everything is ok: "out" changes at 15Mbit/s.
The funny thing is that after removing the dummy_out, everything runs
fine now.
And, yes, I am pretty sure that I did not change anything else.
Pere
Article: 111703Davy wrote: > > I guess > gated clock does not behavior like original clock and introduce race. A gated clock will be delayed relative to the original clock, by the delay of the gate used to gate it. In a timing simulation, this will be a positive time delay. In a zero-delay simulation, this will be more like a delta cycle delay. In either case, this can introduce a race condition. If you have flip-flops A and B, where A is clocked by the original clock, and B is clocked by the gated clock, and the input of B is driven by A, then you have a potential race condition. The output of A can change before B is clocked by the delayed gated clock. It only works if the propagation delay from the clock through A to the input of B is greater than the propagation delay from the clock to the gated clock (actually, it has to exceed it by the hold time of B). This is true even in zero-delay, except that the delays are essentially delta cycles (and Verilog makes no guarantees about delta cycle ordering, so you cannot rely on anything here). This kind of problem is why some design methodologies forbid gated clocks, and require the use of clock enabled flip-flops instead.Article: 111704
On 8 Nov 2006 10:30:01 -0800, sharp@cadence.com wrote: > >Davy wrote: >> >> I guess >> gated clock does not behavior like original clock and introduce race. > >A gated clock will be delayed relative to the original clock, by the >delay of the gate used to gate it. In a timing simulation, this will >be a positive time delay. In a zero-delay simulation, this will be >more like a delta cycle delay. In either case, this can introduce a >race condition. > >If you have flip-flops A and B, where A is clocked by the original >clock, and B is clocked by the gated clock, and the input of B is >driven by A, then you have a potential race condition. The output of A >can change before B is clocked by the delayed gated clock. It only >works if the propagation delay from the clock through A to the input of >B is greater than the propagation delay from the clock to the gated >clock (actually, it has to exceed it by the hold time of B). This is >true even in zero-delay, except that the delays are essentially delta >cycles (and Verilog makes no guarantees about delta cycle ordering, so >you cannot rely on anything here). > >This kind of problem is why some design methodologies forbid gated >clocks, and require the use of clock enabled flip-flops instead. Or you build the moral equivalent with a feedback mux fronting the flip-flop. Adding skew to the equation for a gated clock just increases the intensity of the headache. Gated clocks are forbidden in the Reality-based Community ;-)Article: 111705
Dolphin wrote: > EPCS device controller info can be found on: > http://www.altera.com/literature/hb/nios2/n2cpu_nii51012.pdf The source files for the HAL are in the components directory of either the Nios or Quartus install. In this case, they are under quartus. The files you're interested in are altera_avalon_epcs_flash_controller.c/h as noted in the EPCS Device Controller Core with Avalon Interface document, page 3-5. You can glean the operation from these files or just include them in your build and use the HAL interface. Just using them should not affect which C library you use. Most likely, the issues you're running into with respect to the C library are due to using the IDE rather than setting up your own build. MarkArticle: 111706
Relevant to several recent threads, Altera just announced their Stratix III and with it Quartus 6.1 of which the first bullet item is: "Multiprocessor support: Allowing parallel processing during compilation for computers with multiple processors results in a reduction in compile times. Quartus II software offers the first multiprocessor support from an FPGA vendor to take advantage of the new multiple-core processors." The actual software is available *now* (according to the press release). Trying to get it reveals that *now* is really December 4th :-) I look forward to see how it scales with multiple cores. TommyArticle: 111707
Hello, Can anyone advise me where to find a clear timing model of Xilinx Spartan-3 family? The data sheet contains mainly timing table but with no clear explanation of the timing parameters. I am looking something like http://www.xilinx.com/bvdocs/appnotes/xapp375.pdf which is timing model for CoolRunner. I cannot find similar document for Spartan-3 in Xilinx’s web. Thank you for your help.Article: 111708
hi, i am doing the following project. can any one help me for VHDL coding for simulation on altium designer? or at least guid me with ideas to implement software without any errors. VHDL simulation and Implementation of CSMA and DCF of Wireless LAN Learn about the wireless LAN technique and system design, simulation and verification techniques for digital communication systems. Parts of the Medium Access Control (MAC) layer of the IEEE 802.11 Wireless LAN standard will be simulated and implemented in VHDL. hoping a positive reply..from you all experts in this area. thanks and regards vasuArticle: 111709
> I'm sure teher must also be binary to hex converter utils out there. SRecord (http://srecord.sourceforge.net/) converts to and from a lot of formats. It's the swiss army knife for loader file conversion, IMO :-) Hope this helps Arnim From paulu@sx4all.nl Wed Nov 08 13:12:27 2006 Path: newssvr27.news.prodigy.net!newsdbm04.news.prodigy.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newsfeed.media.kyoto-u.ac.jp!newsfeed.icl.net!colt.net!feeder.news-service.com!newsgate.cistron.nl!xs4all!transit3.news.xs4all.nl!post2.news.xs4all.nl!newszilla.xs4all.nl!not-for-mail Message-Id: <4552483a$0$10268$e4fe514c@dreader28.news.xs4all.nl> From: Paul Uiterlinden <paulu@sx4all.nl> Subject: Re: Modelsim problem - mixed VHDL,Verilog & VHO Newsgroups: comp.arch.fpga,comp.lang.verilog,comp.lang.vhdl Followup-To: comp.arch.fpga Date: Wed, 08 Nov 2006 22:12:27 +0100 References: <45501d41$0$3044$5a62ac22@per-qv1-newsreader-01.iinet.net.au> User-Agent: KNode/0.10.1 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 28 NNTP-Posting-Host: 213.84.176.29 X-Trace: 1163020346 dreader28.news.xs4all.nl 10268 213.84.176.29:10206 Xref: prodigy.net comp.arch.fpga:122699 comp.lang.verilog:34240 comp.lang.vhdl:67266 Mark McDougall wrote: > I'm having problems getting a simulation running. Here's the > recipe... > > Quartus output VHO file - contains VHDL & Verilog components. > Testbench components - VHDL & Verilog components. > > Note (and I *think* this is part of the problem) the VHO file > contains a certain verilog modle, whilst the testbench also contains > an instance of the same module, albeit with *different* parameter > values. Have a look in the ModelSim User's Manual, in chapter 'Compiling Verilog Files'. There is a paragraph "Handling sub-modules with common names". It mentions the special meaning of the vsim option -L work: "When you specify -L work first in the search library arguments you are directing vsim to search for the instantiated module or UDP in the library that contains the module that does the instantiation." I'm not sure if this is exactly your problem. -- Paul. www.aimcom.nl email address: switch x and sArticle: 111710
Is there any way to switch from a ucf file for an ML402 dev board to a ucf file for a ML403 board without having to delete one file from the project and copy the source from another ucf file? Can it automatically know what ucf file to use based on the FX12 or SX35 part? Brad Smallridge aivision dot comArticle: 111711
Hi, Hi, I am getting the following error when I create a peripheral of my own and then add it to the project. As you can see i created and imported a peripheral which has the name register_controller, the verilog file is named user_logic.v. Please help me with this error. Is this a bug in XPS which needs a patch? TIA At Local date and time: Thu Nov 09 03:25:56 2006 xbash -q -c "cd /cygdrive/c/projects/peripheral_test_no_ddr/; /usr/bin/make -f system.make bits; exit;" started... ********************************************* Running Xilinx Implementation tools.. ********************************************* xflow -wd implementation -p xc4vfx12ff668-10 -implement xflow.opt system.ngc Release 8.2i - Xflow I.31 Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. xflow.exe -wd implementation -p xc4vfx12ff668-10 -implement xflow.opt system.ngc Using Flow File: C:/projects/peripheral_test_no_ddr/implementation/fpga.flw Using Option File(s): C:/projects/peripheral_test_no_ddr/implementation/xflow.opt Creating Script File ... #----------------------------------------------# # Starting program ngdbuild # ngdbuild -p xc4vfx12ff668-10 -nt timestamp -bm system.bmm C:/projects/peripheral_test_no_ddr/implementation/system.ngc -uc system.ucf system.ngd #----------------------------------------------# Release 8.2i - ngdbuild I.31 Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -p xc4vfx12ff668-10 -nt timestamp -bm system.bmm C:/projects/peripheral_test_no_ddr/implementation/system.ngc -uc system.ucf system.ngd Reading NGO file 'C:/projects/peripheral_test_no_ddr/implementation/system.ngc' ... Loading design module "C:/projects/peripheral_test_no_ddr/implementation/microblaze_0_wrapper.ngc"... Loading design module "C:/projects/peripheral_test_no_ddr/implementation/mb_opb_wrapper.ngc"... Loading design module "C:/projects/peripheral_test_no_ddr/implementation/debug_module_wrapper.ngc"... Loading design module "C:/projects/peripheral_test_no_ddr/implementation/ilmb_wrapper.ngc"... Loading design module "C:/projects/peripheral_test_no_ddr/implementation/dlmb_wrapper.ngc"... Loading design module "C:/projects/peripheral_test_no_ddr/implementation/dlmb_cntlr_wrapper.ngc"... Loading design module "C:/projects/peripheral_test_no_ddr/implementation/ilmb_cntlr_wrapper.ngc"... Loading design module "C:/projects/peripheral_test_no_ddr/implementation/lmb_bram_wrapper.ngc"... Loading design module "C:/projects/peripheral_test_no_ddr/implementation/rs232_uart_wrapper.ngc"... Loading design module "C:/projects/peripheral_test_no_ddr/implementation/leds_4bit_wrapper.ngc"... Loading design module "C:/projects/peripheral_test_no_ddr/implementation/leds_positions_wrapper.ngc".. . Loading design module "C:/projects/peripheral_test_no_ddr/implementation/push_buttons_position_wrapper .ngc"... Loading design module "C:/projects/peripheral_test_no_ddr/implementation/dcm_0_wrapper.ngc"... Loading design module "C:/projects/peripheral_test_no_ddr/implementation/register_controller_0_wrapper .ngc"... Applying constraints in "system.ucf" to the design... Checking timing specifications ... INFO:XdmHelpers:851 - TNM "sys_clk_pin", used in period specification "TS_sys_clk_pin", was traced into DCM_ADV instance "dcm_0/dcm_0/Using_DCM_ADV.DCM_ADV_INST". The following new TNM groups and period specifications were generated at the DCM_ADV output(s): CLK0: TS_dcm_0_dcm_0_CLK0_BUF=PERIOD dcm_0_dcm_0_CLK0_BUF TS_sys_clk_pin*1 HIGH 50% Processing BMM file ... Checking expanded design ... ERROR:NgdBuild:604 - logical block 'register_controller_0/register_controller_0/USER_LOGIC_I' with type 'user_logic' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'user_logic' is not supported in target 'virtex4'. WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCS_GEN[0].REGCS_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCS_GEN[1].REGCS_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCS_GEN[2].REGCS_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCS_GEN[3].REGCS_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCS_SIZE_GEN[0].REGCS_SIZE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCS_SIZE_GEN[1].REGCS_SIZE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCS_SIZE_GEN[2].REGCS_SIZE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[0].REGCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[1].REGCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[1].REGRDCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[1].REGWRCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[2].REGCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[3].REGCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[4].REGCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[5].REGCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[6].REGCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[7].REGCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[8].REGCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[8].REGWRCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[9].REGCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[10].REGCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[10].REGRDCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[10].REGWRCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[11].REGCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[11].REGRDCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[11].REGWRCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[12].REGCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[12].REGRDCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[12].REGWRCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[13].REGCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[13].REGWRCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[14].REGCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[15].REGCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[16].REGCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[16].REGRDCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[16].REGWRCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[17].REGCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[18].REGCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[18].REGRDCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[18].REGWRCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[19].REGCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER _OUTPUTS.REGCE_GEN[19].REGRDCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[19].REGWRCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[20].REGCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[20].REGRDCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[20].REGWRCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[21].REGCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[21].REGRDCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[21].REGWRCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[22].REGCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[22].REGRDCE_FF_I' has unconnected output pin WARNING:NgdBuild:443 - SFF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/I_ADDRESS_DECODER/REG ISTER_OUTPUTS.REGCE_GEN[22].REGWRCE_FF_I' has unconnected output pin WARNING:NgdBuild:440 - FF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/INCLUDE_MASTER.I_MAST ER_ATTACHMENT/INCLUDE_MN_ABUS_SHADOW.MN_ABUS_SHADOW_GEN[30].FDE_I' has unconnected output pin WARNING:NgdBuild:440 - FF primitive 'register_controller_0/register_controller_0/OPB_IPIF_I/INCLUDE_MASTER.I_MAST ER_ATTACHMENT/INCLUDE_MN_ABUS_SHADOW.MN_ABUS_SHADOW_GEN[31].FDE_I' has unconnected output pin WARNING:NgdBuild:478 - clock net debug_module/bscan_drck1 with clock driver debug_module/debug_module/BUFG_DRCK1 drives no clock pins Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- NGDBUILD Design Results Summary: Number of errors: 1 Number of warnings: 55 One or more errors were found during NGDBUILD. No NGD file will be written. Writing NGDBUILD log file "system.bld"... ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow execution... make: *** [implementation/system.bit] Error 1 Done!Article: 111712
Dre wrote: > Basically i am looking for a way to get this cable working with the x64 bit version of windows - can somebody help me with this ??? > > Regards Dre Unfortunately, the drivers and iMPACT software for 64 bit platforms will not be available until the next release of ISE due in Jan, 2007Article: 111713
Thank you very much for your help. But I want to load data/program into the SRAM of that board, do you know how can I do that? Thanks again. On Nov 7, 3:27 pm, "Matthew Hicks" <mdhicks2@uiuc.edu> wrote: > If you are talking about the EEPROM or any other non-volatile on-board > memory, it should be detected by Impact. Just create an PROM file (.mcs) > from the .bit file and load it into the memory. All of this can be done > inside impact and should be detailed in the user manual for your board. > > ---Matthew Hicks > > "Jialin" <jiaojialin@gmail.com> wrote in messagenews:1162913626.614634.231140@m73g2000cwd.googlegroups.com... > > > > > Hi my friends, > > > We know little about Spartan and Xilinx. We are connecting our > > Spartan 3 starter kit board to a PC and using Xilinx ISE 8.1 to control > > it. > > > We want to find a way to load our program ( instructions) into the > > memory of > > the Spartan board. Could you tell me how? We will appreciate it if you > > could kindly show some light on this.- Hide quoted text -- Show quoted text -Article: 111714
Thank you very much for your help. But I want to load data/program into the SRAM of that board, do you know how can I do that? Thanks again. On Nov 7, 7:22 pm, "John_H" <newsgroup@johnhandwork.com> wrote: > If, on the other hand, you have a picoBlaze or MicroBlaze for which you want > to update the memory, the Spartan3E Starter Kit has that ready to go. > Source code is available. > > "Matthew Hicks" <mdhicks2@uiuc.edu> wrote in messagenews:eiqq83$819$1@news.ks.uiuc.edu... > > > > > If you are talking about the EEPROM or any other non-volatile on-board > > memory, it should be detected by Impact. Just create an PROM file (.mcs) > > from the .bit file and load it into the memory. All of this can be done > > inside impact and should be detailed in the user manual for your board. > > > ---Matthew Hicks > > > "Jialin" <jiaojialin@gmail.com> wrote in message > >news:1162913626.614634.231140@m73g2000cwd.googlegroups.com... > >> Hi my friends, > > >> We know little about Spartan and Xilinx. We are connecting our > >> Spartan 3 starter kit board to a PC and using Xilinx ISE 8.1 to control > >> it. > > >> We want to find a way to load our program ( instructions) into the > >> memory of > >> the Spartan board. Could you tell me how? We will appreciate it if you > >> could kindly show some light on this.- Hide quoted text -- Show quoted text -Article: 111715
"molecularelectronics@googlegroups.com" <vasulu.b@gmail.com> wrote in message news:1163019315.211987.95260@e3g2000cwe.googlegroups.com... > hi, > > i am doing the following project. can any one help me for VHDL coding > for simulation on altium designer? or at least guid me with ideas to > implement software without any errors. Wouldn't it be simpler to just ask for someone to do the project for you? > VHDL simulation and Implementation of CSMA and DCF of Wireless LAN > > Learn about the wireless LAN technique and system design, simulation > and verification techniques for digital communication systems. Parts of > the Medium Access Control (MAC) layer of the IEEE 802.11 Wireless LAN > standard will be simulated and implemented in VHDL. That sounds like a quote from a homework assignment. The spelling and grammar are much better than the previous paragraph, and it also instructs the reader to learn. > thanks and regards > vasu You're not by any chance Indian are you? It would be ironic if Western nations were outsourcing jobs to Eastern graduates who had outsourced their project work to Western engineers :-)Article: 111716
Phil wrote: > I would like to ask if somebody has come across the same problem: I > need to convert a picture (bmp format) to a .hex or .mif file which > will go into ROM's in a Stratix-2 FPGA. Do you know of any conversion > utility which translates .bmp to .hex suitable for FPGA's? I've got a small utility that converts BIN to HEX for exactly that purpose. However, I suspect you really want to convert your BMP to an uncompressed, raw bitmap first? If so, then as someone else suggested, use PaintShopPro or similar. I'd steer clear of MIFs - I used to use them but you run into problems when simulating using other tools. I can't think of any reason why you'd ever need MIFs rather than HEX files... Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 111717
Hi Dave, The placement of the fpga for chip to chip lvds in my board is about 1 to 1.5inch (distance), is that not possible? Anyhow, i don't really need such bandwidth for now, just want to make sure everything works fine, BTW, does a 100mil trace mismatch would work for LVDS pair? Thats approx. 25ps delay right? Ayon kay Dave Nunn: > You will not be able to achieve 622Mbps with Spartan 3 as the DCMs are > limited to 280MHz to yield a DDR bit rate of 560MHz. You might get > there with Spartan 3E. However, you will need to be extra careful with > source clocks (jitter) and SSO noise elsewhere on the receiver FPGA. > The jitter issue is especially important as I have noticed that cycle > to cycle jitter performance with DCMs isn't that great. I write from > experience of using Spartan 3 with LVDS links (albeit down a less than > ideal cable @ 500MHz). > > yy wrote: > > Hi Bob, > > I've matched the trace length withing 100mils is that OK? BTW, i use > > Spartan3 FPGA. > > Does having the DCI option in Spartan3 will eliminate the external > > termination resistor at the receiving end? > > One more thing, the other FPGA i'm using is Altera Cyclone-II FPGA(for > > this chip-to-chip connection)--and cyclone fpga needs at least 3 > > external resistors, my question is, > > can Spartan3's LVDS_DCI compensate for the external 'resistor network' > > at cyclone2, i mean if the DCI is enabled in spartan3 will there be no > > need for that resistors when cyclone2 is driving the LVDS line? > > > > Yy > > > > Ayon kay Bob: > > > "yy" <yy7d6@yahoo.com.ph> wrote in message > > > news:1162860919.587459.46830@m73g2000cwd.googlegroups.com... > > > > Hi i'm currently working on a high-speed chip-to-chip serial interface > > > > FPGA interface, i would like to know some suggestions regarding FPGA > > > > differential signalling; especially the trace matching of pair of LVDS > > > > signal, and the whole Channel (set of LVDS signals; Tx_Frame, Tx_Clk, > > > > Tx_Data) etc. > > > > My application is for 622Mbps signalling rate. > > > > Anyone has an experience on this? > > > > > > > > > > It's important to keep all signals' p-to-n length matched closely. This will > > > insure that there is a clean cross between the p and n inputs of the input > > > comparator during one-to-zero and zero-to-one transitions. You don't want a > > > p input to change from zero to one while the n input is still stuck at a > > > one. > > > > > > For signal-to-signal length matching (in a source synchronous bus), you must > > > consider the outputs' clock-to-out delay matching and the inputs' setup and > > > hold time. There is no way to determine the length matching requirements > > > without knowledge of the output and input characteristics. > > > > > > I would recommend using a FPGA family that has internal 100ohm differential > > > termination (within the input block). For Xilinx, this is V2Pro and above > > > (watch the VCCO requirements carefully). This will make layout easier and > > > give you the best setup and hold margin because at 622Mbps you're gonna need > > > all you can get. > > > > > > BobArticle: 111718
shaz.pecobian@gmail.com wrote: > im doing a project to implement single and double precision floating > point arithemetic units on Altera FPGA.Can someone please arrange me or > tell me any link from whr i can find the VHDL coding for the same.im a > beginner in the VHDL field. If you're looking for source code then you're not *doing* any sort of project at all - you're copying one. -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 111719
oopere wrote: > Of course, there is the possibility that I am missing some point. Any > hint? Did it meet timing? Were your timing constraints actually correct? Is it a synchronous design? Are you using gated clocks? Could be a lot of things before you point the finger at Quartus... Did you delete your 'db' directory and compile from scratch? Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 111720
Paul Uiterlinden wrote: > Have a look in the ModelSim User's Manual, in chapter 'Compiling > Verilog Files'. There is a paragraph "Handling sub-modules with > common names". It mentions the special meaning of the vsim option > -L work: Thanks, I'll check it out... Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 111721
Please look at the Spartan3E Starter Kit webpage http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3E-SK-US where, under the _Documentation_ heading you'll find the User Guide and the Reference Designs. The reference design includes a PicoBlaze with a memory loader that has both Verilog (or perhaps VHDL) source and an external utility to load the memory dynamically. The Picoblaze assembler will also generate a file that can be used as INITs in your BlockRAM instantiation. The JTAG related updates should be the same for Spartan3 as it is for the 3E. There are other memory-only update tools from Xilinx that might be easier. Search the Xilinx site (or Answers Database) for "coe" which is the memory file formate used for post-compiled memory updates. "Jialin" <jiaojialin@gmail.com> wrote in message news:1163025444.476315.65650@m73g2000cwd.googlegroups.com... > Thank you very much for your help. > > But I want to load data/program into the SRAM of that board, > do you know how can I do that? > > Thanks again. > > On Nov 7, 7:22 pm, "John_H" <newsgroup@johnhandwork.com> wrote: >> If, on the other hand, you have a picoBlaze or MicroBlaze for which you >> want >> to update the memory, the Spartan3E Starter Kit has that ready to go. >> Source code is available. >> >> "Matthew Hicks" <mdhicks2@uiuc.edu> wrote in >> messagenews:eiqq83$819$1@news.ks.uiuc.edu... >> >> >> >> > If you are talking about the EEPROM or any other non-volatile on-board >> > memory, it should be detected by Impact. Just create an PROM file >> > (.mcs) >> > from the .bit file and load it into the memory. All of this can be >> > done >> > inside impact and should be detailed in the user manual for your board. >> >> > ---Matthew Hicks >> >> > "Jialin" <jiaojialin@gmail.com> wrote in message >> >news:1162913626.614634.231140@m73g2000cwd.googlegroups.com... >> >> Hi my friends, >> >> >> We know little about Spartan and Xilinx. We are connecting our >> >> Spartan 3 starter kit board to a PC and using Xilinx ISE 8.1 to >> >> control >> >> it. >> >> >> We want to find a way to load our program ( instructions) into the >> >> memory of >> >> the Spartan board. Could you tell me how? We will appreciate it if you >> >> could kindly show some light on this.- Hide quoted text -- Show quoted >> >> text - >Article: 111722
Hi Tommy, > I look forward to see how it scales with multiple cores. On two cores we've seen between 1.6X and 1.9X the performance (depending on the algorithm) for the parallelized sections of code, yielding up to a 20% compile time reduction. Adding more cores gives you big speed-ups on those portions of code -- but Amdahl's Law kicks in pretty fast. The remaining single-threaded algorithms become a larger portion of the run-time as you add processors, diminishing the overall returns. FPGAs are getting bigger faster than CPUs are getting faster; this has been true for a long time. Without innovation in the software, compile times would grow with each generation. Thankfully, we've been able to close this gap, and even improve our run-time (and memory consumption) over time. Multi-cores is just the next step in this evolution. Modern CAD systems such as Quartus II contain numerous algorithms, all of which contribute significantly to the run-time of the system. Each algorithm presents its own challenges for parallization (if that's a word). Over time as we parallelize more and more of the tool, the benefits and scalibility will increase. Memory consumption is also a challenge as FPGAs continue to scale in size. Keeping memory use in check yields many benefits -- cheaper machines, sticking with 32-bit OSes, and better cache locality (and hence run-time). You'll find QII 6.1 (even for Stratix III) performs well on this metric too. > The actual software is available *now* (according to the press > release). Trying to get it reveals that *now* is really December 4th > :-) Customers can get the software today via their local Altera sales representative or distributor sales office. General/full availibility is December 4th as you've indicated. Regards, Paul Leventis Altera Corp.Article: 111723
Hi Mark,
The vho file cannot contain both VHDL and Verilog. If it does it is a
bug. Can you email me the vho file that is causing the problem?
Subroto Datta,
Altera Corp.
On Nov 6, 9:46 pm, Mark McDougall <m...@vl.com.au> wrote:
> I'm having problems getting a simulation running. Here's the recipe...
>
> Quartus output VHO file - contains VHDL & Verilog components.
> Testbench components - VHDL & Verilog components.
>
> Note (and I *think* this is part of the problem) the VHO file contains a
> certain verilog modle, whilst the testbench also contains an instance of
> the same module, albeit with *different* parameter values.
>
> Attempting to start the simulation under ModelSim ('vsim') loads a bunch
> of structures from the library, and then halts with an error that just
> does *not* make any sense at all!
>
> The error is "irda_peripheral.v(155) The width (1) of VHDL port
> 'addr_cnt_out_2' does not match the width (5) of its Verilog connection
> (3rd connection)".
>
> This error occurs in the file that contains a 2nd instance of the
> verilog module, and the 3rd connection is indeed a vector whose width is
> specified with a parameter - which incidently differs from the value for
> the instance inside the VHO file.
>
> However:
>
> * addr_cnt_out is internal to the VHO and not connected to the instance
> in this file at all.
> * neither of the parameters specify a width of '1' for the vector.
>
> I suspect Modelsim is getting confused between the instance in the VHO
> file and the instance in irda_peripheral.v and is having trouble wiring
> up the ports?!?
>
> Anyone else had a similar experience?
>
> Regards,
>
> --
> Mark McDougall, Engineer
> Virtual Logic Pty Ltd, <http://www.vl.com.au>
> 21-25 King St, Rockdale, 2216
> Ph: +612-9599-3255 Fax: +612-9599-3266
Article: 111724oopere wrote: > Today I have observed again a kind of unpredicatable behaviour in > quartus II that I had already experienced in another project. > > In each case, the situation was: > - A specific signal on a design does not work as expected. > - To debug, an output pin is added to monitor a signal around the > problematic part of the circuit. No other changes are made. > - As a consequence of adding this pin, the original signal works ok. > - The debugging pin is removed and the design works perfectly. > > It seems as if the compilation process is not 100% deterministic but > relies on previous runs. The same kind of problem has (had) been > experienced in quartus 4.2 and 5.1. Is there any option to force > quartus II to start each compilation from scratch? > > Of course, there is the possibility that I am missing some point. Any > hint? > > Thanks for your time > > Pere
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z