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"Ben Jones" <ben.jones@xilinx.com> wrote in message news:eif2gv$d6p1@cnn.xsj.xilinx.com... > > FPGA scientific computing OMG ponies 15 > :-) ...and you had the cheek to post that nonsense thread between me and Bob on your blog! Keep up the good work! Cheers mate, Syms.Article: 111501
"tullio" <tullio.grassi@gmail.com> wrote in message news:1162587092.602160.268940@h54g2000cwb.googlegroups.com... > > axalay ha scritto: > >> If this distanse is 70 mm may I hope that the devise is work correctly? >> And may I do not connect terminate resistor beetwin Rx- and Rx+ ? > > You have to look at the rise time (tR) and fall time of your signals. > My rule of thumb is that if distance D > (2/3)c tR; than you need > terminations. > > There are tons of documents on the subject. > Yep, the rise time is the indicator. IIRC the usual rule of thumb is 1/6 Tr, as you say tullio, there's plenty of stuff on the www. Cheers, Syms.Article: 111502
John_H wrote: > Dang. I'm happy I didn't just turn my board on with my new design and > expect it to work with possibly damaging results. > > I expected the board to be the exact same board as the 500E Starter Kit. There are quite a few differences, some surprising, but mostly it's good news, ie. J1 and J2 is no longer shared with FX2. Now if only they had allocated more bits to the video interface :-( > I'm getting the .ucf sent to me now and I'll pass it along to you, Tommy, at > your gmail address. It appears the status - even though we've purchased the > board - is kind of "pre-release" and we should expect more documentation in > the near future. AAAAAARRHHHGG :-) I had just painstakingly recreated the UCF based on Appendix B in the UG230 + the schematics differences. Oh well. Thank, I look forward to it. Regards, TommyArticle: 111503
tullio wrote: > axalay ha scritto: > >> If this distanse is 70 mm may I hope that the devise is work correctly? >> And may I do not connect terminate resistor beetwin Rx- and Rx+ ? > > You have to look at the rise time (tR) and fall time of your signals. > My rule of thumb is that if distance D > (2/3)c tR; than you need > terminations. Assuming he is using the Xilinx FPGAs, the FPGA has internal terminations. He should not be adding external termination resistors on the Rx signals.Article: 111504
JJ wrote > > Still the basic decider is likely to be whether one knows how to even > start a FPGA. project. Yes. Start by looking at scientific apps on GPUs: www.gpgpu.orgArticle: 111505
Anonyma wrote: > The 20 ns period seems not large enough to accommodate > the pad delay and external loading. A simple testing > circuit shows that about 0.2% read errors. Follow the bouncing links from this old post for some notes about write strobe generation timing, and some SRAM test code for the S3 starter kit. http://groups.google.com/group/comp.arch.fpga/msg/ee222450bf8e47c8 BrianArticle: 111506
Duane Clark wrote: > tullio wrote: >> axalay ha scritto: >> >>> If this distanse is 70 mm may I hope that the devise is work correctly? >>> And may I do not connect terminate resistor beetwin Rx- and Rx+ ? >> >> You have to look at the rise time (tR) and fall time of your signals. >> My rule of thumb is that if distance D > (2/3)c tR; than you need >> terminations. > > Assuming he is using the Xilinx FPGAs, the FPGA has internal > terminations. He should not be adding external termination resistors on > the Rx signals. And the SFP module should also have its RX pins terminated (and AC coupled) in the module. The TX pins are also AC coupled in the module. Ed McGettigan -- Xilinx Inc.Article: 111507
Hi All, Does anyone know when I should "Clean all generated files" in Xilinx 8.2i EDK? Should it be done before or after doing import of your user peripheral after you have made some changes to it? The analogous procedure should of course always be done in ISE before rebuilding your project with changes. For example, in the installed html help files, it says: "The Clean All Generated Files command removes the generated files from a specific task. For example, the Platform Generation tool (Platgen), which is invoked using the Generate Netlist command, generates the netlist files from the source VHDL code. When you clean the process, the generated netlists are removed." (file:///C:/EDK/doc/usenglish/help/platform_studio/platform_studio.htm#html/ps_c_gst_whatsnew.htm) Can anyone tell me where I can find documentation on what I need to clean and how I go about selecting a process so I can clean its files? It would be nice if I don't have to spend hours redoing BSB every time I want to make sure I have a fresh and true build of what I think I'm building. Thanks in advance, -James From przemek@tux.dot.org Fri Nov 03 21:48:41 2006 Path: newssvr14.news.prodigy.com!newsdbm05.news.prodigy.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!border1.nntp.dca.giganews.com!nntp.giganews.com!local01.nntp.dca.giganews.com!nntp.comcast.com!news.comcast.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 03 Nov 2006 23:48:41 -0600 From: przemek klosowski <przemek@tux.dot.org> Subject: Re: Scientific Computing on FPGA Date: Sat, 04 Nov 2006 00:48:41 -0500 User-Agent: Pan/0.14.2 (This is not a psychotic episode. It's a cleansing moment of clarity.) Message-Id: <pan.2006.11.04.05.48.40.965168@tux.dot.org> Newsgroups: comp.arch.fpga References: <1162518049.124275.221090@k70g2000cwa.googlegroups.com> <1162544398.850586.139980@m73g2000cwd.googlegroups.com> <454b6f70.2576595738@news.kpnplanet.nl> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 17 NNTP-Posting-Host: 68.33.148.241 X-Trace: sv3-rlmMUV+hrHxsLwBhL1MRNzi8vrGNr8+8Xqp4ajASIjv/1BmwpOHPMXDS8es4d1wA2jiRMt0I7d+Y/CY!lHaHpe/BUk7nOQqkJvK7n/9g42suuun92vC2XM1nVwAxjn8c6wcivajSyKTxPfwNIfNNheOwp7bL!5jDki8nkbt5q X-Complaints-To: abuse@comcast.net X-DMCA-Complaints-To: dmca@comcast.net X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.32 Xref: prodigy.net comp.arch.fpga:122490 On Fri, 03 Nov 2006 16:36:12 +0000, Nico Coesel wrote: > helmut.leonhardt@gmail.com wrote: > >>Everything what can parallelize is possibly running faster in Hardware >>than in Software. On Fri, 03 Nov 2006 16:36:12 +0000, Nico Coesel wrote: > Still, the amount of processing power a modern PC processor can deliver is > enormous. It is problably more cost effective to optimize an algorithm to > run parallel on 10 PC's than to develop a specific FPGA solution. If space > is a constraint, the answer is in using blade servers. Plus, the FPGA can be clocked at say 200 MHz, 10 times less than the the CPU. Of course that doesn't mean that the CPU will be 10x faster, but the CPU's 'speed of light' is definitely much larger.Article: 111508
Thank for all !!! You are help me very much!Article: 111509
:) are you serious or it is joke? (it about distanse 70 and 71 mm) "Duane Clark =D0=BF=D0=B8=D1=81=D0=B0=D0=BB(=D0=B0): " > axalay wrote: > > If this distanse is 70 mm may I hope that the devise is work correctly? > > And may I do not connect terminate resistor beetwin Rx- and Rx+ ? > > > > I am currently using on SFP module at a distance of 71 mm. I don't use > external termination resistors, if that is what you mean.Article: 111510
I wrote a very detailed description of how the various modes of writing and reading of the block RAMs occurs with details of the way activity on one port affects the other port depending on the write mode. You can find it here: http://www.fpga-faq.com/archives/72675.html#72693 I hope this helps you. =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORGArticle: 111511
May I connect 11 PCI cards (in each I use Xilinx FPGA) in one PCI bus, if use to generate IDSEL signals AD 12...AD31 lines. One card is master and other is slave.Article: 111512
<lancepickens@gmail.com> wrote in message news:1162518049.124275.221090@k70g2000cwa.googlegroups.com... > Hi, > Coming from a scientific computing standpoint (with no hardware > experience). > I was wondering if you can improve any dedicated tasks > by designing special purpose chips a la FPGA to run your code? Video/audio coprocessing? DNA pattern searching is a good example. Already been done though. Some jobs (e.g. running an OS) are best suited to general purpose microprocessors, and some (like video display controllers) demand high-speed yet relatively simple workings and are ideal for dedicated hardware. If you're looking for a big idea, it is best to look for applications that need a vast amount of small simple operations? How about doing OCR front end to correlate 2D-images with many font characters simultaneously?Article: 111513
On 3 Nov 2006 05:05:24 -0800, "radarman" <jshamlet@gmail.com> wrote: >Anonyma wrote: >> Hi, >> >> This is a question about digilent spartan-3 starter board , >> which has a simple 10ns sram and 20ns clock. >> ... A simple testing >> circuit shows that about 0.2% read errors. >> Is it possible to put some timing or other constraints >> in the ucf file to help timing? Thanks. > >One thing to check is that your final output flops are being mapped to >pad registers, and not internal registers. That will eliminate any >variability in prop delay due to different paths in the fabric, Very important. In addition to eliminating variability, in Xilinx parts it can eliminate about 4ns of routing delay in each path ( = 8ns for the round trip ). >I'm not sure how to do that in ISE, though - I use mostly Altera at the >moment. To check what's going on in this respect, look at the .mrp (Map Report) file in ISE. The IOB section (near the end) lists INFF, OUTFF (or OFF) and ENBFF for input, output and tristate flipflops in the IPB respectively. To modify what's happening, there are a number of hoops to jump through. The first is to enable "map FFs into IOBs" settings in the tools; most of the others relate to preventing ISE from optimising away useful signals, like the FFs you need (e.g. if they are shared with internal logic). Apply "keep" attributes to prevent signals disappearing, and "equivalent_register_removal" = "false" attributes to appropriate registers. And keep trying until the right behaviour is reported in the .mrp file. - BrianArticle: 111514
Kolja Sulimma wrote: > rickman schrieb: > > Will Dean wrote: > > > >>"Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message > >>news:454a42f8$1@clear.net.nz... > >> > >>>yes, but I'm really interested to see how you design with discrete > >>>logic, and still get 40% reserve capacity - I know, use a > >>>HEF4894, when a HEF4794 would do ! :) > >> > >>And I was interested in the 'eight or so' chips which fit into the space of > >>the TQFP-100... > >> > >>Will > > > > > > Three dual 4 input muxes (analog switch based), a 4 bit counter, a dual > > tri-state buffer, a dual NAND gate and a dual FF. Together with two 8 > > bit SPI port relay drivers, they all fit in a 10 x 20 mm area. > Up to here, I count only 33 macrocells, probably less. This logic is only 15 or so MC. The part that controls the relays is a bit more complex. I don't recall the exact MC count, but it was in the low 50's for the whole shooting match, but that was not a formal, complete analysis and would likely grow a bit. Then we have a requirement for 40% spare capacity so that we can accommodate later revisions and updates. That puts the design clearly in the 128 MC part. > The > > smallest CPLD I can easily use is a 128 macrocell part in a 100 pin > > TQFP at 16 mm sq package and still requires the two relay drivers plus > > a JTAG header. > > Why not use a 64MC device in CS package? Actually, it has occured to me that I could do a combined approach using a 32 or 64 MC CPLD to replace the discrete logic only and not the relay drivers. An MCU could do the job of sorting out the SPI data and provide "intelligence" for driving the relays. The MCU would have to be very low power, but that might be doable with adequate power management. To be honest, the hard part of all this is the working atmosphere. The moment I suggested that we needed to change the basic design I was inundated with arguments. I am supposed to be the lead engineer on this module and I don't get to make any decisions without the approval of a ton of others - very, very frustrating. Now I am very hesitant to even consider any deviations just because of the gauntlet I will have to run again.Article: 111515
kollarameshk@gmail.com schrieb: > Hi, > I need help for solving the following problem.I am trying to > connect to ML461 JTAG port from PC parallel port by using XILINX > parallel cable through chipscope.But it couldn't connect properly.It > gives the following error. > > ERROR: Socket Open Failed. localhost/127.0.0.1:50001 > localhost > java.net.ConnectException: Connection refused: connect > ERROR: Failed to open Xilinx Parallel Cable. See message(s) above. > > And the same cable setup works properly with the another same board. > > I really appreciate your help. > > Thanks, > -Ramesh > Hi Ramesh, and if you try to connect through impact. Does this work? If so, check the configuration for ChipScope. However I'am not shure if the parallel port POT is still fully supported. You may have a chance to test the USB JTAG Pot ... Cheers MarcArticle: 111516
axalay schrieb: > May I connect 11 PCI cards (in each I use Xilinx FPGA) in one PCI bus, > if use to generate IDSEL signals AD 12...AD31 lines. One card is master > and other is slave. > Hi, actually I have no PCI spec at hand. However 11 PCI loads seems to be far more than I have used, even in Compact PCI Setups ... CheersArticle: 111517
axalay a écrit : > May I connect 11 PCI cards (in each I use Xilinx FPGA) in one PCI bus, > if use to generate IDSEL signals AD 12...AD31 lines. One card is master > and other is slave. > Hi The PCI rule of thumb is "no more than 10 loads on a single bus", a PCI connector counting for 1 load (thus a card in a slot counts for 2 loads) You may need to add PCI-PCI bridges to split your bus. NicolasArticle: 111518
Roberto schrieb: > I am trying to use Xilinx chipscope, but it is not working properly > (probably mishandling by the user...). Perhaps somebody can give me > some light... > > I used core inserter, and I have a ICON and a ILA core. > I want to monitor a SPI bus in a 2VP2 device, that has 12 RAM blocks > available. > I defined a 1 trigger port with width 1, set with the sclk (that > should be around 10MHz). > And I have a 40 data width bus where I try to see many data signals. > > I can go to the point where I generate the programming file (bit file). > Startup clock is set to JTAGclk, keep hierarchy is set to YES. I also > generate (just in case) the mcs file and load my 18V04 EEPROM. I > recicle power and then I click in the Analyze Design Using Chipscope. > After opening the JTAG Chain (XILINX Parallel IV cable), it says that > it found 1 core unit in the JTAG device Chain. But if I press the > "trigger now" button, it does not give me the status of the lines. It > enters a mode where it says"siting for core to be armed." and stays > there forever. Am I setting the trigger in a wrong way? > > We are talking about versions 7.1 os ISE and chipscope pro. > > I would appreciate any input! > Hi, Did you Configure the Trigger? Think of ChipScope as a Scope. If you do it similar, it will work Cheers MarcArticle: 111519
"Symon" <symon_brewer@hotmail.com> wrote in message
news:454bd769_3@x-privat.org...
> "Ben Jones" <ben.jones@xilinx.com> wrote in message
> news:eif2gv$d6p1@cnn.xsj.xilinx.com...
>>
>> FPGA scientific computing OMG ponies 15
>>
> :-)
> ...and you had the cheek to post that nonsense thread between me and Bob
> on your blog! Keep up the good work!
Some things deserve to be preserved for prosperity. :-D
Surprised you found the blog though, must be more careful with my robots.txt
in future...
Cheers,
-Ben-
Article: 111520Jhlw wrote: > Hi All, > > Does anyone know when I should "Clean all generated files" in Xilinx > 8.2i EDK? Should it be done before or after doing import of your > user peripheral after you have made some changes to it? > The analogous procedure should of course always be done in ISE > before rebuilding your project with changes. There are only two situations where I have cleaned the generated files. One is when I wanted to make a compressed (zip) copy of the directory, either for backup or to send to Xilinx in support of a webcase. The other is if I want to force EDK to resynthesize the design (via Export to Projnav). Otherwise I never bother and have seen no ill effects. I wouldn't say "[t]he analogous procedure should of course always be done in ISE before rebuilding your project with changes". ISE has always recognized when there are source code changes and will rebuild accordingly. Plus, there is a right-click method to force any processing flow step. Cleaning is useful if you want to reduce the size of a backup. --- Joe Samson Pixel VelocityArticle: 111521
Not quite 11 buy we have something like 6 way arrays of our products. Basically the maximum a standard motherboard we have does. If you are doing a custom system essentially based on PCI then there is a good chance that it will work providing either the bus segments on your motherboard are not too long or you can slow the clock rate down a little. Propagation time and keeping it down is the key. If these are your own cards you should have a good idea of your I/O timing and what margin you have to play with. Otherwise if your are using cards by outside vendors then there is a possability not meeting timing if they are relatively slow. There are also lots of things either not covered very well by the PCI spec or simply things people have chosen to ignore so be slightly beware. The words compatible and compliant come to mind. The usual problem comes if your cards want to be bus initator capable and you need support for the grant and request lines. If you case sounds like you are just using them as slaves so that should not be an issue. John Adair Enterpoint Ltd. axalay wrote: > May I connect 11 PCI cards (in each I use Xilinx FPGA) in one PCI bus, > if use to generate IDSEL signals AD 12...AD31 lines. One card is master > and other is slave.Article: 111522
One thing to check is that Impact is not open when using Chipscope. I have seen cases of Impact affecting chipscope operation. John Adair Enterpoint Ltd. kollarameshk@gmail.com wrote: > Hi, > I need help for solving the following problem.I am trying to > connect to ML461 JTAG port from PC parallel port by using XILINX > parallel cable through chipscope.But it couldn't connect properly.It > gives the following error. > > ERROR: Socket Open Failed. localhost/127.0.0.1:50001 > localhost > java.net.ConnectException: Connection refused: connect > ERROR: Failed to open Xilinx Parallel Cable. See message(s) above. > > And the same cable setup works properly with the another same board. > > I really appreciate your help. > > Thanks, > -RameshArticle: 111523
Hi guys,
I'm trying to connect a simple co-processor to microblaze. The
co-processor simply gets 8 inputs and does a simple arithmetic and
gives one output. The problem that I'm currently experiencing is (I
figured it out during simulation) that, when I put a data from
microblaze on FSL the fsl_m_write signal from microblaze doesn't become
1. So the co-processor never notices that there are data on the bus and
it never changes status. As well when I check the data on the FSL
microblaze-to-coprocessor bus, it is not what I'm trying to write. Put
instruction takes 2 cycles to execute. The first cycle the data on FSL
master output of microblaze is insane but the second cycle it becomes
one. However I've made sure that FSL_M_FULL is not 1. So my FIFO is
empty. The clk and reset signal of the co-processor is correctly
connected to the processor. As well I'm doing blocking read and write.
Do you have any idea why it is not working?
I've attached part of my system.v file. As far as I know all the
connections are correct. (I used co-processor wizard from EDK to
connect my co-processor to microblaze).
By the way just before attaching the code to here I checked to make
sure that clock and reset connection is OK. Previously during
simulation I checked the clock and reset and they were working fine.
However now in the system.v file as you can see below there is no clock
signal given as the input to fsl of microblaze or co-processor. However
it is working fine during simulation. I tried to set the clock port to
sys_clk_s but it seems that it has serious problem. Because my
simulation is working as if the fsl buses and peripheral is not
clocked.(ilmb_LMB_ABUS and microblaze/fsl_m_data become high
impedance).
I really appreciate your help,
Amir
microblaze ....
.FSL0_S_CLK ( ),
.FSL0_S_READ ( custom_ip_0_to_microblaze_0_FSL_S_Read ),
.FSL0_S_DATA ( custom_ip_0_to_microblaze_0_FSL_S_Data ),
.FSL0_S_CONTROL ( custom_ip_0_to_microblaze_0_FSL_S_Control ),
.FSL0_S_EXISTS ( custom_ip_0_to_microblaze_0_FSL_S_Exists ),
.FSL0_M_CLK ( ),
.FSL0_M_WRITE ( microblaze_0_to_custom_ip_0_FSL_M_Write ),
.FSL0_M_DATA ( microblaze_0_to_custom_ip_0_FSL_M_Data ),
.FSL0_M_CONTROL ( microblaze_0_to_custom_ip_0_FSL_M_Control ),
.FSL0_M_FULL ( microblaze_0_to_custom_ip_0_FSL_M_Full ),
////////////
custom_ip_0_to_microblaze_0_wrapper
custom_ip_0_to_microblaze_0 (
.FSL_Clk ( sys_clk_s ),
.SYS_Rst ( sys_rst_s ),
.FSL_Rst ( custom_ip_0_to_microblaze_0_OPB_Rst ),
.FSL_M_Clk ( net_gnd0 ),
.FSL_M_Data ( custom_ip_0_to_microblaze_0_FSL_M_Data ),
.FSL_M_Control ( custom_ip_0_to_microblaze_0_FSL_M_Control ),
.FSL_M_Write ( custom_ip_0_to_microblaze_0_FSL_M_Write ),
.FSL_M_Full ( custom_ip_0_to_microblaze_0_FSL_M_Full ),
.FSL_S_Clk ( net_gnd0 ),
.FSL_S_Data ( custom_ip_0_to_microblaze_0_FSL_S_Data ),
.FSL_S_Control ( custom_ip_0_to_microblaze_0_FSL_S_Control ),
.FSL_S_Read ( custom_ip_0_to_microblaze_0_FSL_S_Read ),
.FSL_S_Exists ( custom_ip_0_to_microblaze_0_FSL_S_Exists ),
.FSL_Full ( ),
.FSL_Has_Data ( )
);
custom_ip_0_wrapper
custom_ip_0 (
.FSL_Clk ( sys_clk_s ),
.FSL_Rst ( custom_ip_0_to_microblaze_0_OPB_Rst ),
.FSL_S_Clk ( ),
.FSL_S_Read ( microblaze_0_to_custom_ip_0_FSL_S_Read ),
.FSL_S_Data ( microblaze_0_to_custom_ip_0_FSL_S_Data ),
.FSL_S_Control ( microblaze_0_to_custom_ip_0_FSL_S_Control ),
.FSL_S_Exists ( microblaze_0_to_custom_ip_0_FSL_S_Exists ),
.FSL_M_Clk ( ),
.FSL_M_Write ( custom_ip_0_to_microblaze_0_FSL_M_Write ),
.FSL_M_Data ( custom_ip_0_to_microblaze_0_FSL_M_Data ),
.FSL_M_Control ( custom_ip_0_to_microblaze_0_FSL_M_Control ),
.FSL_M_Full ( custom_ip_0_to_microblaze_0_FSL_M_Full )
);
microblaze_0_to_custom_ip_0_wrapper
microblaze_0_to_custom_ip_0 (
.FSL_Clk ( sys_clk_s ),
.SYS_Rst ( sys_rst_s ),
.FSL_Rst ( ),
.FSL_M_Clk ( net_gnd0 ),
.FSL_M_Data ( microblaze_0_to_custom_ip_0_FSL_M_Data ),
.FSL_M_Control ( microblaze_0_to_custom_ip_0_FSL_M_Control ),
.FSL_M_Write ( microblaze_0_to_custom_ip_0_FSL_M_Write ),
.FSL_M_Full ( microblaze_0_to_custom_ip_0_FSL_M_Full ),
.FSL_S_Clk ( net_gnd0 ),
.FSL_S_Data ( microblaze_0_to_custom_ip_0_FSL_S_Data ),
.FSL_S_Control ( microblaze_0_to_custom_ip_0_FSL_S_Control ),
.FSL_S_Read ( microblaze_0_to_custom_ip_0_FSL_S_Read ),
.FSL_S_Exists ( microblaze_0_to_custom_ip_0_FSL_S_Exists ),
.FSL_Full ( ),
.FSL_Has_Data ( )
Article: 111524
See whole thread at:
http://groups.google.ca/group/comp.arch.fpga/browse_thread/thread/322e88de0fbb80e8/65ecc09c50ed8d9b?lnk=raot&hl=en#65ecc09c50ed8d9b
I have been getting exactly the same output continually
from my project when I load it into my development board
(ML403), in spite of making changes that should cause
different output. When I did "Project -> Clean All Generated
Files" in EDK, I finally managed to get some changes to
appear.
I think the solution is to make a zipfile of the fresh project
containing the autogenerated user IP and restore that to
a fresh directory every time you want to make a change
to the user IP, rather than guessing what files need to
be cleaned (see my first post in this thread for a quote from
a help page that says you can clean the files of a "process"
but doesn't say anything else -- that was the entire content
of that help page).
I'm following the EDK_82_PPC_Tutorial.pdf for the ML403
board; see
http://www.xilinx.com/support/techsup/tutorials/edk_tutorials.htm
-- "EDK PowerPC Tutorial using the ML403 Development Kit 8.2"
and adding my core to the user IP. This worked for me in
a previous project, and I don't think it is any accident that
it suddenly started working the day I tried it in a fresh project.
It does seem to be my experience as a user with a couple of
months of experience that project files need to be cleaned in ISE,
too, so users with similar levels of experience and knowledge
of what needs to be cleared are probably safer in starting with
a fresh project every time they make a change, by making a
zipfile of the fresh project when they set it up. However, creating
a fresh project in ISE is almost trivial compared with going
through BSB ("Base System Builder") in EDK followed by
"Create User Peripheral". What could save some time in ISE is
if you had to set up a complex test bench waveform. After you
have changed that a few times and have rescaled the timing
and changed its length, it gets "tired" and produces a bit of a
mess the next time the timing is rescaled. It's a good idea to make
a zipfile copy of the whole project so you can just restore it,
unless you know more than I do and know exactly what files
to save in order to save the testbench.
I'm taking the time to write this in hopes that it will help others
in a similar situation.
The effect of this Xilinx toolset is to
magnify the "haste makes waste" principle (trying to
hurry makes it easy to make mistakes, which waste time)
by creating a situation in which a user's natural
impatience in not wanting to take the time to
continually build a new project results in wasting
massive amounts of his time*; I might have probably
been able to get my new project working about two weeks ago,
after one week of working on it, or at least I could have been
investigating some real issues, instead of continually
rebuilding a mess of left-over old builds and not
getting what I think I'm getting. I knew about
"Cleaning Project Files" in ISE to do the Build, but I
wasn't clear about always starting with a fresh EDK
project, which is the project I'm building. I don't
seem to be getting the help I need from my various
technical support personnel, because they do not ask me
questions to find out my status and therefore they
don't find out the mistakes that I'm making. This is
probably because some people get angry at them for
insulting their intelligence -- aside from them just
not having the time or the inclination to help. The
solution to the former dilemma might be for tech
support personnel to ask questions at an advanced
level and ask progressively
more basic questions until the status of the user is
found; the step size at which questions can be made
more basic can be changed adaptively according to the
user's responses.
*This may be due to ignorance of design principles
or a desire to make money by selling training courses.
What do people think the appropriate way to deal
with those two cases might be?
This reminds me of yesterday's "Dilbert" --
http://www.unitedmedia.com/comics/dilbert/archive/dilbert-20061103.html
-- in which "Ninety percent of your customers ... 'Fantasize
about beating you to death with your stupid product.'"
Cordially,
-James
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