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@firebird: Typically, the "SPI-interface" of ADCs ist nothing more than a shift register carrying out one bit per clock, so it is up to YOU which clock speed to choose. In very rare situations, you will create a unique and isolated design dealing with high speed ADCs and interfacing to the rest of the FPGA. But here, a counter and a bit-BUX should be all to be done. The counter should have a fixed relationship to your CPU master clock (one one clock domain simpler to handle) and an eye should be kept on the timing: Some ADCs respond e.g. on the falling edge of their local clock, and additional timing delays caused be drivers might will cause tricky edge constellations of data and sampling clock. To deal with this, I usually prepare a second clock in the FPGA running at the double frequency and driving the output registers (here ADC-clock driver). In a recent video design, the ADCs are fed with 100MHz clock speed (full FPGA speed) where the driving clock is passed through register FFs clocked with not200Mhz resulting in 25% additional delay and an perfect timing constellation between data signals and rising clock.Article: 111901
Hi, In the book "Digital signal processing with field programmable gate arrays" (1st edition) written by U.Meyer Baese, I don't understand one sentence. On page 45 about binary adders, it gives: s_k=x_k XOR y_k XOR c_k; c_k+1 = (x_k . y_k) + (x_k . c_k) + (y_k . c_k) In the case of a 2C adder, the LSB can be reduced to a half adder because the carry input is zero. I don't understand the last sentence. For a not 2C adder, I think the LSB can also be reduced to a half adder because the carry input is zero. Am I wrong? Where is wrong? Another question, although I did some logic in my work, I was given a question "What is the 2's complement of 011 (binary)? For my deep memory, my answer is 101 (binary). I came this from: 1. not 011 => 100; 2. increase 1 => 101. Is it correct? Thank you very much.Article: 111902
"Josep Duran" <j.duran@teleline.es> wrote in message news:1163364369.744466.26760@b28g2000cwb.googlegroups.com... > KJ wrote: >>(......) >> >> As a general guideline setup times of an external device will translate >> into >> clock to output delay requirement for the FPGA. Clock to output delays >> of >> an external device will translate into input setup time requirements for >> the >> FPGA. Both of these will translate in roughly the following manner: >> >> Tsu (requirement) = Clock Period - Tco (specification) - Clock Skew - PCB >> prop delays differences >> >> > For example >> > If I have a 50 mhz clock with a 20 ns period is there a general rule as >> > to what my pad to setup and clock to pad should be in order to keep >> > things in sync with the system clock? >> The actual clock cycle is not relevant to how you go about performing the >> task. >> >> KJ > > On a (hopefully) related issue, how do you handle the Tco jitter > between different IO pads. If there is a timing requirement between these two outputs that must be met then generally you must not allow them to change on the same edge of the same clock cycle. Two methods of doing this are: - Take an extra clock cycle, say set one of the outputs on clock cycle 1, the other signal on the next clock cycle holding the first one constant on this clock cycle. This is generally the preferred approach and would be an example of preventing the signals from changing on 'the same clock cycle' - Clock the two signals on opposite edges of the clock. On paper it seems to give you a built-in half a clock cycle skew between the two but when you account for duty cycle variation (clocks are never 50%) and the fact that sometimes you have no control over the clock (like if it comes from an external part) this method loses some of it's luster. This would be an example of not allowing them to change on 'the same edge'. Controlling address, data and the write signal between an FPGA and an async SRAM is a good example of such a case. The SRAM specs generally spec requirements of 0ns of setup time for address relative to write falling and 0 hold time of data after the rising edge of write....but 0 is not negative. Work through such a design and you'll find yourself using one of the two above approaches in order to guarantee proper behaviour. > > Lets say, the FPGA outputs clock and data to an external chip with some > Tsu requirement. > > Lets say, the Tco calculated for all outputs is in the range 10-12 ns, > to my understanding, this is a maximum time. Usually that is the case, sometimes a minimum time is also available. If not assume Tmin = 0. > Is it safe to assume that any deviation from this timing will affect > all outputs the same ? No. > Is it possible that the clock signal goes out in a 20% (or 80%) of the > calculated maximum Tco while some other output needs the full 100% of > the maximum calculated Tco ? I would tend to think it is not possible, > but I must account for some margin here (?) Timing between pins is not guaranteed behaviour, it also changes over temperature ranges and sometimes internal activity. Counting on it will lead to 'mystery' problems like, the board works (or doesn't work) when you first turn it on but then after it warms up it doesn't work (or does). You'll start pulling out heat guns and cold spray marveling at the supposed thermal problem...it's not thermal, it's a timing problem. > > Am I missing some other timing constraint ? > Not really missing but just assuming things that are not guaranteed. If you count on them in your design it will let you down in a not too friendly manner. KJArticle: 111903
> In the last version of naxjp with source available, you can find how these
> commands are used to programm the device. E.g. in naxjp-079/alg95xl.cpp
Can you post the rest of this file?
> for erasing the device you find:
>
> bool DeviceXC95XL::Erase(){
> csd->SetLength(Num,18);
> csd->SetSMASK(Num,0x3ffff);
> if(!stricmp(DeviceCmd,"oerase")){
> PrintMessage("erase");
> csi->SetTDI(Num,0xec,8,0);
> csi->OutputSIR(false);
> csd->SetTDI(Num,0xaa55 << 2 | 3,18,0);
> csd->OutputSDR(false,400000,IgnoreLevel);
> }
> PrintMessage("bulk erase");
> csi->SetTDI(Num,0xed,8,0);
> csi->OutputSIR(false);
> csd->SetTDI(Num,0x03ffff,18,0);
> csd->OutputSDR(false,400000,IgnoreLevel);
> csd->SetTDI(Num,0x00001,18,0);
> csd->SetTDO(Num,0x00001,18,0);
> csd->SetMASK(Num,0x00003,18,0);
> return csd->OutputSDR(true,0,IgnoreLevel);
>
> The comments are however in japanese, Nahitafu has no big knowledge of
> english and further versions of naxjp where no longer available in source.
I have some Japanese friends to help.
>
> Probably Nahitafu signed some NDAs.
I doubt it. Xilinx published full spec for XCR3000. Why would they
hold out on XC9500? I am just trying to make use of some old
inventories. Otherwise, I have to buy new XCR3000s.
>
> I wish the programming instruction would be available somewhere and would be
> folded in some program like xc3sprog.
I'll get it translated and post it. Thanks.
>
> Cheers
> --
> Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
>
> Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Article: 111904Hi Jonathan, Thanks a lot! Now I understand what's "vacuous success" :) Best regards, Davy Jonathan Bromley wrote: > On 10 Nov 2006 18:36:25 -0800, "Davy" <zhushenli@gmail.com> wrote: > > >Hi all, > > > >I have two problem of SystemVerilog Assertion. About property > >implication and sequence. > > > >1. Is > >//-------- > >property rule (a,b,c); > > @(posedge clk) a |-> b ##1 c; > >endproperty > >//-------- > > > >equal to > >//-------- > >sequence rule; > > @(posedge clk) (a&&b) ##1 c; > >endsequence > >//-------- > > No. See the recent thread "implication operators in sva" > on comp.lang.verilog. Also, you have parameterised the > property but not the sequence. > > >2. I was told implication can be same or next cycle. Is same cycle > >equal to "|->"? And is next cycle equal to "|=>"? > > Yes. See my post in the thread I just mentioned. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.bromley@MYCOMPANY.com > http://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated.Article: 111905
Ray Andraka wrote: > John_H wrote: > >> Ray Andraka wrote: >> >>> Xilinx comes up in a programmable known state. You can instantiate >>> the ROC primitive to make your design take advantage of it (unless >>> explicitly told otherwise, all the flip-flops come up cleared). >> >> >> Actually, any FDP, FDPE, FDS, or FDSE primitives come up set unless >> explicitly told otherwise, at least in the Spartan-N(E) families I've >> used. The FD, FDR, FDRS, FDC, FDCP, FDE, FDRE, FDRSE, FDCE, and FDCPE >> primitives all come up cleared as expected unless explicitly told >> otherwise. >> >> All BlockRAM and CLB SelectRAM (including SRLs) come up cleared by >> default but can be overridden as well. > > Yes, that is true if you instantiate the primitives. The synthesis, > however, does not force the use of those primitives necessarily. If you > want it to come up in a known state then you need to use the ROC. Synthesis doesn't force the use of the set-on-power-up primitives but it doesn't exclude their use either. Look at any synthesis-produced instance of the mentioned primitives in your designs and you should find they power up to a logic high unless you explicitly override their operation. > Borge, yes and no on the ROC. It is there mainly for the benefit of > simulation, however if you instantiate the ROC component as a black box, > synthesis leaves it in, and the Xilinx translate takes the black boxes > out, leaving you with flip-flops that are explicitly forced to a > specific starting state.Article: 111906
Hi! About the adder Question: The 2level-Combinational Adder (or Fulladder) consists of two half adders and an OR-gate. The reduction to a Half Adder for the LSB is only valid under the assumption that there is no Carry from an earlyer calculation. For a "not-2C Adder", well, whatever architecture it has if it isn't created from half adders, the LSB can't be reduced to a halfadder without destroying the "not-2C" architecture. (e.g. Carry Look Ahead Adder) About the 2's complement: It's a cognitive trick: The question was: what IS the 2's complement of 011 (binary)? The 2's complement of 011 (binary) IS 011, because it's a positive number. Remember that the 2's complement number range has a positive part too! You answered the question: can you create the 2's complement of -011(binary)? Here it's clear that we have a negative number and can construct it's 2's complement as you did. In the case of signed numbers always ask about the way of the sign representation. (Sign Bit, 2's complement or some other coding scheme) Only with that additional information you can decide what to do. Best regards Eilert fl schrieb: > Hi, > In the book "Digital signal processing with field programmable gate > arrays" (1st edition) written by U.Meyer Baese, I don't understand one > sentence. On page 45 about binary adders, it gives: > > s_k=x_k XOR y_k XOR c_k; > > c_k+1 = (x_k . y_k) + (x_k . c_k) + (y_k . c_k) > > > In the case of a 2C adder, the LSB can be reduced to a half adder > because the carry input is zero. > > I don't understand the last sentence. For a not 2C adder, I think the > LSB can also be reduced to a half adder because the carry input is > zero. Am I wrong? Where is wrong? > > > Another question, although I did some logic in my work, I was given a > question "What is the 2's complement of 011 (binary)? For my deep > memory, my answer is 101 (binary). I came this from: > 1. not 011 => 100; > 2. increase 1 => 101. > Is it correct? > > Thank you very much. >Article: 111907
Hi, I was trying to run a C program from the OCM BRAM. I have not incorporate external memory to my design yet. I managed to download the ELF file using XMD but it didn't run. When I type "stop", the message from XMD was "unable to stop processor". What could be the problem? What are the settings required in order to run program from OCM. Thanks.Article: 111908
Hi, Has anyone successfully used MPMC2 as the memory controller for DDR2 SDRAM? I used it to interface with the Micron's MT47H32M16CC-37EB DDR2 SDRAM and it doesn't work. Any important steps/settings required in order to get it working? Thanks.Article: 111909
Gentlemen, Try to be reasonable. All the devices you are mentioning don't exist today. They might be underway but still ... not available. The moment you have the features available, you are allready thinking of new nice-to-have's. IMHO this is more academic then reality. I'm still designing with 1st generation LatticeEC's and XP's, concidering ECP2 or ECP2M's but not looking further. If my customer asks me to work with Altera, then I'm proposing C2 (good availability), but again, not looking further. Both S3 and V5 are too new (this counts for ECP2M as well). When the project is ready in say 3 months, I want to have silicon. I hate to tell my customers that they need to wait for their proto for another 6 months because the core of the system is not available yet! Regards, Luc On 11 Nov 2006 09:46:13 GMT, unknown (unknown@aol.com) wrote: >Personnaly, I'm also waiting for Cyclone III. Looks promising. >By the way, I've been told that MAX III is also on the way ... and that NIOS II will be >supported :o) > > >---------------------------------------------- >Posted with NewsLeecher v3.5 Beta 5 > * http://www.newsleecher.com/?usenetArticle: 111910
lb....@telenet.be schrieb: > Gentlemen, > Try to be reasonable. All the devices you are mentioning don't exist > today. They might be underway but still ... not available. > The moment you have the features available, you are allready thinking > of new nice-to-have's. IMHO this is more academic then reality. > I'm still designing with 1st generation LatticeEC's and XP's, > concidering ECP2 or ECP2M's but not looking further. If my customer > asks me to work with Altera, then I'm proposing C2 (good > availability), but again, not looking further. > > Both S3 and V5 are too new (this counts for ECP2M as well). When the > project is ready in say 3 months, I want to have silicon. I hate to > tell my customers that they need to wait for their proto for another 6 > months because the core of the system is not available yet! > > Regards, > > Luc Virtex-5 are pretty much real and available also, for Stratix-3, ECP2M the availability is not yet there yet, thats correct. Antti PS Cyclone-3 is scheduled to be announced mid DEC2005Article: 111911
"Antti" <Antti.Lukats@xilant.com> wrote in message news:1163409834.243174.140090@m73g2000cwd.googlegroups.com... > PS Cyclone-3 is scheduled to be announced mid DEC2005 As soon as that? :-) WillArticle: 111912
lb.edc@telenet.be wrote: > Gentlemen, > Try to be reasonable. All the devices you are mentioning don't exist > today. They might be underway but still ... not available. > The moment you have the features available, you are allready thinking > of new nice-to-have's. IMHO this is more academic then reality. This _is_ a newsgroup ? Should the posts be restricted only to last years devices, and never to next years ? > I'm still designing with 1st generation LatticeEC's and XP's, > concidering ECP2 or ECP2M's but not looking further. If my customer > asks me to work with Altera, then I'm proposing C2 (good > availability), but again, not looking further. > > Both S3 and V5 are too new (this counts for ECP2M as well). When the > project is ready in say 3 months, I want to have silicon. I hate to > tell my customers that they need to wait for their proto for another 6 > months because the core of the system is not available yet! I don't recall any of the posts saying they had designs held up ? It is of general interest to see what the vendors have fixed, and who has learnt from their past mistakes, or their competitors ? As to when a device is 'ready' to use in a commercial design, that's a quite different issue :) -jgArticle: 111913
Antti wrote: > PS Cyclone-3 is scheduled to be announced mid DEC2005 and the schedule for MAX II ? -jgArticle: 111914
Thanks, Ben, for your response and your proposal with the adder tree. I will think about that but probably I will run out of DSP slices when using that approach ;-) The accumulator is only a small part of my entire design which is completely realized using DSP48 slices. And I don't want to go for a larger Virtex ;-) I will probably use a latency clock to wait for the carry to become available at the P port for the computation of the next chunk with carry input from a fabric source. Unfortunately, this reduces my the overall performance but it seems to be the only solution to me when using cascaded adders. Thanks again. Cheers, Tim Tim schrieb: > Sorry for my unclear explanation. Using your simplification with 64 > bits my goal is to do the following chain of full 64 additions (for > example 3 operations a 64 bit): > > BA [DSP #1; A:B ] > + DC [DSP #1; C] > + FE [DSP #2, A:B] <<--- takes PCIN from DSP #1 > + HG [DSP #3, A:B] <<--- takes PCIN from DSP #2 > -------- > (Z)YX [3, P] > > I assume three cascaded DSP slices to perform the computations. The > statement in square brackets remark the index of the respective DSP > slice which takes the computation on the left and its I/O port in which > the data chunk is fed. > > In the first cycle, I planned to start adding T1=A+C using DSP #1 and > pass on the result T1 to DSP #2 via PCIN. In the next cycle, DSP #2 > computes T2=T1+E and passes the result to DSP #3. At the same time, > DSP #1 can already start to compute R1=B+D (pipelining) and so on... > > The problem with this approach is that I probably can't use the carry > logic in the dedicated silicon since the DSP #1 is using C input for > the Z mux and #2 and #3 the PCIN causing the carry being generated from > a previous result. > > I guess my architecture is not optimal for the use of the DSPs but > there are some constraints on the availability of the 32bit input > chunks which become accessible after a certain period of time. Thus I > cannot freely choose where to start with my computations (chunks become > available in alphabetic order A-B-C-D-E...) > > I am appreciating any ideas which help me to avoid using a carry > generated and routed through the fabric ;-) > > Thanks again, Ben. > Cheers, Tim > > Ben Jones schrieb: > > > Hi Tim, > > > > "Tim" <gueneysu@crypto.rub.de> wrote in message > > news:1162565977.101678.102780@i42g2000cwa.googlegroups.com... > > > Ben, thanks so much! This is the kind of solution I am looking for! > > > > > > But just one litte question: I am dealing with a situation which > > > requires me to add several 256bit numbers in a row. Hence, I planned to > > > use a serial design of several interconnected DSP slices each caring > > > for a single 256 addition computing a 32 bit chunk at a time. I > > > intended to pass on the first 32bit chunk from one DSP slice to the > > > next using the PCOUT/PCIN path. > > > > I'm not sure I quite understand what you are doing. > > > > Let's simplify and look at a 64-bit addition, done in two halves. > > Representing each 32-bit chunk by a letter, you want to do: > > > > BA > > +DC > > --- > > =YX > > > > To do this in two stages, first you add A to C and get X and a carry. Then > > you add B to D with the carry and get Y (and a final carry which we'll > > ignore). So, once you've done the first step, you already have the > > least-significant 32 bits of the result (X) - and they play no further part > > in the computation. So, why do you need to use the PCOUT path for anything > > (other than the carry, if you intend to do the Y=B+D computation in the next > > DSP block up)? > > > > Maybe I've misunderstood your algorithm a bit. > > > > Cheers, > > > > -Ben-Article: 111915
Antti wrote: > PS Cyclone-3 is scheduled to be announced mid DEC2005 and the schedule for MAX III ? (oops, MAX III, of course ) -jgArticle: 111916
zyan schrieb: > Hi, > > Has anyone successfully used MPMC2 as the memory controller for DDR2 SDRAM? I used it to interface with the Micron's MT47H32M16CC-37EB DDR2 SDRAM and it doesn't work. Any important steps/settings required in order to get it working? > > Thanks. same here :( all attempts to get MPMC2 DDR2 designs to work have failed so far have tested on custom V4 board with single 16bit device and on ML501 all attempts failing I guess the only way to get going is to purchase a eval board that *IS* supported by MPMC2 like ml410 and get it working there, and then translate that working design to a custom board. AnttiArticle: 111917
hi all, i have serial data out in my design and i need to convert it to LVDS signal how can i covert it to LVDS . my end system needs differential data as input so i need to convert to LVDS. i have written code in vhdl and data out is ready which is serial data . i am using spartan 3e fpga..... can any one please explain how to change to LVDS. regards srikanthArticle: 111918
zwsdotcom@gmail.com wrote: : This used to work! I've had it put away for a couple of weeks, and now : when I plug in the Platform cable it tries to reinstall the driver and : when it gets to the second stage (after installing the firmware : loader), Windows says that a service installation section in the INF : file was invalid. : Anyone ever seen this before?! How do I fix it? I'd wait for other suggestions before trying this, but if all else fails you can roll back the configuration of XP to before it broke with the 'System Restore' feature - http://en.wikipedia.org/wiki/System_Restore This sucesfully pulled my machine back from the edge when I had some very strange USB problems... cdsArticle: 111919
KJ wrote: > (......) Thank you. You have confirmed the worse of my fears. :-) Best regards Josep DuranArticle: 111920
hi, everyone, I want to run ncvlog ncvhdl ncelab ncsim xst ngdbuild ..... under Unix. I've write a script for this, but with no control statement. How can i control the running flow, namely: if (NCVLOG ERROR) then ERROR REPORT and STOP THE RUNNING.... or if (XST ERROR) then ERROR REPORT and STOP THE RUNNING.... Thanks, ChengArticle: 111921
uvbaz wrote: > hi, everyone, > > I want to run > > ncvlog > ncvhdl > ncelab > ncsim > xst > ngdbuild > ..... > under Unix. > I've write a script for this, but with no control statement. How can i > control the running flow, namely: > > if (NCVLOG ERROR) then ERROR REPORT and STOP THE RUNNING.... > > or > > if (XST ERROR) then ERROR REPORT and STOP THE RUNNING.... http://tldp.org/LDP/abs/html/part2.html Cheers, JonArticle: 111922
<ekavirsrikanth@gmail.com> wrote in message news:1163413947.064149.16520@f16g2000cwb.googlegroups.com... > > > hi all, > > i have serial data out in my design and i need to convert it to LVDS > signal how can i covert it to LVDS . my end system needs differential > data as input so i need to convert to LVDS. i have written code in vhdl > and data out is ready which is serial data . i am using spartan 3e > fpga..... > > can any one please explain how to change to LVDS. > All voltage standards (like LVDS) are specified as user constraints. Consult the Spartan or ISE documentation for the precise details KJArticle: 111923
Hello all,
I am trying to use a two-dimensional array in the port of a vhdl
program as follows:
entity tree_adder is
port (
A : in inhibitory_weights_array;
S : out std_logic_vector(15 downto 0)
);
end tree_adder;
where inhibitory_weights_array is defined in a package as:
TYPE inhibitory_weights_array IS array(0 to 23) of std_logic_vector(15
downto 0);
Synthesis do not show any error, but when I try to check his behavioral
simulation, the following error happen:
The testbench tool fails to create the right waveform, making port A as
an array of 24 elements of bit (equivalent to std_logic_vector(23
downto 0).
I have tried several options for example I changed the entity to:
entity tree_adder is
port (
A0 : in std_logic_vector(15 downto 0);
A1 : in std_logic_vector(15 downto 0);
. . .
.
. . .
.
. . .
.
A23 : in std_logic_vector(15 downto 0);
S : out std_logic_vector(15 downto 0)
);
end tree_adder;
and then defining a signal (after architecture)
signal B : inhibitory_weights_array;
begin
B(0) <= A0;
and so on.
Again it didn't work.
I am using ISE 8.1 and both ISE Simulator and Modelsim SE 5.8.
Any help will be greatly appreciated.
Regards,
Ruben
Article: 111924Thanks, Jon The problem is, i dont know how to get the value e.g. ncvlog returns. Regard, Cheng Jon Beniston schrieb: > uvbaz wrote: > > hi, everyone, > > > > I want to run > > > > ncvlog > > ncvhdl > > ncelab > > ncsim > > xst > > ngdbuild > > ..... > > under Unix. > > I've write a script for this, but with no control statement. How can i > > control the running flow, namely: > > > > if (NCVLOG ERROR) then ERROR REPORT and STOP THE RUNNING.... > > > > or > > > > if (XST ERROR) then ERROR REPORT and STOP THE RUNNING.... > > > http://tldp.org/LDP/abs/html/part2.html > > Cheers, > Jon
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