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hallo, i have 2 FPGAs(both Xilinx Virtex-4) on one Board, and only one Cable(Platform Cable USB). How can i configuration them under iMPact? Somebody help me!!! :) ChengArticle: 111201
Hi Cathy, Read about how pcores works (PSF format) in the documentation and add these modules as pcores. Start with copying an existing pcore which have a similar interface. You can then connect them in .mhs file using XPS. Göran "cathy" <hy34@njit.edu> wrote in message news:1162230620.538892.268840@e64g2000cwd.googlegroups.com... > Hi, all: > > I want to incorporate moduleA and moduleB to XPS and connected them > with microblaze. ModuleA and ModuleB have connection with microblaze > through FSL and OPB separately, and also, moduleA and Moduleb have > connection between themselves. My question is: how to describe the > connection between moduleA/B in XPS. > Thanks a lot, > Cathy >Article: 111202
uvbaz wrote: > hallo, > > i have 2 FPGAs(both Xilinx Virtex-4) on one Board, and only one > Cable(Platform Cable USB). How can i configuration them under iMPact? > > Somebody help me!!! :) > > Cheng > Using JTAG chain or using other configuration mode? With two Xilinx FPGAs in the same JTAG chain, the Xilinx Impact software will auto-detect your both devices. Then Impact will ask to associated the .bit file for each devices ... Regards, Laurent Gauch ____________________________ http://www.amontec.com Introducing new JTAGkey TinyArticle: 111203
Hi there, I am working on a high-speed (500 MHz, Virtex 4, speedgrade -12) and multi-precision adder (unsigned) capable to compute 256 bit additions using the DSP48 slices. I am using a sequential adder design, thus passing a chunk with the lowest bits to a DSP adder slice fist (each chunk is only 32 bit for internal reasons), continuing up to the highest bits of the input computing a 32 bit result each clock. When implementing the carry logic between the chunks, I just came across with its funny realization in the DSP slice. You can either use the fabric to determine the carry yourself (1) or use the inverted MSB from the output P[47]/PCIN[47] (2). Using the fabric (1) for carry implementation requires the additional CARRY_IN register to preserve the maximum clocking speed of 500MHz making it necessary to wait for the carry until the computation of the next chunk can start. Option (2) seems not to be applicable to my problem due to the inverted carry signal which is useless for my scenario. Does anybody have a good solution to this? Thanks already in advance! Cheers, TimArticle: 111204
Ray Andraka wrote: > daver2 wrote: > > Kevin Neilson wrote: > > > >>daver2 wrote: > >> > >>>I am implementing an extremely old logic design (circa 1965!) on a > >>>Xilinx Virtex 4 (XC4VLX25). > >>> > >>>For those interested - it is the logic for the computer that flew to > >>>the moon and back! The design is based on approximately 5,000 3-input > >>>NOR gates and not a flip flop in sight! For the circuit diagrams see > >>>website 'http://klabs.org/history/ech/agc_schematics/index.htm'. > >>> > >> > >>Does the design implement flops using NORs with feedback? If so, that > >>could be an issue. The ISE tools don't like combinational feedback. > >>-KEvin > > > > > > Kevin, > > > > Yes, the design does use NOR gates with feedback to create the > > flipflops - and yes I am getting warnings from XST about combinatorial > > loops. I am (as we speak) going through the network that the > > synthesiser has generated for the 4LUT's to see that what it has > > generated is what should have been generated! > > > > The original logic would have potentially suffered from unstable > > oscillation and glitches if it had not been designed properly in the > > first place so it is my belief that ISE is complaining about something > > that won't occur in reality. > > > > Dave > > > > > Unfortunately, the original design depends on redundant cover terms and > circuit delays to guarantee that proper operation. FPGAs are not > intended for what amounts to asynchronous logic. Unlike the original > design, the delays in the interconnect between the gates in the FPGA are > significant and need to be considered when doing the design. Unless you > intend to had route this, you can't guarantee the delays are properly > balanced to avoid the hazards the original design avoids. Also, the > FPGA tools generally do not leave the cover terms necessary to avoid > glitch hazards in an async design without you explicitly forcing the > tools to keep the terms. You would be more likely to achieve success by > converting the flip-flops in the original design to FPGA flip-flops, > something that kind of goes against your intent I suppose. > > The ISE complaints are quite valid, and unless you take the pains to > make sure the design is not reduced by the tools and that the routing > delays are properly balanced and considered, you will likely not wind up > with a working design. > > In order to get the tools to keep from optimizing out stuff you need in > there for hazard covers, you will at least need to put syn_keeps or the > equivalent on each node in the original design, and may have to go as > far as explicitly instantiating xilinx primitives with the proper init > strings for each gate. Instantiation might in the long run be the > easier way to go, as it gives you a bit more control when it comes to > placement. > > Good luck. Thanks Ray, You are confirming what I feared. I decided to implement a small part of the project to see what problems I would fall into before converting everything and then sorting out the resulting mess! Whilst the ModelSim solution works this is no real indication that it will in reality! I will have a bit more of a think in the meantime... Thanks for your time and help. DaveArticle: 111205
Andy wrote: > The original design was verified for the timing and behavior > (specifically glitch-free behavior) of hard NOR gates within the gate > array fabric that it was implemented on. > > Change the NORs to luts, and change the timing (radically), and you no > longer have a reliable design, no matter how reliable the original was. > > Combinatorial feedback loops in FPGAs are bad medicine. > > If the original design had macros for every flop built out of NORs, you > could replace those macros with rtl code for conventional flops, and > then ISE would be happy, and so would you/your design. Otherwise your > going to have to be able to recognize the pattern of feedback in NOR > networks that makes a flop, then cut that out and replace it with a > conventional flop. > > Andy > > > daver2 wrote: > > Kevin Neilson wrote: > > > daver2 wrote: > > > > I am implementing an extremely old logic design (circa 1965!) on a > > > > Xilinx Virtex 4 (XC4VLX25). > > > > > > > > For those interested - it is the logic for the computer that flew to > > > > the moon and back! The design is based on approximately 5,000 3-input > > > > NOR gates and not a flip flop in sight! For the circuit diagrams see > > > > website 'http://klabs.org/history/ech/agc_schematics/index.htm'. > > > > > > > > > > Does the design implement flops using NORs with feedback? If so, that > > > could be an issue. The ISE tools don't like combinational feedback. > > > -KEvin > > > > Kevin, > > > > Yes, the design does use NOR gates with feedback to create the > > flipflops - and yes I am getting warnings from XST about combinatorial > > loops. I am (as we speak) going through the network that the > > synthesiser has generated for the 4LUT's to see that what it has > > generated is what should have been generated! > > > > The original logic would have potentially suffered from unstable > > oscillation and glitches if it had not been designed properly in the > > first place so it is my belief that ISE is complaining about something > > that won't occur in reality. > > > > Dave Andy, Thanks for the tip. Of course, you are correct. My theory was to try a small bit of the logic to find out what the problems were initially and then to decide if they were solvable. I have learned a lot about the original logic by studying the ModelSim runs and I think this excercise is useful - however you may be correct in getting a workable solution in silicon. I shall have a little more thinking and experimentation time before I give up though and then I shall explore some other avenues. Thanks for your time in reading my post and replying. DaveArticle: 111206
Jim Granville wrote: > c.j.w@telia.com wrote: > > Hi, > > > > Where can I find a specification on how stable the internal clock of > > Xilinx's CPLDs (in this case the XC9572-7) is? For example tolerance, > > and drift of the frequency for ambient temperature. I can't find it in > > the product specs, and also not on Xilinx's website (to my surprise). > > The only thing the data sheet says is that f_SYSTEM has a min-value of > > 83.3. I also can't find anything about how to connect this system clock > > to a signal in my VHDL code. > > > > I will use the CPLD to generate a PWM signal for control of a servo, > > and therefore the exact length of the pulses, in absolute time, is > > critical. If the internal clock is not considered reliable enough I > > would have to use an external chyrstal oscillator circuit. I could > > probably at least tolerate an error of a couple of percent of the > > frequency. > > I think I can see a miss-match here :) > The f_system is the maximum value the Chip is guaranteed to clock > (external Clock) at (usually with some given test pattern, to make it a > usefull number ) > > It is NOT a spec value for some internal clock oscillator!!. > > So, yes, you will have to provide an external Osc, with Sq wave drive. > > -jg OK, thanks - actually I was considering whether there really was an internal clock - I asked a lab assistant, who told me there was. I figured it had to be the f_SYSTEM - but it's not :-). I'll use an external oscillator circuit. Thanks everyone for helping me out. Regards CarlArticle: 111207
Thanks, Laurent Is JTAG Chain = Boundary Scan Chain? Yes, it is "Automatically connected to a cable and identity Boundary Scan Chain". Unfortunately, impact detect only one FPGA. Which mistakes cause this happen: PINs are not correctly connected? impact is not properly adjusted? or something else? thanks again Regards, Cheng AMONTEC schrieb: > uvbaz wrote: > > hallo, > > > > i have 2 FPGAs(both Xilinx Virtex-4) on one Board, and only one > > Cable(Platform Cable USB). How can i configuration them under iMPact? > > > > Somebody help me!!! :) > > > > Cheng > > > > Using JTAG chain or using other configuration mode? > > With two Xilinx FPGAs in the same JTAG chain, the Xilinx Impact software > will auto-detect your both devices. Then Impact will ask to associated > the .bit file for each devices ... > > Regards, > Laurent Gauch > ____________________________ > http://www.amontec.com > Introducing new JTAGkey TinyArticle: 111208
Hi Cheng, JTAG = Boundary Scan = large shift-register (TDI TDO signals) + state machine TAP control (TMS signal) JTAG is a synchronous bus (TCK signal), as a SPI bus. If Xilinx Impact only detect one device, this means you only have one device in the JTAG chain. You maybe have jumpers (or 0 ohm resistors) on your board for routing the JTAG chain. Regards, Laurent Gauch ____________________________ http://www.amontec.com Introducing new JTAGkey Tiny uvbaz wrote: > Thanks, Laurent > > Is JTAG Chain = Boundary Scan Chain? Yes, it is "Automatically > connected to a cable and identity Boundary Scan Chain". > > Unfortunately, impact detect only one FPGA. Which mistakes cause this > happen: PINs are not correctly connected? impact is not properly > adjusted? or something else? > > thanks again > > Regards, > Cheng > > > AMONTEC schrieb: > > >>uvbaz wrote: >> >>>hallo, >>> >>>i have 2 FPGAs(both Xilinx Virtex-4) on one Board, and only one >>>Cable(Platform Cable USB). How can i configuration them under iMPact? >>> >>>Somebody help me!!! :) >>> >>>Cheng >>> >> >>Using JTAG chain or using other configuration mode? >> >>With two Xilinx FPGAs in the same JTAG chain, the Xilinx Impact software >>will auto-detect your both devices. Then Impact will ask to associated >>the .bit file for each devices ... >> >>Regards, >>Laurent Gauch >> ____________________________ >> http://www.amontec.com >> Introducing new JTAGkey Tiny > >Article: 111209
Kryten wrote: > "daver2" <davidroberts@siemens.com> wrote in message > news:1162220709.470867.305120@e64g2000cwd.googlegroups.com... > >I am implementing an extremely old logic design (circa 1965!) on a > > Xilinx Virtex 4 (XC4VLX25). > > > > For those interested - it is the logic for the computer that flew to > > the moon and back! The design is based on approximately 5,000 3-input > > NOR gates and not a flip flop in sight! > > Aw dang, I was going to do that. > Well, it was on my 'to do' list for when I have time. > But I'm working 12 hour days and hope to do so for quite a while, so I don't > have much time left for hobby stuff. > > I did get round to having a look at it though > (see http://www.howell1964.freeserve.co.uk/logic/apollo_clone.htm) > and I recall thinking that it might not be a good idea to directly translate > the circuit into loads of NOR gates. I was going to try writing a higher > level VHDL description to do a functional equivalent that was better suited > to current FPGA technology. > > Good luck with the project - I look forward to fitting it into my own FPGA > chip. Hi Kryten, Thanks for the reply. I found your website previously and have it bookmarked as a reference! Well, there is nothing stopping two (or more) people from implementing the AGC in VHDL!!! I also have an outline design for the AGC in a more higher-level VHDL structure. My initial thoughts were that a gate-level implementation should be less prone to my misinterpretation of the AGC functionality, as the english description of the functionality of the logic doesn't exist any longer (or at least I haven't a copy). Whilst the various software simulations and John Pultorak's excellent Block I construction gives some major insights into the operation of the instruction set etc. etc. they would appear to be limited in more esoteric areas like RUPTs etc. I have implemented the DSKY in 'proper' VHDL and this seems to work beautifully. I still have some issues with regard to the actual interface to the AGC though that I plan to resolve when I start to look at the AGC I/O sub-system. I have just taken delivery of my extremely pretty, large, green, 7-segment LED displays - so the next few weeks will be taken up constructing a DSKY rather than bashing VHDL... I shall 'pause for thought' and this point and try out some of the synthesised logic on a real FPGA and see what happens. If this doesn't work, I may have to resort to a functional emulation - but using the gate-level version with ModelSim plus the existing software emulators to give some degree of verification. Thanks for your time in replying. DaveArticle: 111210
Todd wrote: > Hi all > > I'm a design engineer trying to evaluate the large number of > possibilities for adding Ethernet to our embedded system. > > So far I've been very impressed by the Altera Cyclone II with NIOS II > and free lightweight TCP/IP stack. Adding Ethernet appears to amount > to the Cyclone II and a MAC+PHY chip like LAN91C111 (or equivalent). > > Anyone have experience with using the Cyclone II merely for Ethernet? > Should I try to put the MAC inside the FPGA and just use an external > PHY? > > Any recommendations for a communication protocol between the FPGA and > my DSP? SPI seems the most obvious choice for reasonably high > bandwidth (>6 Mbps). Right now my DSP runs from a 1.5 Mbps UART so > mimicking this data flow would save me a bunch of assembly code > changes. However, I'd like to send more data back to the host so could > use upwards of 6 Mbps. > > Also, I'm interested in general recommendations for System on a > Programmable Chip (SOPC), which Altera is obviously highly interested > in advancing. It seems very attractive since I could eventually get > rid of the DSP by simply creating a second NIOS II processor within the > FPGA and porting my assembly code to C. The upgrade path is > straightforward and indefinite since Altera will keep coming up with > even better FPGAs. Any caveats or warnings? Lastly, are there major > reasons I should be considering Xilinx instead? > > Thanks in advance for the help! > -Todd > > Hi Todd, I've designed Ethernet MACs for a couple of clients, they're reasonably straightforward. The CRC is possibly the most complicated bit but there is VHDL code out there on the internet for that if you go looking. I've also used the SMSC LAN91C111, it's a nice chip but I found it slightly awkward to use the buffer manager. If you design the MAC into your Fpga and use a PHY chip then you can design your own buffer manager, which I would recommend, as it gives you flexibility and more easily achieved higher performance should you need it. AlanArticle: 111211
"maxascent" <maxascent@yahoo.co.uk> wrote in message news:SJ6dnWa9V6M9ftjY4p2dnA@giganews.com... > > Hi I am trying to infer a Xilinx dual port block ram with different > address and data widths. I want to infer it in my code and then get > Synplify to recognise it. I can do this if the address and data are the > same but dont know how if they are different. I'm completely missing out on what possible use it would be to have different address widths.....memory needs to be addressed, if you give it a partial address just what do you think should come out? Simple example would be a 3 bit address on one port and a 2 bit address on the other. On the one port you can go from 000 to 111 the other from 00 to 11....so what do you want coming out of the memory when the two bit address is set to 00? The data that is located at memory 000? Or the data from 100? I think if you'll ponder on this for a bit you'll realize that different address widths make no logical sense at all. In any case, what you need to do is size your dual port memory to a single address and data size. Next put a wrapper around it that 1. Instantiates the dual port memory 2. Adds whatever logic you require to define the mapping between the different data bus sizes. KJArticle: 111212
Why should we do your homework? Your professor most probably gave you this case to study the best architecture to implement the FFT and IFFT algorithm. So in your case (with Quartus) you can go for Stratix, Cyclone or Max2. Up to you to decide which is best. I assume however how FFT algorithms are working. If not, try google. In the assumption that it's not a homework, then you better by a FFT IP core that targets your chosen FPGA and EDA tools. Regards, Luc On 30 Oct 2006 16:56:03 -0800, "Jaksa" <Jaksa1984@gmail.com> wrote: > >John_H wrote: >> Which tools and which FPGAs does your school use? >> >> >> "Jaksa" <Jaksa1984@gmail.com> wrote in message >> news:1162255557.907076.68510@m73g2000cwd.googlegroups.com... >> > Hi. >> > I have to write FPGA sintezible VHDL code for FFT and IFFT (for 128 >> > points (can be generic too)). Can Anybody help me, please. Any kind of >> > help would help me. Thanks people >> > >I am using Altera Quartus II software. Why?Article: 111213
"Peter Alfke" <alfke@sbcglobal.net> wrote in message news:1162255891.335808.86090@m7g2000cwm.googlegroups.com... >I agree, and I was not making a moral statement. > Just that the ranks of engineers that can debug low-level (fundamental) > problems are shrinking. But you haven't established that this is a 'problem'. Shrinking to fit the number of slots that the world needs is economically sound. Shrinking below that will cause a shortage which will cause the price of people who have those skills to go up. > Soon only IC designers will understand these things (because they are > still their livelihood), since everybody else has "moved up". But maybe they will be the only ones who use this on a day to day basis and have an actual need to know this. Can you say that you understand the operation of flip flops and can demonstrate this using the equations of quantum mechanical level or can you even compute the fields that will be produced by that changing flip flop by using Maxwell's equations? Maybe you can, but I'll hazard to say that if forced to do this in front of someone who is skilled in either or both of these theories then probably not. > ( I have > a son who works in software R&D, and we have very limited common ground > in electronic things). But maybe he is very skilled in other areas....keep in mind Adam Smith and the division of labor in economic theory. > I was, however, bemoaning the fact that so many things in our lives > have become black mystery boxes that defy "healthy curiosity". And that > phenomenon is new, within the last 50 years, a short time in the > evolution of technology. My point on the earlier post was that it has gone on for much longer. The true fundamentals of electronics haven't changed in roughly a century (Maxwell and quantum) and yet I would hazard to say that the number of engineers designing electrical or electronic equipment that directly use these theories is pretty close to 0....and would speculate that that is also roughly the number of engineers who directly used it 10, 20, 30, etc...... years ago as well. I don't think many things defy the healthy curiousity but as designers get more and more productive there becomes more and more knowledge that one must accumulate if you want to satisfy that curiousity completely not because the fundamentals are changing but because the approximations and shortcuts that are used above those fundamentals in order to realize those productivity improvements get more and more each year. One can still do it, one can still specialize in any of those areas if you choose to but and there will still generally be a market for people who have accumulated more of that specialized skill....if it is still relevant to the world at large. KJArticle: 111214
Hi guys Nice touch Bob, I laughed my @ss off!!! But you are right; young boys like Jagsa donnot have attitude do they? At least, they can disclose the name of their institute, this would prove useful :) Anyway, Jaksa-boy do your homework please. If you don't feel confident to the least, then this is a free world. You can always change profession, you are just starting... You might even learn a craft... But, hey boy, your institute is paying a sh!tpile of money so that you can have Quartus-II and not get your feet wet with open stuff like GHDL and Signs. Give them a break and sit your @ss down. It's just a trivial design in VHDL, it's not rocket science really. In one or two weeks of mediocre labour, you will be done. That said, you could browse some nice projects here and there in the web (well-known site: http://www.opencores.org) but that's not the point, is it? BTW what's your institute, i might have to ring a few bells there ^o^ ^O^ (+ laughing his @ss off for the entire day). Cheers Jacko Jaksa wrote: > I am using Altera Quartus II software. Why?Article: 111215
"Peter Alfke" <alfke@sbcglobal.net> wrote in message news:1162269349.885081.72560@k70g2000cwa.googlegroups.com... > Good for you, Arien. > Over the past 35 years I have interviewed many hundreds of new college > grads. Among others I always asked a very simple question: > Show me how you analyze the max clock frequency of a 2-bit shift > register (what data-sheet parameters do you need, where do they apply, > and what is the math between them?). > Most can do that, after some > prodding. Then: What happens to the max frequency when there is clock > skew between the two flip-flops. About half gave the wrong answer to > this slightly tricky question. So they did not get hired...In a new > grad I do not look for factual knowledge, but for the ability to think > clearly. Kind of missed how you factored in the stress associated with the interview process. It's easy to sit on the side of the questioner in that situation, not so easy the other way around. Sometimes the weak answers have nothing to do with the skills of that person but reflects how that person tenses up in stressful situations. If they do, then maybe they're not appropriate for a client facing position, but maybe you're not interviewing someone for that type of position either. > Some passed this test with flying colors, sometimes amazed at the > implication of their own answer. Being able to think quickly on your feet is a skill that can help land that job offer. It can also come in handy when on the job...but along with other skills too. > I was looking for nuts-and-bolts applications engineers, and other > interviewers tested their systems and software skills. What about them 'people skills'? The arrogant ones who know the nuts and bolts and flew through your test might be rather disruptive in the work place. Generally they become sidelined because of their arrogance...or work their way up the management chain to become CEO. > We were (and are) pretty selective... This made me ponder why most of the posts about problems with tools are centered around brand X. 'Most' here meaning that the percentage of brand X questions/complaints appears to be far above brand X's market share. It could just be my perception of the posts though. KJArticle: 111216
KJ wrote: > "maxascent" <maxascent@yahoo.co.uk> wrote in message > news:SJ6dnWa9V6M9ftjY4p2dnA@giganews.com... >> Hi I am trying to infer a Xilinx dual port block ram with different >> address and data widths. I want to infer it in my code and then get >> Synplify to recognise it. I can do this if the address and data are the >> same but dont know how if they are different. > > I'm completely missing out on what possible use it would be to have > different address widths.....memory needs to be addressed, if you give it a As well as different address widths the ports have different data widths and depths as viewed from each port. The same number of bits are accessible from both ports. It can be useful in avoiding mux's but I tend to find requires direct instantiation of the appropriate block ram component: RAMB16_Sm_Sn. Cheers, Andy.Article: 111217
> I don't know much about PPC's, but here's some > thoughts on DCM problems: We checked a lot of docs and learned a lot about DCMs ... but it turned out that the PPC was and is working fine! The problem was with the timing of our the flash chip and some rounding in the wait routine. This caused setup/hold to be around the limit of "somehow working" and sometimes failing at 300 MHz :-/ again - thanks for the good ressource list ... bye, MichaelArticle: 111218
Hi Todd,
"Todd" <tschoepflin@gmail.com> wrote in message
news:1162255661.055244.134860@e64g2000cwd.googlegroups.com...
> Hi all
>
> I'm a design engineer trying to evaluate the large number of
> possibilities for adding Ethernet to our embedded system.
>
> Anyone have experience with using the Cyclone II merely for Ethernet?
> Should I try to put the MAC inside the FPGA and just use an external
> PHY?
I worked on a project doing Ethernet using Nios and a LAN91C111 a few years
ago. The performance was quite disappointing (I forget which stack we were
using but it wasn't "paid for"). Then again, that was a few years ago; this
is now - and your requirements may vary. What exactly are you doing on the
TCP/IP side? What wire speed are you targeting?
> The upgrade path is straightforward and indefinite since Altera will
> keep coming up with even better FPGAs. Any caveats or warnings?
Yes, I'd say never assume that *any* company (and to be fair that includes
the one I work for!) will continue to produce better and better products
indefinitely. Most people prefer to hedge their bets and make their design
as vendor-independent as possible, in case of nasty surprises.
> Lastly, are there major
> reasons I should be considering Xilinx instead?
Well, of course! :-) You could get yourself a Virtex-4 FX12 part with an
integrated 400MHz PowerPC 405 processor and two hard-macro 10/100/1000
Ethernet MAC blocks, all in a decent-sized FPGA with 32 XtremeDSP slices to
implement your DSP algorithms.
<removes salesman hat, because it doesn't really fit...>
-Ben-
Article: 111219Taking into account what has been said already, have you considered implementing the design with a software emulator? You said it runs fine in ModelSim, and any vanilla embedded CPU should be able to do so in realtime.Article: 111220
Hi, I have a bootloader running from internal ram (m4k blocks). I also build a standalone application to run from external ram. The application is a .bin file which is sent to the bootloader through a serial interface (RS232). The bootloader copies the application to external ram and executes it. My application is built to run from address 0x00200000. If I make a .bin file from the generated .elf file I get a file of about 2 MB. This is because the alt_exception and alt_irq_handler is laid at address 0x20 and 0xEC. AFAIK this is not necessary. Do I have to make a linker file to fix this? Or should I use another startup assembly file? In case of a linker file, does anyone have an example for this situation? So the bootloader runs from internal ram (with base address 0) and the application runs from external ram (with base address 0x00200000). TIA, FrankArticle: 111221
"KJ" <kkjennings@sbcglobal.net> wrote in message
news:POF1h.1806$wX.413@newssvr12.news.prodigy.com...
>
> I'm completely missing out on what possible use it would be to have
> different address widths.....memory needs to be addressed, if you give it
> a partial address just what do you think should come out? Simple example
> would be a 3 bit address on one port and a 2 bit address on the other. On
> the one port you can go from 000 to 111 the other from 00 to 11....so what
> do you want coming out of the memory when the two bit address is set to
> 00? The data that is located at memory 000? Or the data from 100?
Both, surely?
Imagine a 64-bit RAM with two ports. One port has 6 bits of address and 1
bit of data; the other has 1 bit of address and 32 bits of data. On address
port A, you put a value 0-63 and you get the single corresponding bit of the
contents. On address port B, you put a value 0-1 and you get either bits
0-31 or bits 32-63 of the contents. Generalize to whatever widths you want.
I'm not sure why none of the synthesis tools support this, but it's true,
they don't. I've always ended up instantiating something to get this
behaviour. :-(
Cheers,
-Ben-
Article: 111222jetm...@hotmail.com wrote: > Taking into account what has been said already, have you considered > implementing the design with a software emulator? You said it runs > fine in ModelSim, and any vanilla embedded CPU should be able to do so > in realtime. There are a couple of software emulators already out there in the 'wild' (one of the best being at http://www.ibiblio.org/apollo/. This software emulation is used by the orbiter flight simulator (see http://orbit.medphys.ucl.ac.uk/orbit.html and screenshot at http://mysite.wanadoo-members.co.uk/marui/orbiter_agc.jpg) for the navigation computer. During the implementation of the orbiter (and other) projects, things are found out not to be working as expected, and this is usually traced down to a simplification or misunderstanding of the way the computer actually works. I actually tried to do exactly what you propose with some of the microcontrollers available (I think I had a play with a large AVR in the past). One of the problems was that the fixed 'core rope' memory is 36,864 words in size (73728 bytes) and this usually breaks the embedded C compilers which have a limit of 64KB (or at least the free ones that I have downloaded). OK, I could split the fixed code up into chunks and knit it together etc. etc. but this is hassle. I work with software every day and an opportunity to get back and do a bit of hardware/VHDL for a change is too tempting! I am attempting to develop as 'true-to-life as possible' simulation of the AGC whilst, at the same time, being able to run at a significantly faster-than-real-time to enable orbiter missions to be undertaken in hours rather than days. One other possibility would be to construct my own run-time system so that I could enter the NOR-gate logic as it appears in the AGC schematics, compile it and emulate it within a framework. This would give me the realism I desired but may not achieve the speed improvement for the orbiter project. The emulation approach would also introduce a 'serialisation' of the logic rather than the true parallelism of a native hardware design. If I arrange for the emulation framework to be implemented within a FPGA I could achieve my goal of realism but I suspect the speed would still probably suffer - perhaps not as much as a purely software/embedded processor solution though? Oh well, if things were as simple as sending men to the moon everyone would be doing it... Sorry to ramble on a bit in this post but I have been thinking about the excellent replies I am receiving and the ideas that are buzzing around my head need to be captured somewhere! Thanks to everyone for your time in replying to my question. DaveArticle: 111223
KJ wrote: Please ignore my previous post in the section after.... > > We were (and are) pretty selective... and accept my apologies for the inference. KJArticle: 111224
For some reason when reading the original post I was reading that what was needed was independent control of both address and data over the multiple ports implying a certain number of memory bits accessible from port A and another (different) number from port B. >From the two responses it would appear that all we're talking about is two independent data bus sizes. Address size of the various ports is a calculated value determined from the data bus size and memory size. Ben Jones wrote: > I'm not sure why none of the synthesis tools support this, but it's true, > they don't. I've always ended up instantiating something to get this > behaviour. :-( > Not sure what support you think you're not getting. Memory can be inferred from plain vanilla VHDL with synthesis tools. Data bus sizing (and the implied address bus sizing) is a wrapper around that basic memory structure and gets synthesized just fine...so it is supported. If what you mean by 'not supported' is that there isn't a pre-defined instance that you can plop down into your code and parameterize, then you're going into the Mr. Wizard territory which leads you to vendor specific implementations. Avoiding the vendor specific stuff is usually a better approach in most cases. To have vendor independent useful modules like this, these modules should be standardized. This is exactly the type of thing that LPM attempted to do. LPM languishes as a standard though because it didn't get updated to include new and useful modules. Presumably this is because the FPGA vendors would rather go the Mr. Wizard path and try to lock designers in to their parts for irrational reasons rather than enhance standards like LPM so that designers can remain vendor neutral at design time and let the parts selection be based on rational reasons like cost, function and performance. KJ
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