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rickman schrieb: > Here are a couple more data points. I changed the part to an > xc4vlx25-12 and it exceeded the 100 MHz timing requirement, in fact it > ran at 110 MHz. But at -10 it failed only reaching 84 MHz. On the > other hand the XC3S400-5 weighed in at almost 91 MHz. So speed grade > can make a moderate difference. > > The thing that surprised me the most is that in the Spartan 3 parts the > routing was about half the delay in the worst case paths. But in the > V4 part routing was over 70% of the delay in the worst case paths! So > the LUTs got faster between S3 and V4, but not the routing! In fact, > the routing delays were longer in absolute terms, but I'm not sure this > was a valid comparison as the longest delays were on different nets > between the two parts. > > I also found a bug in the IDE. When you change parts to evaluate > differences, the Summary Report does not change the Target Device. All > the other info seems to be correct, but the target stayed the same no > matter what I did. you are correct - the main difference between S3 and V4 is the LUT delay in the matter of fact the LUT delay is really really small in V4, when I made measurements to check this delay I wasnt to belive at first but then looked at datasheet timings and it was all correlating. I got signals up to 975MHz within slowest V4, while in S3 I think I did not get to around 370Mz only. so the routing really matters! AnttiArticle: 109301
Hello, I'm building a project with Xilinx ISE 8.2.02i. During "Implement Design" the process stalls for about 5 minutes after "Generating PAD report". CPU/Memory usage during this time is about 10-20%. Any hints? Regards, Norbert StuhrmannArticle: 109302
thanks for the tipp. just trying that out now. but i would still like to try the sample code from edk out. so perhaps somebody could generate that for me. that would really help me a lot. thanksArticle: 109303
In my opinion, Alteaa's StratixII GX is better. VII Pro is too old and low performance and FX has too many bugges. Lattice's product has good difinition. But Lattice's FPGAs are not used widly, and Lattice's experience on FPGA is too poor and their software is also very poor. So I think Altera SIIGX is better. <lb.edc@telenet.be> ??????:7dp9h21kovb7jv066iud878pvt9vro4bj8@4ax.com... > Matthew, > > I suggest you have a look at Lattice a forget a while of the Xilinx > solution. Lattice can offer a very nice PCIe solution in their ECP2M > (low cost solution for x1 and x4), and in their LatticeSC (high end up > to x8). > The IP core is smaller than Xilinx', and on top more robust. > > Best regards, > > Luc > > On Fri, 22 Sep 2006 23:24:42 -0500, "Matthew Hicks" > <mdhicks2@uiuc.edu> wrote: > >>I am building a data input board that will have 1000/100/10 Base Ethernet, >>USB 2.0, IEE 1394, SATA, and a high speed expansion connector for future >>use. I am using harware chips to take care of the physical and link >>layers >>of the respective protocols. Each of these chips speaks PCI-E on the back >>side. I will also have a raw MGT connection using a custom protocol that >>is >>connected to a larger network of computers that also speak this protocol. >>I >>want to connect all of the hardware chips to a Virtex II Pro that has 8 >>MGT >>ports. I noticed the similarity between PCI-E requirements/operation and >>those for the MGTs. It appears that Xilinx has a core for this, but when >>I >>try to use the core corgen says that it's only available for Virtex 4s. >>Any >>suggestions or problems that I should be on the look-out for. >> >> >>---Matthew Hicks >>Article: 109304
John: Lattice has a CPLD evaluation board available for the MachXO device. It is a low cost board, and one of their most popular evaluation board. The kit includes the MachXO256 in TQFP100 packaging, power supply and parallel download cable. All of the device I/O are avaible for use, plus there is a small (too small) prototype area. The I/O levels to each I/O bank in the device are selectable (via SMT resistor), sleep mode is available on the DIP switch, there are 8 LEDs and the board includes mounting footprints for expansion headers. It's priced at a reasonable $99.00. You might want to check it out: http://www.latticesemi.com/products/developmenthardware/cpldboards/machxostarterevaluationbo.cfm John Adair wrote: > Problem with CPLDs is that not many people want development boards > other than possibly students. Generally I think people think of these > devices as "simple" so go straight to their own board rather than > trying a ready made platform. > > Speaking as a development board manufacturer the other problem with > making boards like these is that profit line would be very low. > Generally people have an expectation that CPLDs are cheap and the drive > is not there in most cases to justify development. > > That all said we already do a CPLD module that can be used as a crude > development module but not in the lower power devices you are > interested in. We are looking at making this into a proper board with a > power jack and regulator to allow easy stand alone powering from a > brick in the wall. No timescales yet on this but we are talking a > number of academic institutions to find out interest level. > > John Adair > Enterpoint Ltd. > > rickman wrote: > > I want to do some testing on some of the low power CPLDs and I can't > > find a decent test board for the Lattice ispMACH4000 parts or the XPLA3 > > parts. The XPLA3 parts are hard to find on a good eval board because > > they are a bit long in the tooth and even though they are a good choice > > when you want to use a single supply (or need 5 volt tolerance) support > > for them is starting to wane. The only good eval board for the XPLA3 > > parts that I can find is from India. > > > > The MACH4000 parts are a whole different matter. Lattice has an eval > > board that uses the LC4032ZC or the LC4064ZC chip, but nothing larger. > > It also has terrible documentation. Further I believe I am hearing > > that they never intended it to be an eval board, but rather a marketing > > tool to compare their part to an X brand part. So it was pushed into > > eval service with little documentation and support. With no third > > party eval board that I can find and the Lattice board with a $500 > > price tag and no useful documentation, it looks like I will have to go > > with the XC2C128 part just by default! > > > > Anyone know of eval boards for the ispMACH4000 parts?Article: 109305
In comp.arch.embedded rickman <gnuarm@gmail.com> wrote:
> Perhaps a bit off topic, but I use Google to access these newsgroups
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Well, as some people used to jest at the height of the "intel inside"
logo campaign: how's that for a problem neatly encircled.
As well as Google knows how to do a web search engine, as bad is their
grasp of Usenet. They're arguably the biggest threat to Usenet's
continuing existence since "the September that never ended".
--
Hans-Bernhard Broeker (broeker@physik.rwth-aachen.de)
Even if all the snow were burnt, ashes would remain.
Article: 109306CBFalconer wrote: > Dennis wrote: >> CBFalconer wrote: >>> Dennis wrote: >>>> Go to www.ibm.com and click on IBM Certified Used Equipment in the >>>> Shop for column. I picked up a T30 with serial and parallel ports >>>> that I am very happy with for about $500. It looked like new. >>> I took a look there and none of the models seem to include a >>> floppy. Also, none describe the presence or absence of serial and >>> parallel ports. I have heard horror stories about the parallel >>> port compatibility in IBMs, which I need for my laser printer. Any >>> comments? >>> >> Interesting, it looks like they shortened the descriptions since I was >> there last. They also no longer list things like the monitor connector >> and PC card slots either. All the T30 series have a serial and parallel >> port. I think they dropped the serial port on the T40 series. It appears >> that most of the information has been moved over to the lenovo site now. >> A bit of a pain to find the model from the IBM site and then have to go >> over to the lenovo site to see what all is included on a particular >> model. On the bright side it looks like the hardware maintenance and >> service manuals are still available for download on the lenovo site. >> >> I have only used the parallel port to run an LCD display which worked fine. >> >> The Thinkpads dropped the internal floppy option a while back. I have an >> external USB floppy which is probably not worth the price any more. > > How reliable is the USB floppy, and what sort of price is > involved? Do they come with a proper Windows installation CD, or > is it a system restore nonsense. Does your parallel port usage > mean bit banging? Is the USB 1 or 2? > I don't use the USB floppy very much (I actually borrow it from work) but haven't had any problems with it. (I mostly use USB flash drives._ It is plug and play under Windows XP and shows up as a removable drive (duh!). It is the IBM version which was in the $100 range. I have seen other ones in the $30 range, which is more reasonable. I haven't tried booting from the USB floppy but there are BIOS options that imply it can be done. The parallel port use was all bit banging. Put out data for the LCD, pulse the E line, etc. I actually did it under Linux using a Knoppix CD (and a USB flash drive for my code) so as not to disturb the hard drive with Windows XP. I seem to remember I had to do some BIOS configuration on the parallel port so that is was where my Linux code expected to find it. I think the USB is 1.1 - it doesn't support the 480Mb speed. It works with several different USB flash drives, my digital camera and the TI EZ430-F2013 development kit.Article: 109307
Antti wrote: > Antti > http://www.microfpga.com > FPGA programming without HDL > Antti, I clicked on your link above, and it's just a bit of text, no links, nothing. I'm using a recent mozilla browser. Is that all that's supposed to happen when you visit the site? -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 109308
As long as the PCIe core is compliant, it's not a matter of better or worse. The range of products that Lattice can offer is broader than Altera's, so I assume that OP will find something that fits his needs. Regards, Luc On Sat, 23 Sep 2006 22:33:04 +0800, "PLD Hacker" <pldhacker@tom.com> wrote: >In my opinion, Alteaa's StratixII GX is better. VII Pro is too old and low >performance and FX has too many bugges. Lattice's product has good >difinition. But Lattice's FPGAs are not used widly, and Lattice's experience >on FPGA is too poor and their software is also very poor. So I think Altera >SIIGX is better. ><lb.edc@telenet.be> ??????:7dp9h21kovb7jv066iud878pvt9vro4bj8@4ax.com... >> Matthew, >> >> I suggest you have a look at Lattice a forget a while of the Xilinx >> solution. Lattice can offer a very nice PCIe solution in their ECP2M >> (low cost solution for x1 and x4), and in their LatticeSC (high end up >> to x8). >> The IP core is smaller than Xilinx', and on top more robust. >> >> Best regards, >> >> Luc >> >> On Fri, 22 Sep 2006 23:24:42 -0500, "Matthew Hicks" >> <mdhicks2@uiuc.edu> wrote: >> >>>I am building a data input board that will have 1000/100/10 Base Ethernet, >>>USB 2.0, IEE 1394, SATA, and a high speed expansion connector for future >>>use. I am using harware chips to take care of the physical and link >>>layers >>>of the respective protocols. Each of these chips speaks PCI-E on the back >>>side. I will also have a raw MGT connection using a custom protocol that >>>is >>>connected to a larger network of computers that also speak this protocol. >>>I >>>want to connect all of the hardware chips to a Virtex II Pro that has 8 >>>MGT >>>ports. I noticed the similarity between PCI-E requirements/operation and >>>those for the MGTs. It appears that Xilinx has a core for this, but when >>>I >>>try to use the core corgen says that it's only available for Virtex 4s. >>>Any >>>suggestions or problems that I should be on the look-out for. >>> >>> >>>---Matthew Hicks >>> >Article: 109309
For lab use, a Via epia M10000 is really good. You need to put it in a box with whatever storage media you want, but otherwise it is a very complete computer with parallel printer port, serial ports, USB ports, ethernet, i2c, audio, display controller etc. I use one in a very basic box with nothing but a hard disc. It happily runs linux and I rsh to it from another computer to save having lots of monitors about. Bit-banging the printer port works fine, as does the i2c interface (although I only get 16kbit/s throughput using the linux drivers). Its quiet and really cheap too! JohnArticle: 109310
avionion@gmail.com schrieb: > Here is ttranslation : > " in the last weeks a small RISC processor sketched. A few data: - > described completely in VHDL - Harvard architecture - 16-bit data > capacity (other one at something expenditure naturally possible) - > 16-bit of instructions - optimizes for Spartan 3 (a few > Instanziierungen) - internal command Rome (max. 2^16 of instructions = > 128 KB) - internal and external RAM, per max. 64 KB - separate I/O - > Multipliers signed/unsigned - Dividierer unsigned pipelined (17 clocks > with 16 bits data capacity) - interrupt input - Parity checks for > internal RAM and ROM (goes if necessary on external interrupt > CONTROLLERs) - altogether not pipelined (fetch, decode and execute > with nearly all instructions in a clock) - Clock frequency with > Spartan 3, class of data signaling rates 4:50 - 60 MHz - approx. 200 > Slices without periphery, at least 3 BRAM and 1 multiplier. For it I > would have to offer an assembler (programs in C) and a simple > debugger/simulator (programs in Java). If here serious interest > exists, I would make myself the trouble, few pages a Doku would > arrange. If not, I can save those; -). Of course everything free of > charge for non-commercial purposes and without each warranty. For a > first impression I attached times the command set. " > ziggy wrote: > > In article <1158485668.999811.326430@e3g2000cwe.googlegroups.com>, > > "Antti" <Antti.Lukats@xilant.com> wrote: > > > > > Hi, > > > > > > the original announcement is at the bottom of the thread there > > > > > > http://www.mikrocontroller.net/forum/read-9-411815.html#new > > > > > > or the direct download link > > > > > > http://www.mikrocontroller.net/attachment.php/418674/Ssfp16_1.0.zip > > > > > > all the documentation is in german only at the moment, > > > but it should be still useable - the download archive includes > > > > > > vhdl files > > > example toplevel and ucd for Digilent S3 starterkit > > > assembler (with C sources) > > > simulator (in java) > > > script to use data2mem for rom initialization > > > documentation > > > > > > there is no ISE project, so new project must be made, then just add all > > > vhdl files. on my test build the UCF caused errors on timing > > > constraints and bram loc constrains, after removing them the build was > > > succesful. > > > > > > for succesful data2mem script merging the UCF-BMM must match or the > > > data2mem will not be able to init the bitstream correctly so that may > > > have to be fixed manually, otherwise is the project ready to go for S3 > > > starterkit. > > > > > > and size - just for testing I synthesized for S3-50: > > > used slices 43% > > > not bad for an 16 bit processor. > > > > > > Antti > > > > Any ETA on translations for us over here in the us that never learned > > another language? be aware with posting google translations - the author of the SSFP16 posted on the german newsgroup in an tone "well you dont have to worry I am not going to make you legal trouble", and then talked about FDL copyright violation. To my best knowledge such accusations are meaningless, but.. well this is what you get when you try to help :) I asked my wife to edit the google-moogle translation, but as we have 2 small kids she really hasnt found the time todo it yet, and I havent pushed it either. The legalese stuff in the SSFP16 docs looked at weird to me when I first read it, near to paranoia, but now I see what it means :( AnttiArticle: 109311
Peter Alfke a écrit : > I think it's time for you to describe the "badness". > The thread gets a bit long in the tooth. :-( > Peter Alfke > =========== I designed a PCI board with 3 XC4010E on it (PCI with AMCC part, not in FPGA). The first FPGA is configured asynchronous peripheral. The other FPGA are daisy chained and configured slave peripheral (cf. Data book p. 4-74). During ten years, I had had no problem with that design. Since the beginning of this year, as XC4010 is a discontinued part, I buy it more and more often from brokers. I got three deliveries of "bad" parts. Using those "bad" parts, configuration pins M0, M1, M2, if left floating, do not all polarize high as they should, because of internal pull-ups. Then, the parts do not enter the configuration mode implied by my design. If I set external pull-ups, configuration pins polarize correctly and configuration process seems to be successful, but the behaviour of the part is wrong, ie my board does not work. I did not investigate much at this time, but the pins seem to remain floating and the parts do not start working. Though, these "bad" parts are not counterfeits, as would be empty cases, because configuration process progresses correctly : DONE raises on time, with no external pull-ups, parts may enter master serial with address pins toggling. The only difference is that "good" parts had mainly been delivered in sticks and "bad" parts had always been delivered in tapes. Further, "bad" parts were recent, but seemed older (oxyded pins). I'd like to know whether someone else experienced same problem. Jacques GENINArticle: 109312
I still remember what we used to suggest 10 years ago: Look at the Dout pin. There, the serial bitstream is passed on to the next device, but only after the device otself has received its configuration. So you should see the preamble' length count etc, and then a continuous High level, until the end of the internal configuration. And then the remainder of the concatenated bitstream is passed on to the next device. You have one advantage: You have a working board. So poke around on CCLK and Dout-Din-Dout and observe the traffic, and compare the boards. You claim that these should be identical devices (although Xilinx made several different sub-families, they are clearly marked) There is still the possibility that you bought grey-market or bogus parts. Do you know the source? Bon chance (isn't that what they say?) Peter Alfke, from home. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Jacques GENIN wrote: > Peter Alfke a =E9crit : > > I think it's time for you to describe the "badness". > > The thread gets a bit long in the tooth. :-( > > Peter Alfke > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > I designed a PCI board with 3 XC4010E on it > (PCI with AMCC part, not in FPGA). > The first FPGA is configured asynchronous peripheral. > The other FPGA are daisy chained and configured slave > peripheral (cf. Data book p. 4-74). > During ten years, I had had no problem with that design. > Since the beginning of this year, as XC4010 is a > discontinued part, I buy it more and more often from brokers. > I got three deliveries of "bad" parts. > Using those "bad" parts, configuration pins M0, M1, M2, if > left floating, do not all polarize high as they should, > because of internal pull-ups. Then, the parts do not enter > the configuration mode implied by my design. > If I set external pull-ups, configuration pins polarize > correctly and configuration process seems to be successful, > but the behaviour of the part is wrong, ie my board does not > work. I did not investigate much at this time, but the pins > seem to remain floating and the parts do not start working. > Though, these "bad" parts are not counterfeits, as would be > empty cases, because configuration process progresses > correctly : DONE raises on time, with no external pull-ups, > parts may enter master serial with address pins toggling. > > The only difference is that "good" parts had mainly been > delivered in sticks and "bad" parts had always been delivered > in tapes. > > Further, "bad" parts were recent, but seemed older > (oxyded pins). > > I'd like to know whether someone else experienced same > problem. >=20 > Jacques GENINArticle: 109313
Peter Alfke a écrit : > I still remember what we used to suggest 10 years ago: > > Look at the Dout pin. There, the serial bitstream is passed on to the > next device, but only after the device otself has received its > configuration. > So you should see the preamble' length count etc, and then a continuous > High level, until the end of the internal configuration. And then the > remainder of the concatenated bitstream is passed on to the next > device. > > You have one advantage: You have a working board. So poke around on > CCLK and Dout-Din-Dout and observe the traffic, and compare the boards. Too late, now. I'll do that tomorrow... > You claim that these should be identical devices (although Xilinx made > several different sub-families, they are clearly marked) > There is still the possibility that you bought grey-market or bogus > parts. That's the most likely... Do you know the source? The brokers won't tell... I'd better buy elsewhere... > > BonNE chance (isn't that what they say?) > Peter Alfke, from home. > ============= Thanks Jacques GENINArticle: 109314
Hi Scott - I am assuming that this is a version of modelsim XE that is supplied. If so in the command window type : view struct Then type : view sig The structure window has a top down view of design. By selecting the desired level in structure, all regs/wires for that level are displayed in the signal window. Select wires/regs and drag drop to waveform window. (You can display this via "view wave" in command window). -- Regards, John Retta Owner and Designer Retta Technical Consulting Inc. Colorado Based Xilinx Consultant email : jretta@rtc-inc.com web : www.rtc-inc.com "scott moore" <nospam@nowhere.com> wrote in message news:OMqdnWQobY9qnonYnZ2dnUVZ_rOdnZ2d@comcast.com... > Hi, > > I could use a bit of help with Webpack/ISE 8.2 from Xilinx. I am > learning Verilog by constructing a small project in it, in fact > an 8080 CPU core. > > I have completed the project, and am debugging it, but I can't seem > to get the ISE 8.2 simulator to display signal traces down inside the > module instantiations. After searches on this group's old messages, > I gather that in older versions, 7.x and back, this was simply a > matter of right clicking the signal in the signal names list and > choosing the "add to wave" option. However, this does not appear > to exist for 8.2, or was changed. I guess it is possible that the > free webpack does not have that capability, but the Xilinx website > seems to claim that the free version of the simulator "modelsim" > is not limited in an way but speed. > > Right now, the only way I appear to have to get signals out to > the waveform pane is by routing them out to pins on my testbench, > a tedious procedure at best. > > Thanks in advance, > > Scott MooreArticle: 109315
ziggy wrote: > In article <1158822468.138975.247720@h48g2000cwc.googlegroups.com>, > "Antti" <Antti.Lukats@xilant.com> wrote: > > > ziggy schrieb: > > > > > In article <1158770147.385889.73830@m73g2000cwd.googlegroups.com>, > > > "Antti" <Antti.Lukats@xilant.com> wrote: > > [snip] > > > If so, people like me will need to stick to other 'free' cores. > > > > Hi ziggy, > > > > all people like you can stick to any cores of your liking when doing > > HDL or FPGA designs as the MicroFpga can *NOT* be used with > > any kind of HDL flow at all. No synthesis, no place and route! > > > > Just take an FPGA and GCC compiler. > > No FPGA vendor tools involved in the process flow: > > 1) write your C program > > 2) compile with GCC > > 3a) merge ELF or bin into BIT or > > 3b) download over JTAG or serial > > > > 4) your C programs runs > > > > in any supported FPGA > > on any board or hardware it is in. > > > > Antti > > Ah, i think i understand now.. its running c-code directly on the > hardware.. I don't think it is that simple. At least I don't think this is the equivalent of Handel C which can compile your C code to a bit file to load into the FPGA just like an HDL bit file. That would require a lot of knowledge about the internals of the FGPA and would be different for every single one! I expect they are doing something where they load a fixed set of gateware into the FPGA which is perhaps like a reconfigurable processor rather than a fixed instruction set. But I am speculating. I just don't believe they have obtained all the info to generate bit files for FPGAs. That is sort of the "Holy Grail" of open source FPGA development software. Instead they use JBITs on Xilinx and something equivalent on Altera devices. I believe each of these programs have some limitations for this sort of thing and licensing may be the major issue for open source people.Article: 109316
Problem is that one of our partners on the project is Xilinx, so I think we may be locked-in to a Xilinx based solution if it involves an FPGA. It will also save a good deal of money for us to use a Xilinx part. But, I did look at the Altera part and they seem to have a better high-speed serial solution and by default a more fleshed-out PCI Express IP core. ---Matthew Hicks "PLD Hacker" <pldhacker@tom.com> wrote in message news:ef3i22$ppf$1@news.cn99.com... > In my opinion, Alteaa's StratixII GX is better. VII Pro is too old and low > performance and FX has too many bugges. Lattice's product has good > difinition. But Lattice's FPGAs are not used widly, and Lattice's > experience on FPGA is too poor and their software is also very poor. So I > think Altera SIIGX is better. > <lb.edc@telenet.be> ??????:7dp9h21kovb7jv066iud878pvt9vro4bj8@4ax.com... >> Matthew, >> >> I suggest you have a look at Lattice a forget a while of the Xilinx >> solution. Lattice can offer a very nice PCIe solution in their ECP2M >> (low cost solution for x1 and x4), and in their LatticeSC (high end up >> to x8). >> The IP core is smaller than Xilinx', and on top more robust. >> >> Best regards, >> >> Luc >> >> On Fri, 22 Sep 2006 23:24:42 -0500, "Matthew Hicks" >> <mdhicks2@uiuc.edu> wrote: >> >>>I am building a data input board that will have 1000/100/10 Base >>>Ethernet, >>>USB 2.0, IEE 1394, SATA, and a high speed expansion connector for future >>>use. I am using harware chips to take care of the physical and link >>>layers >>>of the respective protocols. Each of these chips speaks PCI-E on the >>>back >>>side. I will also have a raw MGT connection using a custom protocol that >>>is >>>connected to a larger network of computers that also speak this protocol. >>>I >>>want to connect all of the hardware chips to a Virtex II Pro that has 8 >>>MGT >>>ports. I noticed the similarity between PCI-E requirements/operation and >>>those for the MGTs. It appears that Xilinx has a core for this, but when >>>I >>>try to use the core corgen says that it's only available for Virtex 4s. >>>Any >>>suggestions or problems that I should be on the look-out for. >>> >>> >>>---Matthew Hicks >>> > >Article: 109317
French has only two genders, and I got them mixed up. No wonder that people mix up the three genders in German. It's usually the last mistake before perfection. You say "die Tisch" (from tabula) and you are "a foreigner"... Peter =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Jacques GENIN wrote: > Peter Alfke a =E9crit : > > I still remember what we used to suggest 10 years ago: > > > > Look at the Dout pin. There, the serial bitstream is passed on to the > > next device, but only after the device otself has received its > > configuration. > > So you should see the preamble' length count etc, and then a continuous > > High level, until the end of the internal configuration. And then the > > remainder of the concatenated bitstream is passed on to the next > > device. > > > > You have one advantage: You have a working board. So poke around on > > CCLK and Dout-Din-Dout and observe the traffic, and compare the boards. > Too late, now. I'll do that tomorrow... > > You claim that these should be identical devices (although Xilinx made > > several different sub-families, they are clearly marked) > > There is still the possibility that you bought grey-market or bogus > > parts. > That's the most likely... > Do you know the source? > The brokers won't tell... I'd better buy elsewhere... > > > > BonNE chance (isn't that what they say?) > > Peter Alfke, from home. > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > Thanks > Jacques GENINArticle: 109318
Kashmir wrote: > John: > > Lattice has a CPLD evaluation board available for the MachXO device. > It is a low cost board, and one of their most popular evaluation board. > The kit includes the MachXO256 in TQFP100 packaging, power supply and > parallel download cable. All of the device I/O are avaible for use, > plus there is a small (too small) prototype area. The I/O levels to > each I/O bank in the device are selectable (via SMT resistor), sleep > mode is available on the DIP switch, there are 8 LEDs and the board > includes mounting footprints for expansion headers. It's priced at a > reasonable $99.00. You might want to check it out: Thanks for the info, but I have already looked at the XO and it breaks 10 mA before you even start clocking it. I can't put it in sleep mode because it has to run all the time. This is a very odd design. It has two sections, one is multiplexing a pair of SPI ports and four discrete signals over three pins using a clock, sync and data IO. The clock is about 10 times faster than the SPI rate, so the distortion introduced should not be excessive. This section must run at all times. The other section receives one SPI port input to control 8 latching relays. I can add an RC circuit to control the timing of the relay pulse, otherwise the only clock is the SPI clock which will be very infrequent. I estimate that the total power for these two circuit can be kept to just a couple of mA. The input power is from a wide range battery input and efficiency is a concern. So I am thinking of using the CPLD itself to control a switched capacitor voltage divider which will cut the voltage in half or in third to make the circuit more efficient over the battery input range. So burning another 10 mA just to start the CPLD is not a good idea. The Coolrunner is really a good choice for this circuit with its low power and 5 volt tolerance. I wanted to evaluate the Lattice MACH4000 parts since they claim really low power. But if they don't even have a *real* eval board, I don't know what to say!Article: 109319
CBFalconer wrote:
...
> How reliable is the USB floppy, and what sort of price is
> involved? Do they come with a proper Windows installation CD, or
> is it a system restore nonsense. Does your parallel port usage
> mean bit banging? Is the USB 1 or 2?
Somebody gave my son a USB floppy she was going to throw out because it
didn't work. By son took it because he thought I might like to see why.
He was told that it was only supposed to work with an IMAC. I plugged it
into my XP machine and it worked fine: no drivers needed. I asked my
daughter to try it on her IMAC, and it worked for her too. That was a
year ago and she won't give it back. I think the original cost was about
$40.
Jerry
--
"The rights of the best of men are secured only as the
rights of the vilest and most abhorrent are protected."
- Chief Justice Charles Evans Hughes, 1927
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Article: 109320I am trying to look at a failed timing path in the floorplanner and I expected to be able to click on a link in the timing report and be taken to a selected net, logic or the entire path depending on the link. Instead it reports some errors about not being able to open a socket and crashes with the following error message... FATAL_ERROR:GuiUtilities:WinApp.c:710:$Revision - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. ... The timing analyzer terminates. Anyone know what this is about?Article: 109321
In article <1159043087.677421.228270@b28g2000cwb.googlegroups.com>, "Peter Alfke" <alfke@sbcglobal.net> writes: >There is still the possibility that you bought grey-market or bogus >parts. Do you know the source? Are grey market parts a serious problem these days? What does "grey" actually mean? I remember in the old TTL days when it was easy to get parts that were out of spec. I'd assume Xilinx would have pretty good control over the factories where their chips are packaged/tested. Too much trouble with leaks and the factory looses the contract. But maybe I don't know how things actually work in places where labor is cheap. I'd expect to find real chips getting recycled when startups go out of business. Some of them may not have been handled correctly so I wouldn't be surprised by problems if I got chips from a non-official source. But they have to be somewhat careful or their reputation for junk will get out. Is there a mechanism to make a whole batch of chips go bad without visible damage? I'm assuming idiot or short cuts rather than malicious. The sort of thing that would happen in a startup about to go under. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 109322
John Retta wrote: > Hi Scott - > I am assuming that this is a version of modelsim XE that is > supplied. > If so in the command window type : view struct > Then type : view sig > The structure window has a top down view of design. > By selecting the desired level in structure, all regs/wires > for that level are displayed in the signal window. Select > wires/regs and drag drop to waveform window. (You > can display this via "view wave" in command window). > Not actually sure what simulator I am using. The choice when I created the project calls it "ISE simulator". I was doing several things wrong, or laboring under a few misconceptions. I found that you can drag and drop signals from the "hierarchy" window to the waveform window. My principle problem was that I didn't know that if you highlighted the testbench in the sources window, it simulates without stimulus, and found out you have to have the .tbw (testbench waveform) file highlighted. Now the commands you were giving, I presume that these need to be given to the "sim console", which appears to be running TCL. In short, it does not appear to know the "view" command, but it has "show" and many other commands, so this may again point out that I am not running "modelsim" as I thought, sorry. Anyways, I am off and running today, and in fact got a lot of work done getting my project running. I'll learn more about these direct commands, some of them look quite useful, like the "show load" to show nets driven by a signal. Thanks again. Scott MooreArticle: 109323
Hal Murray wrote: >... > Is there a mechanism to make a whole batch of chips go bad > without visible damage? I'm assuming idiot or short cuts > rather than malicious. The sort of thing that would happen > in a startup about to go under. I thought I read Peter mention something about humidity -- if the humidity isn't kept right during storage, something bad can happen to the pads, so when the part is soldered down to a PCB something won't be right...or something. -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 109324
Yes, I wonder when one FPGA is working and the other is configured at the same time when they are working for the same module. Camwood David Ashley wrote: > Ray Andraka wrote: > > Partial reconfiguration itself is not new, but the tools' ability to > > handle it is. The design flow for partial reconfiguration is not for > > the faint of heart. Unless you have a reason to be swapping partial > > bitstreams in and out in many different combinations, you are generally > > better off using full bitstreams. > > What about just using 2 FPGA's? > > -Dave > > -- > David Ashley http://www.xdr.com/dash > Embedded linux, device drivers, system architecture
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