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"Antti" <Antti.Lukats@xilant.com> wrote in message news:1159524271.564035.322150@h48g2000cwc.googlegroups.com... > > Zara schrieb: > >> On 29 Sep 2006 01:45:03 -0700, "Mack" <disentis@gmx.li> wrote: >> >> >Hi all, >> > >> >I'm working on a Virtex-4 FX Design with a custom logic fabric and a >> >PowerPC Core containing a dual port BRAM block. The CPU with software >> >application and BRAM block was created with XPS, then the XPS submodule >> >is imported in my ISE Design as system_stub.vhd. The Top-Level is a >> >Schematic, there i added the other user-specific vhdl-moduls as symbols >> >and of course the system_stub symbol. >> >With a simple C Application i get access to the bram and can read and >> >write data to an from. >> >The next step is to get access to the second port of this bram via my >> >vhdl logic. How can i do this? >> >How can i connect in XPS System Assembly the second BRAM port to >> >external ports? Is it possible to get in ISE TopLevel a system_stub >> >schematic with the additonal ports of BRAM like Adresses, Data, RST, >> >Clk, WEN? >> >Is there another usual way to solve my problems? >> > >> >Every response would be appreciated. >> >Mack >> >> *Probably*, if you intantiate only an lmb_if_ram_controller, connected >> to (for instance) port A of a bram, then all you have to do is in >> "ports" view of System Assembly, click on "connectio-Filters", check >> "All". The, under your BRAM you will have access to all port B. Assign >> signal names to all signals, and them make them external. >> There you are. >> >> Zara > > hi thanks! > > sometime easy things in EDK are not so easy, I never tried the > port filter thing !!! > > Antti > You can also do this directly in the .mhs file. Just look at the .mpd file for the bram block and you will find the port names for the second port. Now just add them to the .mhs for the bram block, add your external ports and connect them to the bram signals This is what the port filter thing allows you to do but in the GUI instead. GöranArticle: 109576
Brian Drummond schrieb: > On 27 Sep 2006 08:31:02 -0700, "zeeman_be" <zeemanbe@gmail.com> wrote: > > >Hi all, > > > >I am implementing a microblaze processor in a subdesign in a Virtex4 > >component (ISE v7.1 sp3, EDK v7.1 sp2). > >The microblaze is using the internal BRAMS as instuction and data > >memory. > > > >The program is increasing and becomes more than 64kByte. > > >It would be a solution to split the textblock in two parts. I have > >found the instructions for writing a LinkerScript for doing that. The > >only problem I have is to find the place where the object files of my > >code are temporary stored. > > XAPP642 and Answer Record 16547 show how to locate individual functions > into segments other than "text". In fact it's even slightly simpler than > shown there. You only need to use the "Generate Linker Script" dialog to > generate a new segment (say, "text2") and locate it in your second 64K > block. > > Then use the attributes as shown to place any individual functions in > text2 instead of text. No need to write linker scripts or find object > files. > > (I've only used it with the PPC gcc under EDK 7.1 but see no reason why > mb should be any different in this respect) > > - Brian hum I just looked the project with large BRAMs and it seems that EDK 8.2 SP1 has a bug there -namly only the first BLOCK get PLACED attribute in the BMM file! surprisingly data2mem doesnt complain when data is sent to it that belongs to the block with no PLACED in BMM seems really be a nasty BUG :( AnttiArticle: 109577
Hi Folks When creating fast MUXes, I use AND/OR logic (sum of products, SOP) with the CYINIT and MUXCY to implement a 9-input OR within a V2Pro slice. The Problem is, that the output of the MUXCY is not configured by MAP63 to drive the input of the FF within the same slice. As far as I can see, MAP could use the X/Y output of the slice and reenter the slice using the DX/DY input to use the local FF. But the way it is implemented is the the MUXCY output exits the slice, uses routing (some times up to 1.3 ns) and uses a totally different FF. --> How can I force MAP6.3 to drive the local FF by the MUXCY output. Thanks in advance! Stefan Try this to reproduce: use the following code with a register afterwards module logic_or9x1 (I, O); // 1 Bit Wide, 9-Input OR Gate input [0:8] I; output O; wire or_term1, or_term2, or_term3, cout; assign #1 or_term1 = ~(I[0] | I[1] | I[2] | I[3]); assign #1 or_term2 = ~(I[4] | I[5] | I[6] | I[7]); assign #1 or_term3 = I[8]; MUXCY muxcy0 (.DI(1'b1), .CI(or_term3), .S(or_term1), .O(cout)); MUXCY muxcy1 (.DI(1'b1), .CI(cout), .S(or_term2), .O(O)); endmodule -- Stefan Philipp Universität Heidelberg Electronic Vision(s) Kirchhoff-Institut für Physik Im Neuenheimer Feld 227 69120 Heidelberg Tel.: ++49-6221-54-9897 Fax: ++49-6221-54-9839 -- Das gesamte Universum expandiert, aber trotzdem finden wir keinen Parkplatz!Article: 109578
Thomas Reinemann wrote: Sorry, but I made to a victim of quantization noise. My sampled sinusoid input signal wasn't really a sinusoid.Article: 109579
Zara schrieb: > On 29 Sep 2006 01:45:03 -0700, "Mack" <disentis@gmx.li> wrote: > > >Hi all, > > > >I'm working on a Virtex-4 FX Design with a custom logic fabric and a > >PowerPC Core containing a dual port BRAM block. The CPU with software > >application and BRAM block was created with XPS, then the XPS submodule > >is imported in my ISE Design as system_stub.vhd. The Top-Level is a > >Schematic, there i added the other user-specific vhdl-moduls as symbols > >and of course the system_stub symbol. > >With a simple C Application i get access to the bram and can read and > >write data to an from. > >The next step is to get access to the second port of this bram via my > >vhdl logic. How can i do this? > >How can i connect in XPS System Assembly the second BRAM port to > >external ports? Is it possible to get in ISE TopLevel a system_stub > >schematic with the additonal ports of BRAM like Adresses, Data, RST, > >Clk, WEN? > >Is there another usual way to solve my problems? > > > >Every response would be appreciated. > >Mack > > *Probably*, if you intantiate only an lmb_if_ram_controller, connected > to (for instance) port A of a bram, then all you have to do is in > "ports" view of System Assembly, click on "connectio-Filters", check > "All". The, under your BRAM you will have access to all port B. Assign > signal names to all signals, and them make them external. > There you are. > > Zara Zara, thanks a lot. That's exactly what I'm looking for... MackArticle: 109580
On 29 Sep 2006 00:04:51 -0700, james7uw@yahoo.ca wrote: >Hi all, > >I [...] get the following transcript after ModelSim comes up, >in the ModelSim transcript (output) window: ># vsim -lib work -sdfmax /UUT=.sdf -t 1ps user_logic_tbw ># ** Error: (vsim-SDF-3196) Failed to find SDF file ".sdf". ># Error loading design ># Error: Error loading design ># Pausing macro execution ># MACRO ./user_logic_tbw.tdo PAUSED at line 7 >VSIM(paused)> >Why can't it find the .sdf file? This should just work because >everything should be set up automatically. It looks like you are asking it to load a file CALLED ".sdf" - and not surprisingly it can't find one. The file is probably called "mydesign.sdf" and that should be the value given to the /UUT= argument. If you can't persuade the tools to generate the correct filename, you can always enter the correct command line in Modelsim's console yourself. - Brian > >I have the .sdf file in my project directory, called ppcaesh\, in >\ppcaesh\netgen\par\ . The full path I'm using is >C:\XilinxMe\ISE\AES01OC\ppcaesh\netgen\par\ . In that directory, I have >two files, user_logic_timesim.sdf and user_logic_timesim.nlf . This is >where ISE put them. > >>From the manual (the ModelSim User Manual, from http://www.model.com), >-sdfmax /UUT=.sdf is telling ModelSim to use the sdf file, but why >can't it find it in the place that ISE put it? I don't really know that >/UUT=.sdf syntax. One would think that a filename before the .sdf >should be getting put in there automatically. Also I realize that "UUT" >stands for "Unit Under Test", but how is that significant to ModelSim? > >What would I set in ISE or in ModelSim, to patch this problem? > >I have searched the web to try to find answers on this, but can't find >anything understandable, only snatches. I have downloaded the ModelSim >manuals and tried to figure out what is going on from them, but this >seems to be some conglomeration of ISE syntax using ModelSim and I >couldn't find an explanation of that /UUT=.sdf syntax so that I could >figure out what to patch. Can anyone tell me? > >Thanks in advance, >-JamesArticle: 109581
Hi, I have hit a bottleneck while using FIFO interface mode of FTDI FT2232L USB demo board, which i plugged into my linux box (2.4.20-8smp). I made sure that the ftdi_sio and usbserial modules are removed. To verify that the onboard EEPROM is actually configured to 245BM FIFO interface, I used Mprog (in windows). Next, I have installed the latest libftdi and libusb packages and tried to explore the handshaking signals in FIFO mode. So, first I have set the async bit bang mode (value 1) using ftdi_set_bitmode API and I could successfully read and write from FT2232L using ftdi_read_data and ftdi_write_data APIs. But then in bit bang mode, I do not have access to FIFO handshaking signals (TXE and RXF) as they are masked to RD and WR signals (as per the FT2232L manual). But without setting the bitbang mode, the write operation fails and so the read operations as well. Please let me know how can i use the FIFO mode correctly and what am I missing here. Apart from these, how can i sense the AC[0:3] and BC[0:3] signals on FT2232L through API. Will ftdi_read_pins help ? Also, how shall I interpret the data returned by ftdi_read_pins API. I am kind of new to this. So, I would appreciate if you can elaborate your understanding. Thank you very much for you help. Regards,Article: 109582
Why does it often ask if I want to recover a schematic file from previous work when i open a schematic file?Article: 109583
Try using the LO output of the MUXCY_D primitive instead of the O output.Article: 109584
I know this might sound strange, but try to change the properties of your design files to 'synthesis/implementation only'. With 'synthesis/implementation + simulation' I get the same error, but everything works fine with the above mentioned setting.Article: 109585
Hi! James,
go to simulation toolbar, and click on start simulation, go to the sdf
toolbar and add your sdf file that way and run the simulation.
Berry
james7uw@yahoo.ca wrote:
> Hi all,
>
> I am using ModelSim III XE 6.1e starter edition with ISE 8.2.03i and I
> am trying to do post-par simulation having built everything
> successfully. I have the checkmark in the green circle for "Generate
> Post-Place & Route Simulation Model". In the Sources Window I select
> "Post-Route Simulation" and get the ModelSim Simulator in the Processes
> Window, with "Simulate Post-Place & Route Model" under it. I double-
> click on that and get the following transcript after ModelSim comes up,
> in the ModelSim transcript (output) window:
>
> # Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl
> # do {user_logic_tbw.tdo}
> # ** Warning: (vlib-34) Library already exists at "work".
> # Model Technology ModelSim XE III vcom 6.1e Compiler 2006.03 Mar 8
> 2006
> # -- Loading package standard
> # -- Loading package std_logic_1164
> # -- Loading package std_logic_arith
> # -- Loading package std_logic_unsigned
> # -- Loading package textio
> # -- Loading package std_logic_textio
> # -- Compiling entity user_logic_tbw
> # -- Compiling architecture testbench_arch of user_logic_tbw
> # vsim -lib work -sdfmax /UUT=.sdf -t 1ps user_logic_tbw
> # ** Error: (vsim-SDF-3196) Failed to find SDF file ".sdf".
> # Error loading design
> # Error: Error loading design
> # Pausing macro execution
> # MACRO ./user_logic_tbw.tdo PAUSED at line 7
> VSIM(paused)>
>
> I previously successfully simulated my design at Behavioral,
> Post-Translate, and Post-Map stages.
>
> Why can't it find the .sdf file? This should just work because
> everything should be set up automatically.
>
> I have the .sdf file in my project directory, called ppcaesh\, in
> \ppcaesh\netgen\par\ . The full path I'm using is
> C:\XilinxMe\ISE\AES01OC\ppcaesh\netgen\par\ . In that directory, I have
> two files, user_logic_timesim.sdf and user_logic_timesim.nlf . This is
> where ISE put them.
>
> >From the manual (the ModelSim User Manual, from http://www.model.com),
> -sdfmax /UUT=.sdf is telling ModelSim to use the sdf file, but why
> can't it find it in the place that ISE put it? I don't really know that
> /UUT=.sdf syntax. One would think that a filename before the .sdf
> should be getting put in there automatically. Also I realize that "UUT"
> stands for "Unit Under Test", but how is that significant to ModelSim?
>
> What would I set in ISE or in ModelSim, to patch this problem?
>
> I have searched the web to try to find answers on this, but can't find
> anything understandable, only snatches. I have downloaded the ModelSim
> manuals and tried to figure out what is going on from them, but this
> seems to be some conglomeration of ISE syntax using ModelSim and I
> couldn't find an explanation of that /UUT=.sdf syntax so that I could
> figure out what to patch. Can anyone tell me?
>
> Thanks in advance,
> -James
Article: 109586okay - thanks for your help ... I placed an order for a Conroe E6700 System - I hope I'll find some time for a little benchmark then ... bye, MichaelArticle: 109587
>I think S2 had tristate buffers but not S2E; either way, S3 and S3E >don't have them. Memory blocks are now larger and DLLs are more >functional as DCMs, both have "compatibility modes" for older designs. >There's no longer a power-on surge. You also have new, cheaper >programming ROM options. Are you sure the power-on surge is gone ..?, so far what I have seen this issue is on Spartan-3/3E aswell.Article: 109588
ben.s.vaughan@gmail.com wrote: >Hi, >I'm trying to program a prom on an Avnet development board for a >Virtex4 FPGA using iMPACT. Load up the mcs file ok and hit program.... >and wait.... and wait.... and wait. Let it run to about 40% done but >that took over an hour and half! I stopped it because i'm pretty sure >it shouldn't take that long. >What am I doing wrong here? Specify exact hw/sw setup you are useing..Article: 109589
FPGA wrote: > Hi All, > > I like to use the Spartan 3E Starter kit as audio capture/playback > developping system as it has Linear Technology's DAC and ADC built in. > Ideally I want to be able to connect it to a computer speaker and > microphone just like a computer sound card. But I guess it requires > some external analog circuit and also the line-in and line-out > connector to interfac with the DAC and ADC. > > Is there any reference design avaialbe for this type of external > circuit? Or if there is any commercial expansion/add-on card to > support this purpose that works with Spartna 3E Starter Kit? I've gotten audio output on the S3Esk DAC. See here for details: http://www.fpga.synth.net/beginners/spi_test.shtml Unfortunately, Digilent chose to put both the ADC and DAC on the same SPI interface, so because they have slightly different wordsizes and timing, making a system that can do simultaneous analog input and output is a bit more challenging. It also eats into your bandwidth. If you're interested in audio applications of FPGAs, the site mentioned above has links to a community of folks who are working in that area. EricArticle: 109590
Aurelian Lazarut schrieb: > Hi Annti, > I would call PCIexpress everything but "small little thing" > Aurash > Antti wrote: > > >Xilinx isnt advertizing 'small things' that are also coming as bonus > >with Virtex-5, I found one by accident while browsing the ML501 > >reference designs and docu, namly > > > >* Virtex-5 has fully dedicated pins for the parallel flash so any NOR > >flash connected properly as configuration memory is also accessible by > >the dedicated pins for both read and writes. Those it is possible to > >use indirect nor flash programming for V5-connected nor flash, and > >surprise it is already offered by Xilinx! its hidden in the "LAB > >resources" for ML501 but the indirect programming software and > >bitstreams are available for all v5lx devices. > > > >* anothes small thing is the access to configuration clock oscillator > >after configuration from FPGA fabric (but that has already been told > >here) > > > >* not to mention that the SYSMON what is there in V4 (but disabled by > >the tools) is now finally user accessible > > > >* CRC32 and CRC64 as primitives > > > >* EFUSE primitive whats that !? > > > >* KEYCLEAR primitive !! Thanks you, Xilinx! this is for clearing the > >encryption key from the FPGA fabric - I was missing this feature badly, > >now its there !! > > > >* PCIE primitive ? I am not believing what I am seeing ?! > > > >* PMV is still there too > > > >* USR_ACCESS is enhanced as well > > > >I guess there are some more nice small things hidden - anyone found > >something? > >or was I just dreaming? too late maybe I'd better rest or who knows > >what else > >I would be seeing! > > > >Antti > > > __ > / /\/\ Aurelian Lazarut > \ \ / System Verification Engineer > / / \ Xilinx Ireland > \_\/\/ > > phone: 353 01 4032639 > fax: 353 01 4640324 you are right I should have changed the subject line. initially i was only posting about the NOR flash indirect programming solution Antti http://www.microfpga.comArticle: 109591
Peter Alfke schrieb: > Just to clarify the situation: > Antti had ordered the evaluation board for Virtex-5, and Xilinx has > acknowledged and I suppose has shipped the order on Sept 27. > Now let's see how soon it reaches Antti in Munich, Germany, > (Antti please report to the newsgroup when it arrives. > It should not take weeks, the airplane hasn't that much fuel!) > Also, the present version of EDK already supports that board (with > minor wrinkles). > Let's then listen to the continuation of this story... > Peter > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > Antti wrote: > > Antti schrieb: > > > > > Peter Alfke schrieb: > > > > > > > You can order Virtex-5 devices from your distributor now, and he wi= ll > > > > offer short delivery times. Hi Peter, the order code left my hands, but I am not sure when the order was (or will be) placed. Its beeing processed and I will monitor the process. As of availability of Virtex-5 from distrubutors I can confirm that XC5VLX50--FF676 arrived from Avnet about 3 weeks ago already. So they are orderable, and have been sent out and reached the customer(s). Virtex-5 support in EDK 8.1 SP1 is defenetly there, and G=F6ran was even so kind and tested out a MicroFpga Virtex-5 bitstream on ML501 board. It just worked as made - a fresh new Virtex-5 EDK system worked on real silicon with the first attempt. So it is possible to create Virtex-5 SoC systems with EDK 8.1 SP1 that just work. AnttiArticle: 109592
Sir? You in a FPGA group.Article: 109593
Antti schrieb: > Peter Alfke schrieb: > > Just to clarify the situation: > > Antti had ordered the evaluation board for Virtex-5, and Xilinx has > > acknowledged and I suppose has shipped the order on Sept 27. > > Now let's see how soon it reaches Antti in Munich, Germany, > > (Antti please report to the newsgroup when it arrives. > > It should not take weeks, the airplane hasn't that much fuel!) > > Also, the present version of EDK already supports that board (with > > minor wrinkles). > > Let's then listen to the continuation of this story... > > Peter > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > Antti wrote: > > > Antti schrieb: > > > > > > > Peter Alfke schrieb: > > > > > > > > > You can order Virtex-5 devices from your distributor now, and he = will > > > > > offer short delivery times. > > Hi Peter, > > the order code left my hands, but I am not sure when the order was > (or will be) placed. Its beeing processed and I will monitor the > process. > > As of availability of Virtex-5 from distrubutors I can confirm that > XC5VLX50--FF676 arrived from Avnet about 3 weeks ago already. > > So they are orderable, and have been sent out and reached the > customer(s). > > Virtex-5 support in EDK 8.1 SP1 is defenetly there, and G=F6ran was even > so kind and tested out a MicroFpga Virtex-5 bitstream on ML501 board. > > It just worked as made - a fresh new Virtex-5 EDK system worked on real > silicon with the first attempt. So it is possible to create Virtex-5 > SoC systems with EDK 8.1 SP1 that just work. >=20 > Antti uups 8.1 above should be 8.2 of course, AnttiArticle: 109594
Lathi.Tan@gmail.com wrote: > Thank you all. I haven't tried it yet, but it must be the solution. > Will let you know when the problem is fixed. > > Lathi Asynchronous signal sampling using two cascaded FFs to avoid metastability was always one of the first things my teachers tried to pound into students' minds in design classes... and as a lab tutor, I have seen several students scratching their heads for hours before reminding them of this. A slightly more paranoid version of this would include glitch filtering as well - add some extra FFs and update the internal net only when all FFs match, hold the previous value otherwise. BTW, make sure the first FF gets packed into IOBs since these are usually designed to reduce the likelyhood of metastability ever happening and settle faster in case they fail to prevent it. Regular FFs are designed for highest speed and smallest footprint, they might never settle when they go metastable. -- Daniel Sauvageau moc.xortam@egavuasd Matrox Graphics Inc. 1155 St-Regis, Dorval, Qc, Canada 514-822-6000Article: 109595
pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote: >> I think S2 had tristate buffers but not S2E; either way, S3 and S3E >> don't have them. Memory blocks are now larger and DLLs are more >> functional as DCMs, both have "compatibility modes" for older designs. >> There's no longer a power-on surge. You also have new, cheaper >> programming ROM options. > > Are you sure the power-on surge is gone ..?, so far what I have seen this > issue is on Spartan-3/3E aswell. There are power on requirements, indeed. Simply not the 4x operating current (wild estimate, unsubstantiated) of previous parts. I haven't taken a current probe to my well-behaved boards, however. The fundamental problem with the older parts was addressed in the silicon. - John_HArticle: 109596
Link to entire thread:
http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/19eb30a581e0fe05/e1af05d2e561cff2#e1af05d2e561cff2
Hi All,
Thank you all for your kind replies, Brian, sepher, Berry. I did think
it looked suspicious that I had no actual filename for the .sdf file in
there. Xilinx tech. support said that "It looked like I didn't have a
UUT VHDL file," even though I sent him my entire project, making the
question of whether I had one or not a matter of fact to one who knows
the correct file name, which now looks like it should be
"C:\XilinxMe\ISE\AES01OC\ppcaesh\netgen\par\user_logic_timesim.vhd".
Looking at my GUI, in the Sources (for: Post-Route Simulation) window,
under my tbw file, I had a document icon labeled "UUT" to its right,
and in it I had an orange check mark. This indicated to me that I
probably didn't have some kind of required UUT VHDL file, so I called
up my FAE (Field Applications Engineer), and he realized that in order
to have that created, the following library has to be specified in the
top level design (VHDL) file, outside of the design (entity and
architecture) area.
-- synopsys translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- synopsys translate_on
This confirmed a fragment that I had found on the web. Searching for
"Warning: (vlib-34) Library already exists at "work"" turned up
http://www.fpga-faq.com/archives/62150.html , which said
--------------------------
Article: 62152
Subject: Re: please help, modelsim does not simulate
From: garrya@ihug.com.au (Garry Allen)
Date: 20 Oct 2003 18:31:49 -0700
This happens because Modelsim is not finding the appropriate library
declaring bufg...
at the top of your vhdl file when you include the libraries add
something like
-- synopsys translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- synopsys translate_on
--------------------------
I added that, and rebuilt down to and including "Generate Post-Place &
Route Simulation Model", and then I had something in there for the UUT:
C:\XilinxMe\ISE\AES01OC\ppcaesh\netgen\par\user_logic_timesim.vhd.
Then in "ModelSim Simulator" in the Processes Window, with "Simulate
Post-Place & Route Model" under it. I double- clicked on that and got
the following transcript after ModelSim comes up, in the ModelSim
transcript (output) window:
# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl
# do {user_logic_tbw.tdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE III vcom 6.1e Compiler 2006.03 Mar 8
2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Loading package vital_primitives
# -- Loading package textio
# -- Loading package vpackage
[compiling entities and architectures - all (snipped)]
# -- Loading package standard
# Model Technology ModelSim XE III vcom 6.1e Compiler 2006.03 Mar 8
2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity user_logic_tbw
# -- Compiling architecture testbench_arch of user_logic_tbw
# vsim -lib work -sdfmax /UUT=netgen/par/user_logic_timesim.sdf -t 1ps
user_logic_tbw
# Loading C:\Modeltech_xe_starter\win32xoem/../std.standard
# Loading
C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body)
# Loading
C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body)
# Loading
C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../std.textio(body)
# Loading
C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body)
# Loading work [snipped]
# Loading
C:\Modeltech_xe_starter\win32xoem/../vital2000.vital_timing(body)
# Loading
C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.vcomponents
# Loading
C:\Modeltech_xe_starter\win32xoem/../vital2000.vital_primitives(body)
# Loading
C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.vpackage(body)
[Loading work (snipped - 3 lines)]
# Loading
C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_buf(x_buf_v)
# Loading
C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_mux2(x_mux2_v)
# Loading
C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_lut4(x_lut4_v)
# Loading
C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_ff(x_ff_v)
# Loading
C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_sff(x_sff_v)
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C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_one(x_one_v)
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C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_zero(x_zero_v)
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C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_roc(x_roc_v)
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C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_toc(x_toc_v)
# Loading work [snipped]
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C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_ramb16(x_ramb16_v)
[Loading work (snipped - 5 lines)]
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C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_dcm_adv(x_dcm_adv_v)
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C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_dcm_adv_clock_divide_by_2(x_dcm_adv_clock_divide_by_2_v)
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C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_dcm_adv_maximum_period_check(x_dcm_adv_maximum_period_check_v)
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C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_dcm_adv_clock_lost(x_dcm_adv_clock_lost_v)
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C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_inv(x_inv_v)
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C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_srlc16e(x_srlc16e_v)
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C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_ckbuf(x_ckbuf_v)
[Loading my designed instances (snipped)]
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C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_and2(x_and2_v)
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C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_obuf(x_obuf_v)
# ** Warning: Design size of 147314 statements or 0 non-Xilinx leaf
instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
# Time: 0 ps Iteration: 0 Region: /user_logic_tbw File:
user_logic_tbw.vhw
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf
# .main_pane.workspace
# .main_pane.signals.interior.cs
# ** Warning: /X_FF HOLD Low VIOLATION ON I WITH RESPECT TO CLK;
# Expected := 0.187 ns; Observed := 0.132 ns; At : 0.335 ns
# Time: 335 ps Iteration: 3 Instance:
/user_logic_tbw/uut/inst_dcm_cg/dcm_autocalibration_dcm_adv_inst/dcm_adv_inst_ro_fd1
# ** Warning: /X_FF HOLD Low VIOLATION ON I WITH RESPECT TO CLK;
# Expected := 0.187 ns; Observed := 0.132 ns; At : 0.335 ns
# Time: 335 ps Iteration: 3 Instance:
/user_logic_tbw/uut/inst_dcm_cg/dcm_autocalibration_dcm_adv_inst/dcm_adv_inst_ro_fd2
# ** Failure: Simulation successful (not a failure). No problems
detected.
# Time: 2950 ns Iteration: 0 Process: /user_logic_tbw/line__96
File: user_logic_tbw.vhw
# Break at user_logic_tbw.vhw line 280
# Simulation Breakpoint: Break at user_logic_tbw.vhw line 280
# MACRO ./user_logic_tbw.tdo PAUSED at line 14
As you can see the vsim command line now has the correct filename: #
vsim -lib work -sdfmax /UUT=netgen/par/user_logic_timesim.sdf -t 1ps
user_logic_tbw .
And my post-PAR simulation gave correct results in the final output,
since I simulated with a conservatively slow clock of 50ns period (T).
Now my only concern is those two simulator warnings.
Cheers,
-James
Article: 109597Link to entire thread: http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/19eb30a581e0fe05/e1af05d2e561cff2#e1af05d2e561cff2 In my previous message, where I wrote: "I had a document icon labeled "UUT" to its right, and in it I had an orange check mark." That should be: "I had an orange QUESTION mark." Cheers, -JamesArticle: 109598
>BTW, make sure the first FF gets packed into IOBs since these are >usually designed to reduce the likelyhood of metastability ever >happening and settle faster in case they fail to prevent it. Regular FFs >are designed for highest speed and smallest footprint, they might never >settle when they go metastable. What's the prop time from an input FF in an IOB to a nearby FF as compared to two FFs inside the logic that are near eachother? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 109599
On Fri, 29 Sep 2006 16:07:08 -0400, "Daniel S." <digitalmastrmind_no_spam@hotmail.com> wrote: >BTW, make sure the first FF gets packed into IOBs since these are >usually designed to reduce the likelyhood of metastability ever >happening and settle faster in case they fail to prevent it. Regular FFs >are designed for highest speed and smallest footprint, they might never >settle when they go metastable. Actually what you want is the fastest dff followed by the smallest delay to the next flop so a "regular" flop is probably better.
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