Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
"Joseph Goldburg" <wizard1@SPAMnetspace.net.au> wrote in message news:c5ri60$15ed$1@otis.netspace.net.au... > What's the difference between say the Xilinx Coolrunner CPLD > and the Xilinx 4000 FPGA series. > > I noticed the coolrunner dev kit for $50 USD The Coolrunner is a current product and the 4000 series devices are obsolete. 8-) LeonArticle: 68776
Tools used: EDK and ISE 6.2 on Win2000. I compiled the Memec HelloWorld project and successfully ran it on their Spartan IIELC reference design board. With this working project, I changed its properties to a sub-module and exported it to Project Navigator project that had a schematic top level file. I created the library symbol for the sub-module, placed the sub-module and an counter on the schematic and I ran it all the way to Generate Programming File. When I downloaded the bit file, the counter worked, but the Microblaze did not. Even going back to Platform Studio and using the import function did not create a working bit file. I found by extensive poking around that the Project Navigator does NOT automatically update the BMM file with the newly placed locations of BRAM that holds the Microblaze program. (The export from XPS did add a system.BMM, but that file did not have any placement info--the file just had the names of the BRAM instances and the memory bit positions.) Data2Mem needs the placement information to create a new download file. I found that I could use the FPGA editor in Project Navigator to find out where the last PAR operation put the BRAMs. I created a new BMM file from the system.BMM and included the placement info. Specifying this BMM file with the .ELF allowed Data2Mem to create a WORKING Microblaze sub-module bit file. You can manually run Data2Mem in the Project Navigator or use the dialog in XPS (which calls Data2Mem in the script) as long as you supply the correct BMM file. A valid line in a BMM text file for Data2Mem is: bram_1mb/bram_1mb/ramb4_s2_s2_0 [31:30] PLACED = R3C0; The BMM files exported to Project Navigator by XPS did not have the field starting with "PLACED.." After going from PAR to bit file creation, the BMM file still did not change, even though the subsequent Data2Mem procedure to combine the ELF data requires placement info in the BMM. It is quite reasonable not to supply any placement before PAR, because PAR is allowed to move things around, but the final placement info should be extracted and updated into the BMM file. In this example, I manually added the placement information. I have seen a few posts regarding this problem. Is there a button or procedure in Project Navigator to automatically extract new BRAM locations and update the BMM file? Of course I already have a work-around, like forgetting about sub-modules and keeping the project exclusively in XPS !Article: 68777
Hi, I have the NIOS developer board with APEX FPGA.It has a SODIMM socket for SDRAM module. I use a Micron MT8LSDT864HG-10ECS. I make a Quartus project based on verilog/standard_32. I use nios_32 CPU. I create a new memory configuration based on Micron datasheet and I put it into class.ptf from altera_avalon_new_sdram_controller. I write a simple program that can read and write memory maped in sdram. This configuration has Location Vector, Program and Data memory set to ext_ram which is SRAM. But next I change Progam and Data memory to sdram. Program is compiled correctly and srecord looks ok. I load it to board using nios-run. When program starts it prints only "Return address is 0x00000000" and returns to GERMS. The same situation is which all demo programs from cpu_sdk and my own programs. I will be very thankful for any help. Best regards, Maciej Witaszek -- Maciej Witaszek nospam_mwitaszek@elka.pw.edu.pl remove "nospam_" from my addressArticle: 68778
I have downloaded the quartusIIwe, and used it to synthesize some modules for cyclone parts - works great. Now I would like to try SOPC builder and compile some C for an existing nios board, but am a little confused about the toolchain. QuartusII comes with cygwin, but it looks like there is no gcc, etc. for nios. Altera's site says the Gnupro tools for nios do not require a license, but I don't see where I can get these tools without purchasing a license. Altera has a link to their ftp site where the sources are supposed to be, but there are no files there. No sign of nios tools on the redhat site either. It looks like the tools used to be free but no longer. What's the story? Are the SW tools free or not, and where do I get them? I see there is an independant CDK for nios in sourceforge. Is this a direct replacement for gnupro?, or is there some downside to using these like no integration with quartusII? thanksArticle: 68779
On Sun, 18 Apr 2004 00:10:58 +0200, tns1 wrote: > What's the story? Are the SW tools free or not, and where do I get them? Hi, The path to gnupro tool that's published at http://www.altera.com/support/kdb/rd11272000_7307.html are wrong. You may ask a Support to correct one, because I obtain it from them. If they don't want to tell you, ask me to send you the address. The gnupro tools are published under GPL, so it's free. But I don't know if I can publish a path to it. (??) It's a source code of tool chains only:gcc, gdb, ld, ... It doesn't have nios-build and nios-run tools, a SOPC Builder and NIOS components like CPU core. You should obtain them with your dev board. The source code is at some pleaces broken. There are new line where it shouldn't be. In some files there are new lines in DOS format rather than in Unix. So it needs some expererience in Unix/Linux programming. I compiled it with gcc-3.3.3 from Gentoo Linux. I was trying older gcc-2.54, but without success. I thin that it's possible to compile gnupro under Windows using Cygwin libraries. Best Regards, Maciej Witaszek -- Maciej Witaszek nospam_mwitasze@elka.pw.edu.pl remove "nospam_" from my addressArticle: 68780
"Leon Heller" <leon_heller@hotmail.com> wrote in message news:<40800138$0$25243$cc9e4d1f@news-text.dial.pipex.com>... > "prav" <praveenkn123@yahoo.com> wrote in message > news:863df22b.0404160428.43706c3b@posting.google.com... > > Hi all, > > > > i have got a basic doubt in altera's flex10 k library component > > "8count" which is a 8-bit up/down counter.This library component has a > > output named "COUT" is it the decoded version of terminal count(255) > > or something else ?? > > any body can clarify this!! > > > > thanks in advance > > I've just used this counter, but I didn't use COUT. I think it means Carry > Out. You could always check the AHDL code for the part to see exactly what > it does. > > Leon Hi Leon , thanks for u r reply! where can i get the AHDL code for the part "8count"? rgds, pravArticle: 68781
> I have seen a few posts regarding this problem. Is there a button or > procedure in Project Navigator to automatically extract new BRAM locations > and update the BMM file? Of course I already have a work-around, like > forgetting about sub-modules and keeping the project exclusively in XPS ! I'm stil working with EKD3.2 and ISE5.2 but for me it the following works perfectly fine: I add the .bmm file to the "sources" in the project navigator tree ... after place&route I've got a new .bmm file in my ise-directory with all the placement included ... bye, MichaelArticle: 68782
Hello,
i want to create a special UART with a FIFO (at least 64 Bytes deep, perhaps
bigger).
Can someone tell me, how a FIFO can be implemented in hardware ? Is is
"simply" an array of bytes, with two counters: one for filling it in and one
for reading out ? Or is there a better approach ?
At the moment i have only knowledge in ABEL with XILINX CPLD (XC95) series.
Is it the right way to use a CPLD (perhaps a big one, because of the amount
of storage cells needed only for the FIFO) ? Or does a FPGA (i read they
have RAM inside, where i hopefully can put my FIFO in ?) fit better this job
? What XILINX chip (because of already available environment) do you
recommend for this and why ?
Regards and thanks for helping,
Martin
Article: 68783> thanks for u r reply! > where can i get the AHDL code for the part "8count"? > > rgds, > prav It is in /quartus40/libraries/others/maxplus2/8count.tdf - Subroto Datta Altera Corp.Article: 68784
Hi, o, I'm afraid I can't enlighten you in respect of tools that create FSM diagrams from code, but how about a bit o' working practices enlightenment? I'm often engaged in design work under contract and like you end up designing FSMs for my clients (as well as other more fun blocks of hardware). Some clients appreciate the time you spend thinking, analysing requirements, architecturing and designing 'before' you begin coding. They're the smart guys. I've had 5 clients like this. Other clients just expect you to start coding on the first day. Try to educate them, you may not succeed completely, but you might buy enough time to do some of the pre-coding work which in the long run usually pays off. I've had 1 client like this. If you have an interview before you start, try to guage "How smart is the client?". If they just want a code-monkey, you might think about turning them down - in my experience, clients who skimp on doing things properly in terms of design tend to skimp in other areas, too - the skimp concept permeates their entire culture. Incidentally, I have a software engineer pal who hasn't written a line of code for over a decade as part of his day-to-day work; he analyses and documents, defines standards and other software engineering 'things' - he writes code at the weekends whilst at home to keep up-to-date as a programmer; his oft-quoted comment is "One day, I'll get paid to do this!". Ironic how the software community seems to understand that it "isn't about the code", isn't it? I guess how you document FSMs isn't that important, just documenting them is the key thing - that documentation department ought to know better! TimArticle: 68785
"prav" <praveenkn123@yahoo.com> wrote in message news:863df22b.0404172229.7a5fb04e@posting.google.com... > "Leon Heller" <leon_heller@hotmail.com> wrote in message news:<40800138$0$25243$cc9e4d1f@news-text.dial.pipex.com>... > > "prav" <praveenkn123@yahoo.com> wrote in message > > news:863df22b.0404160428.43706c3b@posting.google.com... > > > Hi all, > > > > > > i have got a basic doubt in altera's flex10 k library component > > > "8count" which is a 8-bit up/down counter.This library component has a > > > output named "COUT" is it the decoded version of terminal count(255) > > > or something else ?? > > > any body can clarify this!! > > > > > > thanks in advance > > > > I've just used this counter, but I didn't use COUT. I think it means Carry > > Out. You could always check the AHDL code for the part to see exactly what > > it does. > > > > Leon > > Hi Leon , > > thanks for u r reply! > where can i get the AHDL code for the part "8count"? If you have placed the part, you can just double click on the symbol. LeonArticle: 68786
"Martin Maurer" <capiman@clibb.de> wrote in message news:<c5ti7m$ljn$07$1@news.t-online.com>...
> Hello,
>
> i want to create a special UART with a FIFO (at least 64 Bytes deep, perhaps
> bigger).
> Can someone tell me, how a FIFO can be implemented in hardware ? Is is
> "simply" an array of bytes, with two counters: one for filling it in and one
> for reading out ? Or is there a better approach ?
Do a search, esp. of the FPGA/CPLD vendor web sites. FIFO examples
abound. A FIFO is a homework assignment :)
> At the moment i have only knowledge in ABEL with XILINX CPLD (XC95) series.
> Is it the right way to use a CPLD (perhaps a big one, because of the amount
> of storage cells needed only for the FIFO) ? Or does a FPGA (i read they
> have RAM inside, where i hopefully can put my FIFO in ?) fit better this job
Unless you're using one of the new Lattice XPLDs, you can't use a CPLD
to do a FIFO using internal RAM, since CPLDs ('cept those Lattices)
don't have internal RAM.
> ? What XILINX chip (because of already available environment) do you
> recommend for this and why ?
Pick one that has enough internal resources for your application. Any
of the Xilinx (or Altera, or other brands) will do fine.
Article: 68787Very cool. Why are you selling it? Do you have any closeups of the Virtex. How did you route the pins out? How is the BGA attached to board. Did you use reflow? jaxlau@yahoo.com (Jacques athow) wrote in message news:<acc717b2.0404162015.6a20ae26@posting.google.com>... > our final year project.. thanks to everyone that answered my > questions. We spent more than 1000hours on this project. I wanna see > how much it can go for! > > Xilinx rulez! >Article: 68788
Hello Hendra, see down please: ----- Original Message ----- From: "Hendra Gunawan" <u1000393@email.sjsu.edu> Newsgroups: comp.arch.fpga Sent: Saturday, April 17, 2004 1:58 AM Subject: Re: Problem downloading with parallel converter > "Peter Seng" <NOSPAM@seng.de> wrote in message > news:c5iov3$sfa$1@online.de... > > First try to make changes to the parallel port settings - see Quatech > > documentation. If You can not change the mode, try to set base adress to > > 3BCh (this address should not be capable to work in EPP or ECP mode) or > > contact Quatech and ask if the mode can be set to a user defined status. > > Interupts are of no interest - they are not used by parallel cable III. > > SPP and PS2 ports use a range of 3 adresses, EPP uses a range of 8 > adresses > > and ECP uses two ranges of 8 adresses. > > Which I/O adresses are accessed (adresses and range)? > > > I use 0378-037F. According to the quatech manual, the only configuration > mode that use standard port mode is configuration #9. I tried to change to > that mode but it won't let me to set the base address to 03BC because it is > used for another device. Try to set the occupying device to another address, or if possible disable it. > Could you tell me the address range for SPP, PS2, EPP and ECP so I can play > with it? Standard base adresses are 3BCh, 378h, 278h (named LPT1-LPT3, in this order), but 3BCh is the only not able to be set to EPP or ECP mode. Ranges see above. EPP and ECP may use a secondary adress range at baseadress + 400h. > > > ??? do You use the Xilinx cable and a standard parallel cable to make the > > Xilinx cable longer? > > No, I don't use Xilinx cable at all. My FPGA board is a simple one. > https://digilent.us/Sales/Product.cfm?Prod=D2E The hardware does not look as it is Xilinx compatible, different drivers and missing capacitors.... On our systems we also use different drivers and no capacitors at all - but we do it inside an FPGA - and we also had problems first - so we included digital filtering (instead of capacitors) and it worked afterwards. -> Try to built or lend a Xilinx download cable (Parallel cable III, schematic on the net, see Xilinx). If it works use this. or -> try to connect a 1nF capacitor between TCK and GND of Your board. Not shure if it works.... and/or -> ask digilent what to do, describe your problems > I just connect the board to my laptop using a standard parallel cable. > https://digilent.us/Sales/Product.cfm?Prod=PLLCBL > Thank You! > > Hendra good luk, Peter ############################# SENG digitale Systeme GmbH Im Bruckwasen 35 D 73037 Göppingen Germany tel +7161-75245 fax +7161-72965 eMail p.seng@seng.de net http://www.seng.de ############################# > >Article: 68789
"Kelvin" <kelvin8157@hotmail.com> writes: > well...i will search it again and again until i can find one...dun think > i can afford that kind of price... If you just want to learn about PCI Express you can buy a book, .e.g. the earlier mentioned mindspring book, or "The Complete PCI Express Reference" from Intel Press. If you are about to implement PCI Express you can not affort to not get the spec... Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 68790
Peter Alfke wrote: > Fine frequency resolution with reasonably low jitter. > > I just finished and tested an FPGA design using a 30-bit DDS phase > accumulator that is conservatively clocked at 80 MHz and, with the help of a > DCM in Frequency Synthesis mode and a binary divider chain, generates any > frequency from 1 Hz to 80 MHz with 1 Hz granularity. > The output period jitter is <300 picoseconds peak-to-peak. > There is a roadmap to increase the output frequency to max 5 GHz at > substantially reduced jitter. Seems there's a lot packed into a few sentences here - when/where can we see more info ? -jgArticle: 68791
I'm interested in getting some analog signals out of and into a FPGA. The context is fine tuning the frequency of a crystal and measuring temperature and supply voltages. I don't need high speed. A 1 Hz response is overkill. I'm thinking of 16-20 bits of resolution. I don't need absolute calibration on offset or scale, I can compensate for that in software. I want the low bits to be clean. I want it to be linear within a local region. I don't care (much) if the slope at one end of the range is the same as the middle or other end. (I can correct for that with software.) Stability over time and temperature (and VCC) would be good. It's probably OK if I can measure and correct for it. This is for a hack/hobby project. (Or maybe just a thought experiment.) One obvious approach is to get a D/A chip and let it do all the work. Anybody got any favorite chips for this sort of application? A quick scan on the net finds lots of Audio chips with many bits of precision in the audio band, but I'm not sure what happens at very low frequencies. I doubt if they are very stable over temperature and VCC. Pulse width modulation is the classic way to do low speed D/A from digital logic. For this purpose, I think I can do better by spreading the on bits over the whole time slot rather than clumping them all at the beginning. (Better low frequency noise.) For example, if I wanted slightly lower than 1/3 of full scale, I would send 1 on pulse, and 2 or 3 off pulses, adjusting the ratio of 2 and 3 off pulses to get the best answer. What's the term for this approach? Is there a good writeup someplace? If I use 1 megohm and 1 uF as a filter, that's 1 Hz time constant, so that's the right ballpark. If I run the clock at 1 MHz that's 20 bits of resolution. One advantage of this approach is that the output level doesn't depend upon the value of the resistor (assuming no/tiny load). It's just the ratio of on time to total time and that is easy to control in the digital domain. So the temperature coefficient of the resistor doesn't matter. If I use an op-amp as a buffer, the temp coefficient of the offset voltage may be the limiting factor on stability. How would you test/evaluate something like this? Make two and compare them while you heat one of them? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 68792
Hi, This is somewhat OT, but I can't find a more suitable newsgroup. I am using a Gigabit Ethernet MAC chip from Marv***, which claims full line rate (compliance to IEEE 802.3ab). It has an integrated GMAC, PHY/Serdes, and PCI interface (64-bit, 66MHz). On the PCI bus side, we connect it to a Spartan IIe-300 with a Xilinx PCI Logicore. Everything works in the FPGA, PCI read/write transactions, but we cannot achieve full line rate for 64-byte frame length. We can only achieve 680Mbps because of the overhead in reading/writing descriptors. My questions are: Is this expected? Is this acceptable? I have no prior experience with Gigabit Ethernet MAC, and appreciates any feedback. Thanks Kang Liat ChuanArticle: 68793
Hi Folks, I am using the rocket IOs of the Xilinx Virtex II pro chips, with are working fine, but: While testing different frequencies in simulation, it seems, that if clock correction IDLEs are inserted in data between the SOP/EOP of a CRC checked data package, this results in an CRC error if clock corrections are needed during readout of the receiver elastic buffer, which is not documented in the rocket io user guide. This means, that there is no possibility to do any clock correction during the receive of crc-checked data and IDLEs could only be transmitted outside the SOP/EOP. Does anyone know, if this is generally true ? Thanks in advance, Stefan Philipp -- Stefan Philipp Electronic Vision(s) Room 1-319 Kirchhoff-Institut für Physik Im Neuenheimer Feld 227 69120 Heidelberg Tel.: ++49-6221-54-9897 Fax: ++49-6221-54-9839 -- Hi ! I'm a signature virus. Please copy me to youre signature file to help me spread !Article: 68794
>My questions are: Is this expected? Is this acceptable? I have no >prior experience with Gigabit Ethernet MAC, and appreciates any >feedback. It's not surprising. Is the limitation in the hardware or in the software? Are you running out of PCI bus cycles or CPU cycles? Count the cycles on the PCI bus and do the arithmetic. How many CPU cycles does it take to process each packet? Are you reading/writing the packets from off-chip memory? How long does that take? "acceptable" depends upon your usage/application. It could be a disaster if the box on the other end is sending faster than you can receive so that X% of the packets are falling through the cracks. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 68795
On 19 Apr 2004 02:19:04 -0700, kanglc@starhub.net.sg (owner) wrote: >Hi, > >This is somewhat OT, but I can't find a more suitable newsgroup. > >I am using a Gigabit Ethernet MAC chip from Marv***, which claims full >line rate (compliance to IEEE 802.3ab). It has an integrated GMAC, >PHY/Serdes, and PCI interface (64-bit, 66MHz). On the PCI bus side, we >connect it to a Spartan IIe-300 with a Xilinx PCI Logicore. > >Everything works in the FPGA, PCI read/write transactions, but we >cannot achieve full line rate for 64-byte frame length. We can only >achieve 680Mbps because of the overhead in reading/writing >descriptors. > >My questions are: Is this expected? Is this acceptable? I have no >prior experience with Gigabit Ethernet MAC, and appreciates any >feedback. I've seen Marv*** GbE PHYs work at 100% of line rate, in one of these: http://advanced.comms.agilent.com/RouterTester/datasheets/e7918a.htm Never used one of their MACs though. Umm, 64 bytes frame + 8 bytes preamble and SFD + 12 bytes minimum interframe gap = 84 bytes on the line => 1.4881 Mpps, which corresponds to 761.9Mbps of useful data transfer. You seem to be achieving about 89% of this. This wouldn't be acceptable for test equipment, but may be ok for your application (which you didn't specify). Regards, Allan.Article: 68796
Hi all, I am implementing the DPLL functionality of 74LS297 in an FPGA. For the K-counter in that block there are two outputs namely carry and borrow. I will just explain how i have implemented this. The phase detector(ECPD) output is fed to the K counter if it is high" the counter increments else decrements.In my implementation i have tied ABCD="1000" i.e it is 3 stages long (3 - bit counter). Now the "carry" is set high when phasedetector output is high and K counter value is "111". The "borrow" is set high when phasedetector output is low and K counter value is "000". i wanted to know if what ever i have implemented is right or if i am going wrong anywhere. can anybody tell me how this "carry" and "borrow" signals are really used and generated. Thanks in advance. rgds, pravArticle: 68797
On Mon, 19 Apr 2004 09:10:38 -0000, hmurray@suespammers.org (Hal
Murray) wrote:
>I'm interested in getting some analog signals out of and into a FPGA.
>The context is fine tuning the frequency of a crystal and measuring
>temperature and supply voltages.
>
>I don't need high speed. A 1 Hz response is overkill. I'm thinking of
>16-20 bits of resolution.
That's only a few microvolts...
>I don't need absolute calibration on offset or scale, I can compensate
>for that in software. I want the low bits to be clean. I want it to
>be linear within a local region. I don't care (much) if the slope at
>one end of the range is the same as the middle or other end. (I can
>correct for that with software.)
>
>Stability over time and temperature (and VCC) would be good. It's
>probably OK if I can measure and correct for it.
>
>This is for a hack/hobby project. (Or maybe just a thought experiment.)
>
>One obvious approach is to get a D/A chip and let it do all the work.
>Anybody got any favorite chips for this sort of application?
Given your very low speed and high resolution needs, I suspect you
may end up with a much cheaper solution *without* the external chips,
as you're obviously thinking yourself.
>A quick scan on the net finds lots of Audio chips with many bits of
>precision in the audio band, but I'm not sure what happens at very
>low frequencies. I doubt if they are very stable over temperature
>and VCC.
As you say, their DC performance tends to be iffy. But you do
get good resolution, and all the difficult digital stuff (noise
shaping digital filters, etc) is done for you. And they are
amazingly cheap for what you get.
>Pulse width modulation is the classic way to do low speed D/A from
>digital logic.
That would be my first port of call, too.
Given excellent D/A conversion, you have lots of options
for A/D. Cheapest of all is timing how long it takes to
charge a capacitor up to the input voltage from a known
source. Dual-slope techniques are great.
> For this purpose, I think I can do better by spreading
>the on bits over the whole time slot rather than clumping them all at
>the beginning. (Better low frequency noise.) For example, if I wanted
>slightly lower than 1/3 of full scale, I would send 1 on pulse, and 2
>or 3 off pulses, adjusting the ratio of 2 and 3 off pulses to get the
>best answer. What's the term for this approach? Is there a good
>writeup someplace?
Nothing I've seen in the form you want, although it's exactly what
the hi-res audio converters do, and seaerching for information on
"delta-sigma modulation" and "noise shaping digital filter" should
turn up plenty of interesting stuff.
I've played with this sort of PWM before, so a few musings follow.
My guess is that you've thought about all these things already,
but just in case... see the bottom of this post.
>If I use 1 megohm and 1 uF as a filter, that's 1 Hz time constant, so
>that's the right ballpark. If I run the clock at 1 MHz that's 20 bits
>of resolution.
You can do MUCH better than this, by noise shaping. Audio DACs get
20kHz+ bandwidth and 20-bit resolution with a clock of only a few MHz.
But your bandwidth is so very low that you probably don't need those
difficult digital tricks.
To understand what happens to your least significant bits in this
scheme, imagine that the PWM is set to a value of just 1 (one clock
on, a million clocks off). Now think about what your first-order
lowpass will do to that signal.
Don't forget that the 20-bit settling time of a first order
lowpass filter is much longer than one time constant:
time error effective resolution
(%) (bits)
1RC 37 1
2RC 13 3
3RC 5 4
4RC 1.8 5.5
5RC 0.7 6.8
...
10RC 0.0045 13.6
...
15RC 0.00003 20.3
>One advantage of this approach is that the output level doesn't depend
>upon the value of the resistor (assuming no/tiny load). It's just the
>ratio of on time to total time and that is easy to control in the digital
>domain. So the temperature coefficient of the resistor doesn't matter.
Nor does the tempco/value of the capacitor, which is likely to be
just as variable.
But the power supply voltages that you're switching most certainly do
have an effect.
>If I use an op-amp as a buffer, the temp coefficient of the offset
>voltage may be the limiting factor on stability.
And the offset current - remember you're using a fairly big resistor
in your first-order lowpass section.
>How would you test/evaluate something like this? Make two and compare
>them while you heat one of them?
Make a nice quiet well-filtered reference, subtract from your DAC
output, amplify???
Post something on sci.electronics.design and hope that the nanovolt
gurus there (notably Winfield Hill) will respond with some amazingly
cool suggestions???
Anyways, back to the FPGA-related stuff: Your idea of spreading
the PWM pulses out over the duration of the cycle is interesting,
specially for very low bandwidth applications. As you say, it
reduces the low frequency spuriae, and therefore makes it easier
to filter. I coined the name "distributed PWM" to contrast with
the traditional "block PWM" technique; I have no idea whether
these terms have any legitimacy. You can make a simple
distributed PWM by using a first order delta-sigma modulator;
it's essentially the same trick as Bresenham's algorithm
for drawing angled lines on a raster display. Conceptually
the algorithm is:
* maintain a signed accumulator register A
* establish a PWM cycle length, N clock cycles
* have a "desired output" value V
* on each clock cycle, accumulate A = A + V, and then...
- if A is negative, supply 0 as the output
- if A is positive, supply 1 as the output and modify
the accumulator by forming A = A - N
In practice you lose very little by making N an exact power
of 2, and then the last step (subtract N) comes free with
the arithmetic overflow that gave you a positive A; and
the output value is simply the most significant bit of A.
There's an interesting tweak: if you add the carry-out
from the A=A+V operation back in to the next operation,
then the effect is to make N just one less than the round
power of 2, and you can get the full range of "always off"
through to "always on" without needing an extra bit of
input. I can let you have VHDL or Verilog code examples
for all this if you are interested.
There are, however, several snags. First, like any PWM
generator, the output is directly affected by the power
supply and ground voltages that you're emitting on the
output pin. One easy workaround is to use the output
to switch a CMOS pass-switch (CD4066, or one of the newer
versions) which can be used to get the PWM output from a
clean voltage reference instead of the noisy digital supply.
Second, there is no guarantee that your switching is
symmetrical, so each switching transition introduces some
bias - and, unlike "block PWM", the number of switch
transitions per PWM cycle is very variable. This will
introduce some gruesome nonlinearities. However, it's
not hard to deal with this one too. The key is to
ensure that you get a fixed number of output transitions
in any reasonably short period of time. You can do this
by dividing the PWM cycle into a number of sub-cycles,
and use "block PWM" within each of these sub-cycles. If
this sub-cycle is never allowed to go always-off or
always-on, it is certain to have just one rising and one
falling transition on the output. Of course this stops
you from getting full-scale output, but from the sound
of your application that would not be a problem.
The delta-sigma accumulator now looks like:
* establish the range of values that you can produce
within a single sub-cycle: for example, if the
sub-cycle is 18 clocks long, its output can range
from 1/18 to 17/18, giving a range R of 16.
* establish the number of sub-cycles per PWM cycle,
S = N/R.
* at each sub-cycle boundary:
- form A = A + V
- find the required sub-cycle value X by taking
the whole-number part of A/S
- update A = A - X*S
- use X+1 as the sub-cycle PWM value
(to avoid always-off)
Obviously all this is much easier if S is a power of 2.
Now we have exactly two transitions per sub-cycle and
the transition-related error should be close to constant.
Be careful though: much of the transition-related error
will come from charge injection in your CMOS switch,
and its value will be affected by the digital supply.
With any luck, it's a second-order variation in a
second-order effect and should be negligible.
Apologies if this is all stuff you know about already.
Good luck!
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 68798
On Mon, 19 Apr 2004 12:13:11 +0100, Jonathan Bromley
<jonathan.bromley@doulos.com> wrote:
[stuff]
>
>Don't forget that the 20-bit settling time of a first order
>lowpass filter is much longer than one time constant:
>
>time error effective resolution
> (%) (bits)
[snip wrong numbers]
Whoops, fingers slipped on spreadsheet...
time error effective resolution
(%) (bits)
1RC 37 1.4
2RC 13 2.8
3RC 5 4.3
4RC 1.8 5.8
5RC 0.7 7.2
...
10RC 0.0045 14.4
...
14RC 0.00008 20.2
15RC 0.00003 21.6
Doesn't really affect what I was saying, though.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 68799Jonathan Bromley wrote: > On Mon, 19 Apr 2004 09:10:38 -0000, hmurray@suespammers.org (Hal > Murray) wrote: > > >>I'm interested in getting some analog signals out of and into a FPGA. >>The context is fine tuning the frequency of a crystal and measuring >>temperature and supply voltages. >> >>I don't need high speed. A 1 Hz response is overkill. I'm thinking of >>16-20 bits of resolution. > > > That's only a few microvolts... Yes. A discrete solution with PWM or a DAC requires a comparator being able to sense these microvolts. Considering that the usual offset voltage is in the 2 digit microvolt region, that won't be easy. Further a comparator needs overdrive. It might be simpler to use a standard 20 or 24bit ADC, eg LT2404, LT2424, LT2440 plus a few more. Also Analog Devices has a few. They cost in the order of 7$US. Getting them to produce between 16 and 20 bits is tricky enough. Good luck. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z