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Hi, please have a look at my homepage again. I've put some additional colors in the plot to make it more clear. Hope that helps to understand the problem. I would appreciate your time and help. Kind regardsArticle: 68926
john jakson wrote: > hmurray@suespammers.org (Hal Murray) wrote: >>>F(A,B,C,D) = /A*B*C*D + A*/B*C*D + A*B*/C*D + /A*/B*/C*D + >>> A*B*C*/D + /A*/B*C*/D + /A*B*/C*/D + A*/B*/C*/D Four input XOR was going to be my guess. >>>If you allow some of the outputs of the 2-input AND gates to be shared >>>across minterms, then you can cut 8 AND gates and get down to 23 2-input >>>gates. >>That looks like odd parity, aka an XOR tree. If Peter's claim >>of a (2 input?) XOR counting as 4 NANDs, then we can built it in >>2 layers using 12 gates rather than 23. Did I miss something? As far as I know, gate counting in CMOS is the number of transistors divided by four (the number for NAND2). > In almost any ASIC cell lib, an XOR can be as little as 1 2nand gate > for the elcheapo xfer common control version or usually about 2 2nand > gates worth of area for the much better aoi version. I could look up > the actual sizes for AMI,HP,VLSI but those are dated 0.6u. An inverter > usually costs about 70% of a 2nand. Its not the transister count but > the local interconnect that can make some of these bigger cells not so > big after all. Please forget about counting 2nand equivs. It makes no > sense for ASICs or FPGAs. Transistors divided by four is slightly different from a logic point of view, but seems reasonable to me. (snip) >>I'm assuming NOR and NAND count the same. Is that generally true? >>How do ASIC people count inverters? A whole gate or a partial gate? >>How about AND vs NAND? Do I get a free inverter sometimes? > Nand & Nor are usually 1 unit but Nands are much prefered over Nors > due to p being 1/2 strength of n fets. Inverter is 0.7 of 2nand. > And/Or might usually be 1.7 or possibly smaller say 1.5 for local > optimisation. Each cell generally has some cost just to insert power & > substrate hookup and DFlops, adders & bigger muxes are spared the > insertion cost by cramming as much as possible into the 1 fixed cost > per cell. For TTL, NAND is much simpler than AND and OR, which are simpler than NOR. For CMOS, other than the difference above, I believe that NAND, NOR, AND, OR all take the same number of transistors. > You can get some of this ASIC lib info from TLSI,UMC even Mosis and if > you ask nicely a sales guy will hand you the books, just don't say you > are using FPGAs. I would say that a fair way to count the gates is to generate the CMOS ASIC logic, count the transistors, and divide by four. One could do this for many designs that would fit into a given FPGA, and average the results. -- glenArticle: 68927
Simon Peacock wrote: > I would agree ... and stand corrected ... but can you always think of the > right words ... :-) > > But I did point out that you re-sync... that implies something... and I > believe the delayed shift register (mentioned in this thread) has already > been done but that also requires a clock. > and so I think most people have seen an "AT" modem.. re auto baud.. Hayes > and stuff like that .. even they have clocks. FPGA's are synchronous.. so > is a UART. All comms is synchronous or synchronised. (unless its simply on > and off!) It becomes an exercise in semantics : Uarts require triggered, time interval sampling. You _can_ build a uart without an external, precision, always on clock source. To some, that qualifies as 'not using a clock'. Others might say any digital-divider must have a register, and that register must be clocked, so all registers are verboten in a purists 'Clockless uart'. That design can be done with a delay line ( which needs baud-precision - not really a common building block...), plus it's not clear how it would manage sync in packed streaming data... Complex Async ICs design is not truly clockless, but it can be self-timing, and not locked to a common bus'd clock. The OP's question sounded rather like homework, than any real problem needing a practical solution.... -jgArticle: 68928
khiltrop@gesytec.de wrote: > Hi, > > > I do not know if this matters: it is a Spartan IIe 50k device, interfaces > are - or JTAG or parallel. > > One project, a small test vhdl code, can be loaded and works correct. Both > ways JTAG and parallel are possible. > > Another larger project cannot be loaded. > The Impact-Loader says after 'loading' that the 'done-pin does not go > high'. Indeed the done-pin remains low, also when loading via parallel > interface via microprocessor. > > The BIT-file which is used in any of the cases, was compiled with ISE 4.2i > as well as with the newest WebPack 6.2.02i > > Any hint how a compiled file can be wrong so the BIT-file cannot be > loaded? Either use a pullup resistor on DONE or configure the BIT-File to drive the DONE pin high (Startup Options in Generate Programming File Properties) > > > Klaus Hiltrop >Article: 68929
HI,
Thanks to all who gave a response. Actually i need the VCD file
for power calculation. So, please tell me whther i have to simulate
with the correct data(clk frequnecy depends on the max.frequency
allowed) or not for generating VCD file.
Article: 68930Morris Ho wrote: > Tools used: EDK and ISE 6.2 on Win2000. I compiled the Memec HelloWorld > project and successfully ran it on their Spartan IIELC reference design > board. > [...snip...] > I found by extensive poking around that the Project Navigator does NOT > automatically update the BMM file with the newly placed locations of BRAM > that holds the Microblaze program. I'm still using EDK3.2, but have had similar problems and maybe that will help you: When you set the hierarchy to "sub-module" in XPS, you have to give it the name of the top instance. This name is used in the original BMM created by XPS to tell bitgen the complete path to the BRAMs. XPS also creates an example top-level-VHDL-file that is supposed to show you how to declare and instantiate the module with the MicroBlaze in it (something like "system_stub.vhd"). When you export to "Project Navigator", a new project is created with system_stub.vhd as the top-level-design file, but neither the UCF nor the BMM are added to the project sources, you have to do that manually (theoretically, ngdbuild should find the BMM automatically, but that never works for me). If you don't add the BMM, it is not updated (you normally get a new BMM like system_bd.bmm WITH the information on the placement, not an updated BMM), and then you get exactly the problems you mentioned. But if you do add the BMM as a source to the project, it still doesn't work quite right: In EDK3.2 the top instance name you enter in the project settings is *NOT* transferred to the VHD-file. I.e. if you do copy&paste from system_stub.vhd, the instance name in your top-level does not match the instance name in the BMM file, hence "ngdbuild" just gives you an error about not being able to find the BRAMs and aborts. Same should apply if you do it with schematics. So, this might help you: a) add the BMM as a source to your project in Project Navigator b) make sure the instance name for the module with the MicroBlaze matches the name you specified in EDK before exporting. I've never worked with schematics, but I'm sure you can specify the instance name when you add a component. What you should get in the end is not an updated BMM, but instead a completely new one with "_bd" appended to the name, and that is the one you have to import in XPS. cu, SeanArticle: 68931
Hi, I have used an Aldec's Active-HDL software to change code to machine. The name of the module is Code2Graphics. Similar to Kevin I never got result where code after conversion looked like the one before. In your case it is possible to use the tool to document only. Very user friendy software Regards Jacek "Bert" <_wegvoorspam_lmaarsen@xs4all.nl> wrote in message news:40804f32$0$562$e4fe514c@news.xs4all.nl... > > "Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message > news:2pVfc.151171$w54.1057538@attbi_s01... > > I tried a few of those tools that allow you to draw state machines and > then > > generate the code, but I never liked the code they generated and I don't > > like having "source for the source". So you can use them just for > > documentation, but then you have the problem that the document always > > differs from the actual code when you make a change. I normally just do > > what you do, which is to have a "hand-written mess" before I code the > > machine. I guess I'd recommend using the Mentor tool or something similar > > to make a picture for the customer to see, but not necessarily for code > > generation. If there were a tool that could load in a state machine and > > print it graphically, this would be ideal. Synplicity's synthesizer does > do > > this for state machines it extracts, but the graphical version isn't > really > > pretty enough to show to managers. -Kevin > > > > For state machines we use Ease, a tool for graphical FPGA design > entry. It includes also a nice manner to draw state macines. The output > is used in our company as the documentation. > > I agree that the generated code is never as you wish it should be, > but I am not very unhappy with it. But to be honest only for very > complex state machines I will use this tool, for all other state machines > I write my own VHDL and provide a state machine drawing in our > hardware documentation. > > The time I need to draw the machine, set al the conditions and actions > is mostly just a little bit less than writing the case statement by > yourself. > > Bert > >Article: 68932
If you want low cost than you want to go with the TQFP package. You can't socket it easily but that may not be an issue since you can use ISP. BTW, I wouldn't consider PLCC84 small.Article: 68933
Dave Vanden Bout <devb@xess.com> wrote in message > A 4-input truth-table can be represented by a 16-node hypercube. You can > select 8 nodes of the 16 such that none of these selected nodes are > adjacent. Each of these nodes represents a 4-input minterm and since > they are non-adjacent there is no possibility of combining minterms. A Dave Vanden Bout <devb@xess.com> wrote in message news:<Xns94D253766843Fdevbxesscorp@24.25.9.41>... > hmurray@suespammers.org (Hal Murray) wrote in > news:108c3g94o54ek1a@corp.supernews.com: > > >>F(A,B,C,D) = /A*B*C*D + A*/B*C*D + A*B*/C*D + /A*/B*/C*D + > >> A*B*C*/D + /A*/B*C*/D + /A*B*/C*/D + A*/B*/C*/D > >> > >>If you allow some of the outputs of the 2-input AND gates to be shared > >>across minterms, then you can cut 8 AND gates and get down to 23 2-input > >>gates. > > > > That looks like odd parity, aka an XOR tree. If Peter's claim > > of a (2 input?) XOR counting as 4 NANDs, then we can built it in > > 2 layers using 12 gates rather than 23. Did I miss something? > > I agree with you on that. There must be more resource sharing that allows > you to reduce the 23 gates down to 12. The hypercube reasoning is fascinating. I think what it missed is that XOR allows you to combine non-adjacent nodes (ie 10 is not adjacent to 01). My two cents, -rajeev-Article: 68934
On Wed, 21 Apr 2004 23:47:45 +0200, Maciej Witaszek <nospam_mwitasze@elka.pw.edu.pl> wrote: >where did you find "minimal_sdram_32"? I coudn't find it in Quartus 3.0 and >4.0 both Web Edition and in NIOS dev kit. I'm working now on my own design >so it's posibble that I mixed up a wiring. Strange, but it disappeared in Nios 3.10 I can send it from older versions, but you must contact me on priv (watch out for anti-spam mail). That design was working, because I was in need of having huge data buffer. >> PS: To juz taki czas, ze rodacy szukaja pomocy za granica? :-) >PS. Milo, ze w Polsce tez sie ktos tym zajmuje :) A milo sie dowiedziec, bo myslalem ze nikt tego u nas nie uzywa... -- JerryArticle: 68935
DLLs have advantages over PLLs, and PLLs have advantages over DLLs. It is unfortunate that the battle betwen Xilinx and Altera has polarized this more subtle topic. But things are not all black and white: I managed to feed 6 ns jitter into a Xilinx DCM and see 140 picoseconds jitter on its output. Took some secret sauce, though. Stay tuned. Peter Alfke > > The input jitter filtering you describe above is backwards. PLLs > filter input jitter -- high-frequency jitter is attentuated, although > sufficiently low frequency input jitter is passed through. DLLs pass > input jitter straight through. It's a fundamental property of how > they work -- PLLs are synthesizing the clock from an oscillator that > won't drift fast enough to follow high-frequency input jitter. DLLs > are constructing a clock that is a delayed / digitally multiplied / > divided version of the input clock. So all input jitter gets copied > to the output. > > Regards, > > Vaughn > AlteraArticle: 68936
Dear All, I'm just about to purchase Xilinx ISE BaseX plus MXE for 1,295 USD. Having downloaded the free edition I have to say I'm less than impressed with the general user friendliness - no keyboard shortcuts, no code completion, etc. Is it the case that in terms of commercial tools chains ISE plus Modelsim is the only thing in the market under $2,000? It would be great to hear from any other Xilinx developer's that have found an alternative under 2,000 USD. Thanks, Andy.Article: 68937
And of course, any engineer worth his salt codes a little differently when targetting an FPGA as opposed to targetting an ASIC. An experienced designer knows the structure of the FPGA and tries to ensure the design fits it well. An ASIC designer has a different set of library components on offer to the designer. This means a comparison between FPGA LUT/FF/BRAM/MULT counts and ASIC gate counts has little value. IMO, Syms. "john jakson" <johnjakson@yahoo.com> wrote in message news:adb3971c.0404211711.56b41350@posting.google.com... > For most of my FPGA XST synth reports I look at the bigger functions > it finds, ie adders, Dflops, muxes etc and convert them directly into > their equiv ASIC by looking at the lib relative areas. Most of my > logic doesn't produce alot of those funny 4-8 functions that can't be > easily described or compared, its the memories, muxes, flops, adders > (maybe multipliers) that dominate. >Article: 68938
What about human speech? (Sometimes I wish XON/XOFF worked with the missus!) Are brains synchronous? I wish mine was, maybe then it would work a little more reliably... cheers, Syms. "Simon Peacock" <nowhere@to.be.found> wrote in message news:408771b3@news.actrix.gen.nz... > is a UART. All comms is synchronous or synchronised. (unless its simply on > and off!) > > Simon >Article: 68939
Hi all, I am looking for someone who got experience in: 1. local bus to ide interface 2. local bus to cf+ interface 3. fpga We have a project and we are looking for freelance or contractor. Location: Hong Kong EricArticle: 68940
Our new Broaddown2 board is PCI based but is capable of stand alone operation. Production boards should be available to customer around the end of June. Full details of this board will appear on our website at official launch in 3 weeks time. If you would like some more details in advance please contact me offline. General contact details are available on our website. We can also produce custom derivative boards from this design in 4-6 weeks to your requirements should the standard board not satisfy. -- John Adair Enterpoint Ltd. http://www.enterpoint.co.uk This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "brif" <b.ford@lboro.ac.uk> wrote in message news:c6638f$64s$1@sun-cc204.lut.ac.uk... > Hi everybody, > > I'm currently working on a demonstration project of a lightweight vehicle. > We would like to include a large FPGA to do some control and signal > processing. This would ideally be a totally contained development board, > that could be wired into some kind of bus. (Avoiding using a heavy > backplane) Or a dual processing system with a conventional processor and > FPGA on the same embedded card. > > Unfortunately we're trouble identifiying a suitable device. There appears to > be many PCI/VME ready devices, but few that can be used standalone (Attached > to just communications and power!) > > Does anybody know if there are suitable devices commercialy available? Could > you point me in the right direction please? > > Also is there any information available on similar projects. (Where an FPGA > has been used as the controler for a vehicle) > >Article: 68941
shashi22k@rediffmail.com (Shashi) wrote in message news:<7cdabebf.0404201535.de4bbe8@posting.google.com>... > Hi, > I'm doing a project in clockless uart..as u know that the primary > function of uart is parallel to serial conversion while transmitting > and serial to paralel conversion while receiving..I was wondering if > someone could tell me as how can i do a parallel to serial conversion > and vice versa without using a clock. > > Thank You > SHASHI Say... Do you mean an "asynchronous" UART? You *do* have a system clock available to the FPGA, right? Something in the MHz range?Article: 68942
All, Xilinx uses PLLs (in the MGTs). There is no battle here. DLLs are good, PLLs are good. Choose what you need. Austin Peter Alfke wrote: > DLLs have advantages over PLLs, and PLLs have advantages over DLLs. It is > unfortunate that the battle betwen Xilinx and Altera has polarized this more > subtle topic. > But things are not all black and white: > I managed to feed 6 ns jitter into a Xilinx DCM and see 140 picoseconds > jitter on its output. Took some secret sauce, though. Stay tuned. > Peter Alfke > > >>The input jitter filtering you describe above is backwards. PLLs >>filter input jitter -- high-frequency jitter is attentuated, although >>sufficiently low frequency input jitter is passed through. DLLs pass >>input jitter straight through. It's a fundamental property of how >>they work -- PLLs are synthesizing the clock from an oscillator that >>won't drift fast enough to follow high-frequency input jitter. DLLs >>are constructing a clock that is a delayed / digitally multiplied / >>divided version of the input clock. So all input jitter gets copied >>to the output. >> >>Regards, >> >>Vaughn >>Altera > >Article: 68943
"arkaitz" <arkagaz@yahoo.com> escribió en el mensaje news:c1408b8c.0404212258.1d6531ef@posting.google.com... > Hi Andy, > > > I re-iterate again: Ask yourself: "What happens when both set and > > reset are simultaneously > > asserted?" You may have a problem here. > > > > Does your simulation drive both set and reset at the same time? > > > No, firstly is driven the set signal and later (after some clk periods > the reset signal). I now what I am doing when writing like this; in my > design the reset has more priority than the set signal. > > Thanks, > > Arkaitz. in that case wouldnt be the reset "if" before the set "if"?Article: 68944
Hi there, I tried to connect my LPT1 with a digilab 2e board by using a parallel 4 cable (JTAG). I startet IMPACT and the automatically boundary scan. But I'm always received this message: Connecting to cable (Parallel Port - LPT1). Checking cable driver. Driver windrvr.sys version = 5.0.5.1. Installing WinDriver... Failed. Service using windrvr.sys : SYSTEMCurrentControlSetServicesWinDriver. ImagePath = SystemRootSystem32driverswindrvr.sys. DisplayName = WinDriver. Start = 2. ErrorControl = 1. Type=1. Cable connection failed. Connecting to cable (Parallel Port - LPT2). Checking cable driver. Driver windrvr.sys version = 5.0.5.1. Installing WinDriver... Failed. Service using windrvr.sys : SYSTEMCurrentControlSetServicesWinDriver. ImagePath = SystemRootSystem32driverswindrvr.sys. DisplayName = WinDriver. Start = 2. ErrorControl = 1. Type=1. Cable connection failed. Connecting to cable (Parallel Port - LPT3). Checking cable driver. Driver windrvr.sys version = 5.0.5.1. Installing WinDriver... Failed. Service using windrvr.sys : SYSTEMCurrentControlSetServicesWinDriver. ImagePath = SystemRootSystem32driverswindrvr.sys. DisplayName = WinDriver. Start = 2. ErrorControl = 1. Type=1. Cable connection failed. Connecting to cable (Parallel Port - LPT4). Checking cable driver. Driver windrvr.sys version = 5.0.5.1. Installing WinDriver... Failed. Service using windrvr.sys : SYSTEMCurrentControlSetServicesWinDriver. ImagePath = SystemRootSystem32driverswindrvr.sys. DisplayName = WinDriver. Start = 2. ErrorControl = 1. Type=1. Cable connection failed. Connecting to cable (COM1 Port). Cable connection failed. Cable connection failed. Cable connection failed. Cable connection failed. CB_PROGRESS_END - End Operation. Elapsed time = 28 sec. Cable autodetection failed. GUI --- Switch to File Mode I tried to use the same cable with a laptop and it works. I checked my LPT1 Port with a printer and the port works ok. The Port in the Bios is set to ECP. The drivers "windrvr.sys" and "xpc4drvr.sys" are in the system32/driver directory. I checked the fliset.txt and install.log, both are ok. I installed Xilinx 6.1.03i again. I installed the sevicepack 4. Between the installing were some error messages. The software can't copy some files. I'm using a PC from DELL with windows2000. I don't know what i can do now, please help me. DanielArticle: 68945
Austin Lesea wrote: > All, > > Xilinx uses PLLs (in the MGTs). > > There is no battle here. DLLs are good, PLLs are good. Choose what > you need. Briefly, how do the specialized jitter reduction PLLs from ICS and others achieve their performance? Just wondering.Article: 68946
"eric" <eric3322@hotmail.com> wrote in news:4087f658$1_1@rain.i-
cable.com:
> Hi all,
>
> I am looking for someone who got experience in:
>
> 1. local bus to ide interface
> 2. local bus to cf+ interface
> 3. fpga
>
> We have a project and we are looking for freelance or contractor.
> Location: Hong Kong
>
> Eric
>
We aren't contractors, but we just released an ATAPI core for our XSB-
300E Board that allows the FPGA to interface to an IDE disk or a Compact
Flash in True-IDE mode. The core interface documentation is here:
http://www.xess.com/appnotes/an-041404-atacntl.pdf
but the operational details are in the VHDL files for the project:
http://www.xess.com/projects/xsbatacntl.zip
That might give you a point to start from.
--
|| Dr. Dave Van den Bout XESS Corp. (919) 363-4695 ||
|| devb@xess.com PO Box 33091 ||
|| http://www.xess.com Raleigh NC 27636 USA FAX:(919) 367-2946 ||
Article: 68947You start with a high-Q voltage-controlled oscillator. LC is much better than RC, but LC limits the range for pulling the frequency significantly (square root of C, vs linear with C for the RC case). Then you need some counters plus a good phase detector and a low-pass filter in its control input, so that you do not affect the oscillator with short-lived disturbances, but make it still follow the average frequency. And you decouple your Vcc and keep the ground stable. Really simple, just a bunch of engineering trade-offs. Peter Alfke > From: "Tim" <tim@rockylogic.com.nooospam.com> > Newsgroups: comp.arch.fpga > Date: Thu, 22 Apr 2004 19:48:43 +0100 > Subject: Re: PLL and DLL > > Austin Lesea wrote: >> All, >> >> Xilinx uses PLLs (in the MGTs). >> >> There is no battle here. DLLs are good, PLLs are good. Choose what >> you need. > > Briefly, how do the specialized jitter reduction PLLs from ICS and > others achieve their performance? Just wondering. > >Article: 68948
Thank Jim Wu first. I am not a system administrator. The system administrator for our system is not nice. So before I ask her, I want to make sure everything and I only want to talk with her once (not many times):-( The readme.txt is as follows, This zip file contains the design files for the ISE 4 Indepth tutorial. ----------------------------------------------------------------------- Installation instructions -------------------------- Unzip the file into the $XILINX install directory. Documentation ------------- Refer to the ISE 4 indepth tutorial available at: http://support.xilinx.com/support/techsup/tutorials/index.htm Just unzip it?That is enough? Do I need to do specific things to compile the library?Or this tcl file can compile the library online when ModelSim is started? So far, only verilog files are on the library directory of Xilinx of our system. ModelSim required "_info" file and some directories for these verilog files. Is everything is done by that TCL file automatically or I should compile it first?Thank a lot. "Jim Wu" <NOSPAM@NOSPAM.com> wrote in message news:<jCFhc.16669$2v.16508@nwrdny02.gnilink.net>... > Read the readme.txt file that comes with the script! > > Jim > jimwu88NOOOSPAM@yahoo.com > http://www.geocities.com/jimwu88/chips > > "Lee" <yxl4444@louisiana.edu> wrote in message > news:5c3c88bc.0404211512.66c6020d@posting.google.com... > > I have read the solution #2561 about how to compile librarie for > > modelsim. I download the tcl script file, but I don't know how to use > > it. Can anybody tell me?ThanksArticle: 68949
Jim Wu told me to read readme file. But I still have some questions. Refer to previour messages. Thansk, yxl4444@louisiana.edu (Lee) wrote in message news:<5c3c88bc.0404211913.46cccadd@posting.google.com>... > I am a beginner, don't know how to use the tcl file. Stupid enough:-(
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