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Austin Lesea wrote: > Jacek, > > Yes we have FPGAs that have been used in railway equipment. > > The problem is the sometimes close to ten year qualification process* > for railway equipment, which means by the time it is qualified for use, > the parts are well into their obsolesence. > <snip> > For example, we heard that a manufacturer wants to use an FPGA in a > nuclear reactor control system. That certainly gets our attention, as > we insisted that the design be done in such a way that is consistent > with the application (ie fully TMR, dual redundant, hot standby, etc etc > etc). Errrm - won't the neutron/radiation count be just a tad above a sea level average, in a nuclear reactor control system ? And might it not (hypothetically of course) peak somewhat higher, just when it is rather important that said control system is operating ? Did this enquiry perhaps arrive on April 1st ? -jgArticle: 69001
Hi, Is it possible to generate multiply by 1.5 clock in xilinx virtex2 fpgas using DCMs? Regards GanesanArticle: 69002
"Ganesan" <ganesancp@yahoo.co.in> wrote in message news:2c529f55.0404240106.129a1862@posting.google.com... > Hi, > > Is it possible to generate multiply by 1.5 clock in xilinx virtex2 fpgas using DCMs? > > Regards > Ganesan It sure is! The CLKFX_MULTIPLY/CLKFX_DIVIDE ratio is chosen as 3/2. As long as the input is at least 1 MHz and the output is within the Max frequency spec, you're set. Check the Functional data sheet for a description of the DFS mode and the DC & Switching data sheet for the DCM's DFS mode input and output frequency constraints.Article: 69003
hi, i have been trying to download a design on this board (AFX bg560 - 100), but keep getting the error that "INIT pin does not go high". I even tried to download the sample example but it still doesnt work . Please please let me know how i can resolve this..would it possibly be a problm with the board. Thanks, zincArticle: 69004
Hi, group: I am running core generator to make some dual port RAMs. However my design involves partial reconfiguration, I need to put some LOC constraint on the instantiated DPRAMs, or at least find a way to confine the instance within an area group of their instantiator...How may I do that? KelvinArticle: 69005
BTW, I am using Virtex-2 3000...and ISE6.1... Thanks. Kelvin "Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message news:c6ffap$4qr$1@reader01.singnet.com.sg... > Hi, group: > > I am running core generator to make some dual port RAMs. However my design > involves partial reconfiguration, I need to put some LOC constraint on the > instantiated > DPRAMs, or at least find a way to confine the instance within an area group > of their > instantiator...How may I do that? > > Kelvin > > >Article: 69006
I have made an output device that attaches to older 8 bit computers. The MSB of the address bus goes though some gates and the select clocks a 74273 d type flipflop. The LSB goes into the inputs of the 273. It works great as ttl chips. I've installed the xilinx webpack and am using the schematic entry and it looks very simple to implement. I'm using the FD flipflop since I don't use the clear. Unfortunately it doesn't work. I've run the clock to an output pin and connected a 74hct273 in parallel to verify everything else and the ttl chip works correctly every time. The output of the 9536 seems to be more of a random number generator. The modelsim looks like what I would expect. Is it possible the clock on the flip flop is occuring before all the address pins get settled? I'm new to CPLDs am I missing something obvious? I've played with this for a couple of days now. One interesting thing I did find. I inserted a nand gate in the clock line followed by an inverter. I branched the ouput of the nand back around into the other input of the nand. I assume this would cause the clock signal to oscillate while the decoders selected the flip flop. What's interesting is this causes the flip flop to clock all 8 bits correctly better than half the time. I'm sure that would tell me something if I knew what I was doing. :) Any help would be appreciated, thanks.Article: 69007
On Wed, 21 Apr 2004 16:16:30 +0100, "brif" <b.ford@lboro.ac.uk> wrote: >Hi everybody, > >I'm currently working on a demonstration project of a lightweight vehicle. >We would like to include a large FPGA to do some control and signal >processing. This would ideally be a totally contained development board, >that could be wired into some kind of bus. (Avoiding using a heavy >backplane) Or a dual processing system with a conventional processor and >FPGA on the same embedded card. A fairly complete list of available boards is at: http://www.fpga-faq.com/FPGA_Boards.shtml =================== Philip Freidin philip.freidin@fpga-faq.com Host for WWW.FPGA-FAQ.COMArticle: 69008
I'm looking a microcontroller with the following properties: - Includes a USB port interface, which is used for programming all functions (ideal case). Alternatively, initial function programming could be via JTAG, but once programmed the device must support USB. - Program should be flash-based. EZUSB requires initial program load via USB whenever the device is re-attached to the USB host. I wish to program device functionality once, and this program should be retained when the device is detached from USB. - CPLD (or FPGA with non-volatile program storage / autoload (autoload could be performed by microcontroller)) to support reconfigurable hardware functions. Anyone know of such a device? Thanks, R. Main.Article: 69009
D Widel wrote: > I have made an output device that attaches to older 8 bit computers. > The MSB of the address bus goes though some gates and the select > clocks a 74273 d type flipflop. The LSB goes into the inputs of the > 273. It works great as ttl chips. I've installed the xilinx webpack > and am using the schematic entry and it looks very simple to > implement. I'm using the FD flipflop since I don't use the clear. > Unfortunately it doesn't work. I've run the clock to an output pin > and connected a 74hct273 in parallel to verify everything else and the > ttl chip works correctly every time. The output of the 9536 seems to > be more of a random number generator. > > The modelsim looks like what I would expect. Is it possible the clock > on the flip flop is occuring before all the address pins get settled? > I'm new to CPLDs am I missing something obvious? > > I've played with this for a couple of days now. One interesting thing > I did find. I inserted a nand gate in the clock line followed by an > inverter. I branched the ouput of the nand back around into the other > input of the nand. I assume this would cause the clock signal to > oscillate while the decoders selected the flip flop. What's > interesting is this causes the flip flop to clock all 8 bits correctly > better than half the time. I'm sure that would tell me something if I > knew what I was doing. :) Only that the patient is sick... > > Any help would be appreciated, thanks. Go to the fitter .RPT file, and see the equations created - they show what actually ended up in the device. -jgArticle: 69010
Yes, we have recently designed and produced here in Catalonia some 192x64 LED displays with 16 gray levels EN 50155 compliant for the TGV Barcelona-Madrid. Those displays have a Xilinx XCS05 industrial grade as a coprocessor. Regards Narcis Nadal "Jacek Mocki" <jacekmocki@poczta.onet.pl> escribió en el mensaje news:c6anq7$7r$1@news.onet.pl... Does anyone know some examples of using CPLD or FPGA devices in railways equipment? Regards JacekArticle: 69011
Hello all, I am an electrical engineering student and in need of some advice for a project. There is a project that involves emulating a 16 bit microprocessor in an FPGA and I would like to gain some information about where to start. So, here are my questions: 1) Is it actually possible to emulate a microprocessor in an FPGA? 2) If I manage to code it in a way that any output that would have been obtained from the real processor for a given input is obtained from the FPGA, have I done the job? Or are there other considerations that I should be aware of? 3) What size and kind of FPGA chip and developing board is appropriate for this purpose? 4) Can I implement a working RAM and ROM inside the FPGA or should I leave them out? 5) Are there any flash type (if it is the right word) FPGA's that are electrically erasable and reprogrammable but don't lose their content when the power is turned off? 6) I am planning to start learning VHDL in the summer, is it the right tool for the purpose? 7) Our budget is limited to $500 US max, will I be able to find the right board and chip to finish the project within the budget? I have done some searching in the Internet and have seen some boards that seem to be quite inexpensive, but I wonder if they will do the job. Please forgive my ignorance if the questions seem too naive, I will be taking the relevant courses in the next year. I am just trying to get a head start during the summer by preparing myself. Thanks for any suggestions. JPArticle: 69012
Hello everybody, I was planning to get into fpgas/cplds but don't really want do buy an expensive starterkit. As an older post indicated altera has published the schematics of their byteblaster download cable. However it was not listed on the site and a google link www.altera.com/literature/ds/dsbyte.pdf only gives a file not found error. Does anybody of you have the file (dsbyte.pdf) and could send it to me, or point me to an alternative download location. Your help is appreciated, Florian StudentArticle: 69013
JP@noemail.com wrote: >So, here are my questions: >1) Is it actually possible to emulate a microprocessor in an >FPGA? Sure. >2) If I manage to code it in a way that any output that would >have been obtained from the real processor for a given input is >obtained from the FPGA, have I done the job? Or are there other >considerations that I should be aware of? Design goals: Clock rate, clock ticks per instruction, size of design, IO. Verification goals: Code coverage, logic coverage, static timing coverage. Documentation: What does it do? How does it do it? >3) What size and kind of FPGA chip and developing board is >appropriate for this purpose? Which microprocessor? A carefully designed and optimized for FPGA 16 bit processor will fit in a quarter or less of a small modern FPGA. A full emulation of a P-4 is probably several large FPGAs plus external RAM for the caches. >4) Can I implement a working RAM and ROM inside the FPGA or >should I leave them out? www.xilinx.com www.altera.com www.actel.com >5) Are there any flash type (if it is the right word) FPGA's that >are electrically erasable and reprogrammable but don't lose their >content when the power is turned off? Yes, actel sells one. >6) I am planning to start learning VHDL in the summer, is it the >right tool for the purpose? VHDL is a good tool. I use it. A widely used alternative is Verilog. While Verilog isn't quite as good as VHDL, it works. (~/~) >7) Our budget is limited to $500 US max, will I be able to find >the right board and chip to finish the project within the budget? I >have done some searching in the Internet and have seen some boards >that seem to be quite inexpensive, but I wonder if they will do the >job. Why don't you download the free tools targeting the FPGA on one of these boards and try to build a design that fits into that FPGA? >Please forgive my ignorance if the questions seem too naive, I will be >taking the relevant courses in the next year. I am just trying to get >a head start during the summer by preparing myself. Have fun. -- Phil Hays Phil_hays at posting domain should work for emailArticle: 69014
Tommy Thorn <TommyAtNumba-Tu.Com--not@yahoo.com> wrote in message news:<WCcic.7764$Fo4.96400@typhoon.sonic.net>... > Emacs + Icarus Verilog + Quartus II does the trick for me quite nicely > and all is for free. > > The _only_ thing I miss from the paid-for Quartus is the FPGA Editor and > more device support. I spend 95% of the time in Emacs and Icarus > Verilog, so I don't care much about the remaining 5% as long as it works > (and Quartus II is very stable). When I used Xilinx WebPACK I even had > scripted the P&R and programming tools so I would never leave Emacs. I > have yet to take the time to figure out how to do that with Quartus. > > I'm curious, what are you really expecting better for your $2k? A > better editor? > > Tommy > Thanks for all your replies. Tommy - I should have mentioned that I'm from a Java background, so moving from my favourite IDE, IntelliJ's IDEA, to Xilinx's editor I instantly missed features like code completion. However, as was pointed out, HDL design entry will perhaps only consume a small percentage of total development time, and so editor features are perhaps less important than in a high level language IDE. As there seems to be abundant alternatives to the in built editor, I'm not going to worry about it too much. Nial - Thanks for the recommendation, I'll check out Symphony EDA. You're right about the Modelsim price, I spoke to a distributor who mentioned circa 3,000 UKP for PE edition, however I was hoping to get away with the XE edition for the moment and use <1M gate devices. Thanks, Andy.Article: 69015
Kelvin, Use the floorplanner to find the name of your blockram after the translate stage. Then add a LOC constraint in your UCF file. Read the 'Xilinx constraints guide' to find out about the syntax, something like INST "RTFM_BRAM" LOC = X0Y0; HTH, Syms.Article: 69016
Florian Student wrote > www.altera.com/literature/ds/dsbyte.pdf only gives a file not found error. see page 4 of http://www.altera.com/literature/ds/dsbytemv.pdf -- Mike TreselerArticle: 69017
Mike Treseler wrote: > Florian Student wrote > >>www.altera.com/literature/ds/dsbyte.pdf only gives a file not found error. > > > see page 4 of > http://www.altera.com/literature/ds/dsbytemv.pdf The only change to the MV is the replaacement of the LS244 with a HC244 to make it work also at 3.3V. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 69018
JP@noemail.com wrote in message news:<o1be80trst70j4obop4bosoi0meub5cubh@4ax.com>... > Hello all, > > I am an electrical engineering student and in need of some advice for > a project. There is a project that involves emulating a 16 bit > microprocessor in an FPGA and I would like to gain some information > about where to start. > So, here are my questions: > 1) Is it actually possible to emulate a microprocessor in an > FPGA? > A get ahead of the crowd, student, I like that. As Phil says, it is definitely doable but will take some serious effort. > 2) If I manage to code it in a way that any output that would > have been obtained from the real processor for a given input is > obtained from the FPGA, have I done the job? Or are there other > considerations that I should be aware of? > Well for a student project you may not have to worry about every single detail that may be irelevant to the main project. Get the instruction set architecture (ISA) that you are going to do and define a good practical subset of it, one that can run most test programs you may compile for the real cpu. If your test programs are in asm, you will be able to compare the real & emulated cpu instruction by instruction. Try to avoid getting into complex ISA features, limit address modes to the most basic. You didn't say if you have one, but if I had to pick one, I would pick a cpu which existed some while back and has SW tools and was already implimented with relatively little logic. If you are emulating a recent cpu architecture it may be relatively bloated already and a much harder to replicate. My all time favourite "old" and "simple" 16 bit cpu would be the Texas Instruments 9900, followed closely by the PDP11. The 9900 has its registers in memory so you only need to build quite a no of state machines to fetch and decode ops and fetch and modify operands to memory. The PDP11 is much nicer and has far more SW thats may still be around in your lab or museum but is a level up in difficulty. Most of the old 1st gen mos cpus were heavily inspired by the PDP11, but stripped it down in radically different ways to get differing results, 6502,6800,8080 all draw from it but all were 8b. The 68k would be the 1st mos cpu to surpass the PDP11 in elegance but would be far beyond your reach, it did take Moto 200 man years to do that full custom. If you are driven to do a RISC design, then its a different game since RISC is usually chosen for 32b & up cpus. But RISC can be used for 16b too, many original ISAs for FPGA are naturally RISC and heavily pipelined which FPGAs can be good at. Check out fpgacpu.org or google for FPGA cpu da da da. Also you could take a look at commercial cpu cores that are available far beyond your reach but will indicate what can be done for how many FPGA cells. Another option is to look at SW emulators to use as your reference. If you can run the xyz cpu in SW emulation on a PC, you can probably inspect its internal ISA states quite easily op by op to see changing reg,memory values, pc,sp etc, but there won't be any real internal cpu state since SW emulators are not detailing the ISA internals. There may be SW emulators around for most cpus that were really popular. > 3) What size and kind of FPGA chip and developing board is > appropriate for this purpose? > For Xilinx choose a small Spartan2 100 or 200 board and for Altera a comparable cyclone board. Boards can start as little as $100 and up to $1k for really fancy. Some of these boards come with example code for small cpus too. Check out the boards lists at http://www.fpga-faq.com/FPGA_Boards.shtml but Xess, BurchED, APS, Digilent, Trenz, FPGA4fun, CMOSexod (a friend of mine) come to mind. Your EE lab may well tell/give you the board. If a vendor has high end boards, they probably aren't the right low end vendor for you. Many of these boards will have an external SRAM or DRAM onboard for bulk >>1Mb ram, but for 1st effort, the internal blockram should suffice. Your design tools are free for this size of project, Webpack, Quartas. Don't use a really old FPGA older than say 2-3yrs, it won't have such good resources or tools. You might expect to target a cycle time in the range of 20-50MHz depending on RISCness. > 4) Can I implement a working RAM and ROM inside the FPGA or > should I leave them out? > Most every modern FPGA has more than enough blockram to hold a workeable working store and register file. Smallest spartan2 has about 14? 4k.1 rams which can be made tall & thin or short & fat. The old PDP8s only had a max of 4k.12 core and were perfectly good (but 12b). If DEC,DG and so on had had FPGAs 30yrs ago, they could have easily put the whole cpu in one small FPGA. ] > 5) Are there any flash type (if it is the right word) FPGA's that > are electrically erasable and reprogrammable but don't lose their > content when the power is turned off? > Most sram FPGA boards will boot from external flash device or a usb/serial/whatever connection to PC. > 6) I am planning to start learning VHDL in the summer, is it the > right tool for the purpose? > In most schools that would be a given, although some of us prefer Verilog coming from a Asic background. Also consider using C/C++ as your 1st working functional model which can be used to provide vectors to the hdl simulators. Esp so if you are using a SW emulator as your reference. > 7) Our budget is limited to $500 US max, will I be able to find > the right board and chip to finish the project within the budget? I > have done some searching in the Internet and have seen some boards > that seem to be quite inexpensive, but I wonder if they will do the > job. > As we have said, any of the smallest Spartan2/Cyclones can hold a small cpu and some spare change as long as you forget about FPUs, MMU, cache, and so on. > Please forgive my ignorance if the questions seem too naive, I will be > taking the relevant courses in the next year. I am just trying to get > a head start during the summer by preparing myself. > > Thanks for any suggestions. > > JP You'r welcome johnjakson_usa_comArticle: 69019
I just came across this schematic for the ByteBlaster II: http://www.mcu.cz/atm/index.php?direction=0&order=&directory=EDA Someone has probably worked out the circuit by tracing the connections on a unit as Altera hasn't published it, AFAIK. Leon -- Leon Heller, G1HSM http://www.geocities.com/leon_hellerArticle: 69020
"Narcis Nadal" <nnadal@terra.es> wrote in message news:<unLic.4700406$uj6.16108118@telenews.teleline.es>... > Yes, we have recently designed and produced here in Catalonia some 192x64 > LED displays with 16 gray levels EN 50155 compliant for the TGV > Barcelona-Madrid. Those displays have a Xilinx XCS05 industrial grade as a > coprocessor. > > Regards > > Narcis Nadal > "Jacek Mocki" <jacekmocki@poczta.onet.pl> escribió en el mensaje > news:c6anq7$7r$1@news.onet.pl... > Does anyone know some examples of using CPLD or FPGA devices in railways > equipment? > > Regards > > Jacek This reminds me, in the UK 80s, BR wanted to run high speed service with trains that tilted into the curve as speed required for the ever so old curvy track they didn't want to replace. I remember the tilted trains coming out of the curves locked up and lurching into the opposing track causing much embarrassment to their EEs. What was the outcome, did they get it to work or did they settle for slow trains as usual? This was ofcourse way before FPGA, I expect the controller was TTL+8080s. regards johnjakson_usa_comArticle: 69021
Does a CPLD Input source current ? When I measure the voltage at my CPLD input pin, it is somewhere in the 3V range. When I connect it to ground, it sources about 50 mA. Is that normal ? I thought an input should not behave like this ..!?Article: 69022
Hello all,
I am trying to get XST (ISE 6.1) to infer a dynamic shift register
implemented using Virtex II LUTS. I have used the VHDL model shown
below.
However XST does not use LUTS, instead flip-flops are used. When I
change the line srout <= sr(n) where n is a static value XST manages
to use LUTS for the shift register. Can anybody please tell me what I
am doing wrong. This is the same code as given in XST Synthesis ans
Verification guide.
Thanks
Josh
entity addressablesr is
generic(Depth_g : natural := 96);
port(ck : in std_logic;
en : in std_logic;
srin : in std_logic;
addr : in integer range 95 downto 0;
srout : out std_logic);
end entity;
architecture behaviour of addressablesr is
signal sr : std_logic_vector(Depth_g-1 downto 0);
begin
process(ck,srin)
begin
if (ck'event and ck = '1') then
if en = '1' then
sr <= sr(Depth_g-2 downto 0) & srin;
end if;
end if;
end process;
srout <= sr(addr);
end architecture;
Article: 69023Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> writes: > lbroto <lbroto_ARONDBAS_@free.fr> wrote: > > : I'm lookink for a quartus web edition for Linux. > > [...] > > I'd wish they would use wine and talk to Codeweavers/WineX about > maintanance. Their software mostly works already with wine used as an > emulator... Does anyone have experience with running the Quartus Web Edition on Linux? We are considering making a hobbyist FPGA board, and we are considering both Xilinx and Altera, but the design software will need to be gratis and run on GNU/Linux. I have the Xilinx WebPACK running on GNU/Linux using Wine (command line only but that's enough), but I have found no information yet on doing the same with Quartus. I think I'll just try to get it running... -- GPG: D5D4E405 - 2F9B BCCC 8527 692A 04E3 331E FAF8 226A D5D4 E405Article: 69024
If you are doing jtag can't you use the xilinx cable design. Steve "Rene Tschaggelar" <none@none.net> wrote in message news:408c21a8$0$708$5402220f@news.sunrise.ch... > Mike Treseler wrote: > > > Florian Student wrote > > > >>www.altera.com/literature/ds/dsbyte.pdf only gives a file not found error. > > > > > > see page 4 of > > http://www.altera.com/literature/ds/dsbytemv.pdf > > > The only change to the MV is the replaacement of the LS244 with a HC244 > to make it work also at 3.3V. > > Rene > -- > Ing.Buero R.Tschaggelar - http://www.ibrtses.com > & commercial newsgroups - http://www.talkto.net
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