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I would call that self-synchronizing, not self-clocking. Manchester code is self-clocking, provided you get it going "on the right foot". Peter Alfke > From: "Simon Peacock" <nowhere@to.be.found> > Organization: TelstraClear > Newsgroups: comp.arch.fpga > Date: Wed, 21 Apr 2004 20:31:28 +1200 > Subject: Re: Issues on Shift Register in a Clockless UART > > it should perhaps be pointed out that UART's aren't in fact clockless.. they > are self clocking... that is the clock is passed with the data (i.e. the > leading edge of the start bit is the re-syncing edge) > > Simon > > > "Peter Alfke" <peter@xilinx.com> wrote in message > news:BCAB2209.5F87%peter@xilinx.com... >> Simple answer: You cannot. You can of course generate your own clock... >> Peter Alfke >> >>> From: shashi22k@rediffmail.com (Shashi) >>> Organization: http://groups.google.com >>> Newsgroups: comp.arch.fpga >>> Date: 20 Apr 2004 16:35:16 -0700 >>> Subject: Issues on Shift Register in a Clockless UART >>> >>> Hi, >>> I'm doing a project in clockless uart..as u know that the primary >>> function of uart is parallel to serial conversion while transmitting >>> and serial to paralel conversion while receiving..I was wondering if >>> someone could tell me as how can i do a parallel to serial conversion >>> and vice versa without using a clock. >>> >>> Thank You >>> SHASHI >> > >Article: 68901
Just to indicate more sources of confusion: A LUT used as a RAM is worth at least 4 gates per bit, plus decoding from 4 inputs to 16 cells. That gets us to ~80 gates. If you use the LUT as a 16-bit shift register with adjustable tap (SRL16), then you are well over a 100 gates per LUT. But I will not tell Marketing... 14 years ago I quipped that gate-count is as meaningless a measure of FPGA capacity, as 36-24-34 is a meaningless measure of female beauty. May not be politically correct these days... Peter Alfke ===================== > From: Dave Vanden Bout <devb@xess.com> > Organization: Road Runner - NC > Newsgroups: comp.arch.fpga > Date: Wed, 21 Apr 2004 12:12:15 GMT > Subject: Re: calculate the number of logic gate in FPGA > > hmurray@suespammers.org (Hal Murray) wrote in > news:108c3g94o54ek1a@corp.supernews.com: > >>> F(A,B,C,D) = /A*B*C*D + A*/B*C*D + A*B*/C*D + /A*/B*/C*D + >>> A*B*C*/D + /A*/B*C*/D + /A*B*/C*/D + A*/B*/C*/D >>> >>> If you allow some of the outputs of the 2-input AND gates to be shared >>> across minterms, then you can cut 8 AND gates and get down to 23 2-input >>> gates. >> >> That looks like odd parity, aka an XOR tree. If Peter's claim >> of a (2 input?) XOR counting as 4 NANDs, then we can built it in >> 2 layers using 12 gates rather than 23. Did I miss something? > > I agree with you on that. There must be more resource sharing that allows > you to reduce the 23 gates down to 12. > > >> >> >> >> I'm assuming NOR and NAND count the same. Is that generally true? >> How do ASIC people count inverters? A whole gate or a partial gate? >> How about AND vs NAND? Do I get a free inverter sometimes? >> > > > > -- > || Dr. Dave Van den Bout XESS Corp. (919) 363-4695 || > || devb@xess.com PO Box 33091 || > || http://www.xess.com Raleigh NC 27636 USA FAX:(919) 367-2946 ||Article: 68902
Check out http://www.stratforddigital.ca/products/sputnik for a stand-alone Spartan IIe board up to 300K. Not sure if this is large enough for your application. As application examples I don't have any of those. >>> brif<b.ford@lboro.ac.uk> 4/21/2004 11:16:30 AM >>> Hi everybody, I'm currently working on a demonstration project of a lightweight vehicle. We would like to include a large FPGA to do some control and signal processing. This would ideally be a totally contained development board, that could be wired into some kind of bus. (Avoiding using a heavy backplane) Or a dual processing system with a conventional processor and FPGA on the same embedded card. Does anybody know if there are suitable devices commercialy available? Could you point me in the right direction please? Also is there any information available on similar projects. (Where an FPGA has been used as the controler for a vehicle)Article: 68903
I wonder how the Mapper computes the gate count in the report file? It makes me laugh reading a practically meaningless number quoted to 7 significant figures! Marketing, bless! Syms. "Peter Alfke" <peter@xilinx.com> wrote in message news:BCABF524.5FA5%peter@xilinx.com... > Just to indicate more sources of confusion: > A LUT used as a RAM is worth at least 4 gates per bit, plus decoding from 4 > inputs to 16 cells. That gets us to ~80 gates. > If you use the LUT as a 16-bit shift register with adjustable tap (SRL16), > then you are well over a 100 gates per LUT. > But I will not tell Marketing... > > 14 years ago I quipped that gate-count is as meaningless a measure of FPGA > capacity, as 36-24-34 is a meaningless measure of female beauty. > May not be politically correct these days... > Peter AlfkeArticle: 68904
rrr@ieee.org (Rajeev) wrote in message news:<c0f37b00.0404210325.6ae94ea0@posting.google.com>... > Jon, > > jon.parker@flextronics.com (Jon Parker) wrote in message news:<a76c9332.0404200716.4f8622f6@posting.google.com>... > > I have a DSP development kit, Stratix Edition. I obtained a license > > for the development kit, using the link: > > > > https://mysupport.altera.com/lic/devKitNic.asp?product=stratix > > > > I received the license, installed it per the instructions. Quartus II > > seems to work OK but when I try to run the Filtering Reference Design > > Lab, exercise 3, and run the Signal Compiler 2.1.3, I get the error > > message "! Unable to check a valid DSP Builder License". I was under > > the impression from the Altera Licensing web link that the DSB Builder > > License was included as a feature of the licensing file. I've > > contacted Altera but so far no response. Does anyone have any > > experience with this problem? Thanks a million. > > > > Jon > > Been there done that. More experience that I could wish for. > > Go to the user guide, UG_DSPBuilder.pdf, and read the section titled > "Error Message: Signal Compiler is Unable to Check a Valid License." > In fact keep the whole troubleshooting section handy, because once > you get past the license hurdle, you're likely to need other portions > of it. > > Now, why would Altera document all these problems instead of fixing > them ? > > And yes there are problems that aren't neatly documented. Bless your > stars if you don't run into them. > > Regards, > -rajeev- Hello Rajeev, Thank you for the answer to my post. Between the time of making the post and receiving your reply, the Altera support team answered my question, and the resolution was as described in "Verifying that the LM_LICENSE_FILE Variable Is Set Correctly" on page 133 of the user's guide UG_DSPBuilder.pdf. I somehow overlooked this section of the user's guide in my attempts to resolve my issue. Thanks again for your help. Others reading this can regard my question resolved, and no further replies are necessary. Thanks to all for reading this. Sincerely, Jon ParkerArticle: 68905
Memec offers a fair number of inexpensive evaluation boards that provide circuit boards with FPGAs with on-board communication interfaces like USB and RS232 and generous expansion connectors. Here's a link to a development kit list and to an example: http://legacy.memec.com/devkits/americas.shtml http://www.insight.na.memec.com/Memec/iplanet/link1/Spartan3LC_3.pdf NPE offers a rather dense controller board that combines a Spartan II FPGA with a PowerPC, many analog inputs, a few analog outputs, can a CAN communications port. Dunno about pricing though: http://www.npe-inc.com/npe565.htmArticle: 68906
Not true. Marketing would have rounded it up to the next million. it takes sofrware geeks to quote vaguely defined values with 7 digit resolution, aka "accuracy". Peter Alfke > From: "Symon" <symon_brewer@hotmail.com> > Newsgroups: comp.arch.fpga > Date: Wed, 21 Apr 2004 10:39:22 -0700 > Subject: Re: calculate the number of logic gate in FPGA > > I wonder how the Mapper computes the gate count in the report file? It makes > me laugh reading a practically meaningless number quoted to 7 significant > figures! > Marketing, bless! > Syms. > "Peter Alfke" <peter@xilinx.com> wrote in message > news:BCABF524.5FA5%peter@xilinx.com... >> Just to indicate more sources of confusion: >> A LUT used as a RAM is worth at least 4 gates per bit, plus decoding from > 4 >> inputs to 16 cells. That gets us to ~80 gates. >> If you use the LUT as a 16-bit shift register with adjustable tap (SRL16), >> then you are well over a 100 gates per LUT. >> But I will not tell Marketing... >> >> 14 years ago I quipped that gate-count is as meaningless a measure of FPGA >> capacity, as 36-24-34 is a meaningless measure of female beauty. >> May not be politically correct these days... >> Peter Alfke > >Article: 68907
arkagaz@yahoo.com (arkaitz) wrote in message news:<c1408b8c.0404202314.7f0c710e@posting.google.com>... > Hi, > > Sorry. Was my fault when typewriting; I also use "elsif" clause in the > second process instead of "if" clause. > > > > Logic looks OK except I would have used elsif clause. I suspect > > that your "input" signal, although synchronous, is external to > > the block you're simulating. > > Yes, the input signal is external to my block, it's a clock divider > output and 3 clock period wide. > > > If so, assert it _in_the_simulation_ > > on a falling clock edge. Think of it this way. Label the rising > > edges T=0,1,2,3. Then if input goes high on clk T=2, it really > > goes high "a little while after" T=2 but well before T=3 (we hope! > > but timing is outside the scope of functional simulation). So > > by asserting it at T=2.5 (ie falling edge) you're telling the > > simulator that "input" was low at T=2 but high at T=3... which is > > (hopefully) what you want. I found it confusing at first but > > got used to it after a while. > > It could be a solution; I'll try it. But I cannot see why doesn't my > design work. I have created another design where the input signal is > an input port instead of an output of an internal register. I have > simulated it functionally changing the input value from 0 to 1 > together with a rising edge of the clock. As in the other case a > glitch is appeared in the functional simulation but now the design > works and the FF is reseted. > > I cannot see why ModelSim works fine with an input port and not with > the output of an internal FF. Back to your code: > I have a FF in my design whose reset and set are separate conditions: > > process( rst, clk ) > begin > if ( rst = '1' ) then > output <= '0'; > elsif ( clk'event and clk = '1' ) then > if ( set = '1' ) then > output <= '1'; > end if; > if ( reset = '1' ) then > output <= '0'; > end if; > end if; > end process; I re-iterate again: Ask yourself: "What happens when both set and reset are simultaneously asserted?" You may have a problem here. Does your simulation drive both set and reset at the same time? --aArticle: 68908
Hi, I looking for a small fpga in plcc84 package to migrate from a XC95108 based design, any ideas? not necessarily from Xilinx... This design is only for educational purpose, so low cost is very important, speed is not a problem.. thanks -- my address to reply: "aticatac70-at-hotmail-dot-com"Article: 68909
"Mario Prato" <see@message.body> wrote in message news:ljAhc.85479$hc5.3600878@news3.tin.it... > Hi, > I looking for a small fpga in plcc84 package to migrate from a XC95108 > based design, any ideas? not necessarily from Xilinx... > This design is only for educational purpose, so low cost is very > important, speed is not a problem.. You should still be able to obtain Xilinx Spartan and SpartanXL chips in PLCC-84 fairly easily. Altera Flex 10K10 is another option which might be better because it is still supported by the current tools, which isn't the case for the Xilinx devices; you'll have to use the older tools. LeonArticle: 68910
On Tue, 20 Apr 2004 00:11:46 +0200, jerry1111 wrote: > I got SODIMM from laptop and compiled some simple design (only with UART > & lcd). Worked from the first time. Board was the one with Apex20KE, > > Have you tried "minimal_sdram_32" from examples directory? Hi jerry1111, where did you find "minimal_sdram_32"? I coudn't find it in Quartus 3.0 and 4.0 both Web Edition and in NIOS dev kit. I'm working now on my own design so it's posibble that I mixed up a wiring. I simulated a cpu with Verilog model of SDRAM from Micron and cpu read instruction from SDRAM. It looked ok. I don't what I'm doing wrong :( Best regards, Maciej > PS: To juz taki czas, ze rodacy szukaja pomocy za granica? :-) PS. Milo, ze w Polsce tez sie ktos tym zajmuje :) -- Maciej Witaszek nospam_mwitaszek@elka.pw.edu.pl remove "nospam_" from my addressArticle: 68911
I have read the solution #2561 about how to compile librarie for modelsim. I download the tcl script file, but I don't know how to use it. Can anybody tell me?ThanksArticle: 68912
Dave, That is an interesting result, but I was actually more interested in seeing the I/O numbers for the benchmarked designs, instead of adding new (arbitrary?) I/O constraints that may not have been part of the original design. If the I/O constraints were not met, then the results become difficult to interpret. The only other question in my mind would be whether the different cost tables were used for the Xilinx implementation. However, if both vendors met the I/O constraints, and different cost tables/settings were used for Xilinx (as was done for Altera with DSE) then I agree that the benchmarking is reasonable and there is some validity to them. SD davidg@altera.com (Dave Greenfield) wrote in message news:<5c156a0b.0404191200.408126fc@posting.google.com>... > SD, > 1. To respond to your concerns, our benchmarking team ran a second set > of experiments to compare Stratix to Virtex-II Pro in which the > circuits are given I/O constraints in addition to Fmax contraints. The > results showed a decrease in the absolute Fmax produced for both > families of between 5% to 6%, but a negligible change (less than 0.5%) > in the relative comparison. So, our results as presented in the Net > Seminar remain valid both with a without I/O constraints. > > 2. Design age varies greatly though in general the larger designs tend > to be newer than the smaller designs. Most of the large designs (>40K > LEs) are less than 1 year old. Most of the small & mid density designs > are 1-3 years old. To the extent that we look for data points that are > "out-lying" and fix them (as they are often representive of broader > issues), there is some tuning of our software around these designs. I > think this likely contributes to the discrepancy in results, though I > would speculate that it contributes much less than the methodology > differences. > > Dave Greenfield > Altera Product Marketing > > > nofpgaspam@yahoo.com (SD) wrote in message news:<27eca41.0404131035.7a9a355f@posting.google.com>... > > Dave, > > > > Thanks for your response. If I may address some of these points one > > last time... > > > > 1. I understand that you don't have constraints for all these designs, > > but for the designs you ran the benchmarks on, wouldn't it be more > > thorough to include the I/O timing for the critical path as well? > > Since you already have the data, it shouldn't be much more effort. > > Would it be possible to at least show an average Tsu/Tco change on the > > critical paths for the benchmark designs? I'm not disputing your > > claims of a 5% difference, but without that data, I'm only getting > > numbers for the middle slice of the path. > > > > 2. Could you provide the approximate average age of these designs? > > Also could you comment on whether you think some of the discrepancy in > > the benchmarking results is due to tool/architecture tuning to these > > designs? If the designs were used during Altera's tool/architecture > > development, then they should (and hopefully would) favor an Altera > > implementation. > > > > 3. Sounds reasonable enough :) > > > > SD > > > >Article: 68913
Mario Prato wrote: > Hi, > I looking for a small fpga in plcc84 package to migrate from a XC95108 > based design, any ideas? not necessarily from Xilinx... > This design is only for educational purpose, so low cost is very > important, speed is not a problem.. I think the Atmel ATF1508ASL comes in PLCC84, and Atmel also have a Demo Board, (ZIF84 included) with LEDs that is a good 'educator'. This is 5V, Low power, and 128 macrocells. -jgArticle: 68914
hmurray@suespammers.org (Hal Murray) wrote in message news:<108c3g94o54ek1a@corp.supernews.com>... > >F(A,B,C,D) = /A*B*C*D + A*/B*C*D + A*B*/C*D + /A*/B*/C*D + > > A*B*C*/D + /A*/B*C*/D + /A*B*/C*/D + A*/B*/C*/D > > > >If you allow some of the outputs of the 2-input AND gates to be shared > >across minterms, then you can cut 8 AND gates and get down to 23 2-input > >gates. > > That looks like odd parity, aka an XOR tree. If Peter's claim > of a (2 input?) XOR counting as 4 NANDs, then we can built it in > 2 layers using 12 gates rather than 23. Did I miss something? > > In almost any ASIC cell lib, an XOR can be as little as 1 2nand gate for the elcheapo xfer common control version or usually about 2 2nand gates worth of area for the much better aoi version. I could look up the actual sizes for AMI,HP,VLSI but those are dated 0.6u. An inverter usually costs about 70% of a 2nand. Its not the transister count but the local interconnect that can make some of these bigger cells not so big after all. Please forget about counting 2nand equivs. It makes no sense for ASICs or FPGAs. For most of my FPGA XST synth reports I look at the bigger functions it finds, ie adders, Dflops, muxes etc and convert them directly into their equiv ASIC by looking at the lib relative areas. Most of my logic doesn't produce alot of those funny 4-8 functions that can't be easily described or compared, its the memories, muxes, flops, adders (maybe multipliers) that dominate. > > I'm assuming NOR and NAND count the same. Is that generally true? > How do ASIC people count inverters? A whole gate or a partial gate? > How about AND vs NAND? Do I get a free inverter sometimes? Nand & Nor are usually 1 unit but Nands are much prefered over Nors due to p being 1/2 strength of n fets. Inverter is 0.7 of 2nand. And/Or might usually be 1.7 or possibly smaller say 1.5 for local optimisation. Each cell generally has some cost just to insert power & substrate hookup and DFlops, adders & bigger muxes are spared the insertion cost by cramming as much as possible into the 1 fixed cost per cell. You can get some of this ASIC lib info from TLSI,UMC even Mosis and if you ask nicely a sales guy will hand you the books, just don't say you are using FPGAs. regards johnjakson_usa_comArticle: 68915
Read the readme.txt file that comes with the script! Jim jimwu88NOOOSPAM@yahoo.com http://www.geocities.com/jimwu88/chips "Lee" <yxl4444@louisiana.edu> wrote in message news:5c3c88bc.0404211512.66c6020d@posting.google.com... > I have read the solution #2561 about how to compile librarie for > modelsim. I download the tcl script file, but I don't know how to use > it. Can anybody tell me?ThanksArticle: 68916
"Maciej Witaszek" <nospam_mwitasze@elka.pw.edu.pl> wrote in message news:c66q61$t6q$1@mamut.aster.pl... > On Tue, 20 Apr 2004 00:11:46 +0200, jerry1111 wrote: > > > I got SODIMM from laptop and compiled some simple design (only with UART > > & lcd). Worked from the first time. Board was the one with Apex20KE, > > > > Have you tried "minimal_sdram_32" from examples directory? > > Hi jerry1111, > where did you find "minimal_sdram_32"? I coudn't find it in Quartus 3.0 and > 4.0 both Web Edition and in NIOS dev kit. I'm working now on my own design > so it's posibble that I mixed up a wiring. > I simulated a cpu with Verilog model of SDRAM from Micron and cpu read > instruction from SDRAM. It looked ok. I don't what I'm doing wrong :( > > Best regards, > Maciej > > > PS: To juz taki czas, ze rodacy szukaja pomocy za granica? :-) > PS. Milo, ze w Polsce tez sie ktos tym zajmuje :) > > -- > Maciej Witaszek > nospam_mwitaszek@elka.pw.edu.pl > remove "nospam_" from my address Maciej, This may not pertain to the Apex board sample designs, but the Cyclone samples had a few ns delay on the SDRAM clock. My custom design with the same exact SDRAM chip had to have this delay removed. I was of course happy with this as I now have an unused pll available. KenArticle: 68917
Hiro, The OPB inclued in the EDK supports burst transactions. However, a potential limiting factor may be some of the IP that we deliver which doesn't support burst transactions (for instance, the MicroBlaze I and D Master OPB connections do not support burst currently). Matt hiro wrote: > Dear All, > > Does OPB bus(V2.0) included in Xilinx EDK6.2 support burst transfer > mode (fixed burst or variable burst)? > If yes, how many data can it transfer(read/write) at one operation? > > HiroArticle: 68918
I am a beginner, don't know how to use the tcl file. Stupid enough:-(Article: 68919
tushitjain@yahoo.com (tushit) wrote in message news:<ec6aab0.0404192227.772520b0@posting.google.com>... > Hi, > Thanks for all the help. I wrote the constraints as you have > described, but I am not able to meet the setup time requirement. The > PCI design was done originaly for an ASIC and changing it will be a > big project by itself. My setup time on some paths is 11-12ns. This is > because of a lot of comb. logic in the data path between pin and > register. Is it possible to add delays to the clock path only for the > register which has the setup time violation? This would mean that I > would be trading off freq. for setup time. > Does Quartus do this for me through any optimization options? I did > see a tsu-freq trade off but that is opposite of what I need. > Thanks again for all the help. > Regards > Tushit Hi Tushit, It sounds like you have too many levels of logic on your set-up path. That is definitely the most difficult set of paths in PCI. Quartus does not have an option to automatically delay the clock to a register. There are (tricky) ways to do it by hand, but I wouldn't recommend going down that route. Which device and speed grade are you using? Which synthesis tool? Knowing what you're using will help me give more focused answers. Altera's PCI cores have 2 or 3 levels of logic on the Tsu critical paths. The most critical paths are those involving trdy and irdy in most cases, since those high-fanout signals are harder to localize. So the most important thing to meeting PCI timing is to get a small number of levels of logic on those paths. If you are using Quartus Integrated Synthesis and finding it is not doing a good job on that path, you can put lcell buffers in your HDL to tell the mapper where you want the lcell boundaries. In most circuits this isn't necessary, but PCI is a case where synthesis can fall short. Another, simpler option, is to turn on physical synthesis and see if it improves your results. Physical synthesis knows what the placement is, so it can make better informed decisions about what should be a logic cell than the front-end synthesis. The good news is that if you get the levels of logic down to a reasonable level, the fitter should do the rest automatically for you, so long as you're using Quartus II 4.0 or later. We meet 66 MHz, 64-bit PCI with no place & route constraints in Stratix, so 33 MHz is easy for the fitter. Hope this helps. Let me know how it turns out! Vaughn AlteraArticle: 68920
There are about 40 different development boards listed at http://www.altera.com/products/devkits/kit-dev_platforms.jsp The Microtronix Cyclone board is targeted at industrial / automotive, and sounds like it might have the kind of communication you want -- USB, RS-232, RS-485, Ethernet, etc. It's got a Cyclone C20 on it, which is pretty big (20,000 logic cells), but still not that expensive. If you need bigger than that, there are larger Stratix devices on other boards, all the way up to multi-S80 devices (at significantly higher prices of course). Vaughn If your budget won't bear that kind of expense, the > Hi everybody, > > I'm currently working on a demonstration project of a lightweight vehicle. > We would like to include a large FPGA to do some control and signal > processing. This would ideally be a totally contained development board, > that could be wired into some kind of bus. (Avoiding using a heavy > backplane) Or a dual processing system with a conventional processor and > FPGA on the same embedded card. > > Unfortunately we're trouble identifiying a suitable device. There appears to > be many PCI/VME ready devices, but few that can be used standalone (Attached > to just communications and power!) > > Does anybody know if there are suitable devices commercialy available? Could > you point me in the right direction please? > > Also is there any information available on similar projects. (Where an FPGA > has been used as the controler for a vehicle)Article: 68921
> I hope I will be corrected if I am wrong about DLLs, but DLLs will clean > up a certain amount of input clock 'jitter' (also called phase-noise). > If the relationship between the input frequency and the output frequency > is divisible by a power of two, the DLL's output clock should have very > little jitter. If the relationship is more arbitrary, the output clock > will have a certain amount of jitter. DLL's are great for doubling, > quadrupling, or halving input clock rates. They aren't so great if you > want a clock division of, say, seven-elevenths, or a clock > multiplication of 19.842. > > A PLL/VCO combination is generally (I believe) less tolerant of input > clock jitter, but can produce a more arbitrary clock division or > multiplication within a reduce operating range, while minimizing output > clock jitter. Hi Dwayne, The input jitter filtering you describe above is backwards. PLLs filter input jitter -- high-frequency jitter is attentuated, although sufficiently low frequency input jitter is passed through. DLLs pass input jitter straight through. It's a fundamental property of how they work -- PLLs are synthesizing the clock from an oscillator that won't drift fast enough to follow high-frequency input jitter. DLLs are constructing a clock that is a delayed / digitally multiplied / divided version of the input clock. So all input jitter gets copied to the output. Regards, Vaughn AlteraArticle: 68922
Hi Andy, > I re-iterate again: Ask yourself: "What happens when both set and > reset are simultaneously > asserted?" You may have a problem here. > > Does your simulation drive both set and reset at the same time? No, firstly is driven the set signal and later (after some clk periods the reset signal). I now what I am doing when writing like this; in my design the reset has more priority than the set signal. Thanks, Arkaitz.Article: 68923
Hi.. I want to ask a question. is there a FPGA which have low number of I/O pin but high capacity of CLB resources?Article: 68924
I would agree ... and stand corrected ... but can you always think of the right words ... :-) But I did point out that you re-sync... that implies something... and I believe the delayed shift register (mentioned in this thread) has already been done but that also requires a clock. and so I think most people have seen an "AT" modem.. re auto baud.. Hayes and stuff like that .. even they have clocks. FPGA's are synchronous.. so is a UART. All comms is synchronous or synchronised. (unless its simply on and off!) Simon "Peter Alfke" <peter@xilinx.com> wrote in message news:BCABF216.5FA4%peter@xilinx.com... > I would call that self-synchronizing, not self-clocking. > Manchester code is self-clocking, provided you get it going "on the right > foot". > Peter Alfke > > > From: "Simon Peacock" <nowhere@to.be.found> > > Organization: TelstraClear > > Newsgroups: comp.arch.fpga > > Date: Wed, 21 Apr 2004 20:31:28 +1200 > > Subject: Re: Issues on Shift Register in a Clockless UART > > > > it should perhaps be pointed out that UART's aren't in fact clockless.. they > > are self clocking... that is the clock is passed with the data (i.e. the > > leading edge of the start bit is the re-syncing edge) > > > > Simon > > > > > > "Peter Alfke" <peter@xilinx.com> wrote in message > > news:BCAB2209.5F87%peter@xilinx.com... > >> Simple answer: You cannot. You can of course generate your own clock... > >> Peter Alfke > >> > >>> From: shashi22k@rediffmail.com (Shashi) > >>> Organization: http://groups.google.com > >>> Newsgroups: comp.arch.fpga > >>> Date: 20 Apr 2004 16:35:16 -0700 > >>> Subject: Issues on Shift Register in a Clockless UART > >>> > >>> Hi, > >>> I'm doing a project in clockless uart..as u know that the primary > >>> function of uart is parallel to serial conversion while transmitting > >>> and serial to paralel conversion while receiving..I was wondering if > >>> someone could tell me as how can i do a parallel to serial conversion > >>> and vice versa without using a clock. > >>> > >>> Thank You > >>> SHASHI > >> > > > > >
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