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"Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message news:<40607335$0$31706$fa0fcedb@lovejoy.zen.co.uk>... > I'm sure I've read here about problems running Quartus with > one/some of AMD's 64 bits processors. I think the problem > was a script checking the processor and crashing out > because it didn't recognise the AMD64. > > Does anyone know if this has been fixed? Do all versions of > Quartus work with 64 bit processors (specifically Athlon64s)? > > My main machine's a bit old and tired and I'm thinking of > building myself a new one, but need it to be able to run > tools from A and X. > > > Thanks for any pointers, > > Nial. > > > ------------------------------------------------ > Nial Stewart Developments Ltd > FPGA and High Speed Digital Design > Cyclone based 'Easy PCI' proto board > www.nialstewartdevelopments.co.uk Hi Nial, Quartus II 4.1 will be qualified to work on Opteron processors with Red Hat Enterprise and Red Hat 8.0. In the meantime there are two scripts that can be easily modified to avoid the problem. Here are the details on the changes to make it work on an Opteron. 1) Add this statement after line 130 in the <quartus rootdir>/adm/qenv.csh file: if ( "$redhat_ver" =~ "Red Hat Enterprise Linux WS release 3") set redhat_ver=3.0ws Description: We try to extract the Red Hat version from the /etc/redhat-release file but under Enterprise Linux the pattern has changed, causing problems later in the script. This will be fixed in Quartus II 4.1. 2) Edit line 65 in <quartus_rootdir>/mw/setup-mwuser.csh. Change the line from: if ((`arch` =~ i*86) || (`arch` =~ ia64)) then to if ((`arch` =~ i*86) || (`arch` =~ ia64) || (`arch` =~ x86_64)) then Description: Mainwin startup scripts (which are sourced/included even in the non-GUI executable wrapper scripts) don't support AMD64 (only IA64 -- Itanium). Need to add a check that accepts the result of "arch" on AMD64-based systems. This should be fixed in Quartus II 4.1. 3) Copy /lib/libuuid.so.1 from Red Hat 8.0 or Red Hat 9.0 (32-bit) into the <quartus_rootdir>/linux directory. This 32-bit library was missing from Red Hat Enterprise 3.0 for AMD64 in our installation. I hope this enables to you use the software on Opteron successfully. If you have any questions, please feel free to contact me. - Subroto Datta Altera Corp.Article: 67976
happyjoyjoy31@hotmail.com (Neven Colak) wrote in message news:<4a99fb95.0403221302.5b44cb10@posting.google.com>... > HI, > > I am designing a PCI card which will have a Stratix FPGA as the PCI > controller. The Stratix will have a PCI-X core with PCI backwards > compatibility. Now from my readings, PCI-X is 3.3V only signalling, > whereas today the majority of PC motherboards (pre PCI 2.3 spec) are > 5V signalling. For obvious reasons I will have to make my PCI card a > universal card (keyed to both 5V and 3V3) in order to accept present > day common motherboards (PCI 5V) and future motherboards (PCI-X/PCI > 3V3). > Is there anything special I need to consider? > > Does anybody know where I can find info on making my universal card. > Any good books or App notes. > > Thanks, > Neven Neven, Altera has published an application note (http://www.altera.com/literature/an/an330.pdf) on how to connect a 3.3V-IO FPGA to a 5V PCI bus. This can work for a universal bus as well. We have not specifically examined this for PCI-X. The issue that you may face is timing - the faster clock rate of the PCI-X bus may be a problem when using the bus switch device discussed in this application note. I suggest taking a look at this and determining if you can meet your timing budget with the added delay imposed by the bus switch. If you are doing 66 MHz PCI-X, it probably will be OK as the tCO and tSU are not that tight. For faster rates it will require some analysis. Sincerely, Greg Steinke gregs@altera.com Altera CorporationArticle: 67977
"Subroto Datta" <sdatta@altera.com> wrote in message news:ca4d800d.0403231638.293226bd@posting.google.com... > Quartus II 4.1 will be qualified to work on Opteron processors with > Red Hat Enterprise and Red Hat 8.0. In the meantime there are two > scripts that can be easily modified to avoid the problem. Here are the > details on the changes to make it work on an Opteron. [snip] That's great. Any idea how the Opteron/Linux speed compares with P4/W2k speed? ThanksArticle: 67978
bob <bob@bob.com> wrote in message news:<405F6DAD.2B7CDE60@bob.com>... > We designed a board using the JTAG and passive serial download > procedures in AN250 a while back. In Sept of 2003 > Altera released their "Configuration Handbook" in which now apparently > the JTAG lines have to have pull ups and > downs on them (though the down is incorrectly stated as 10K should be 1K > apparently). It would seem, if i read > between the lines, that the JTAG pullup on the TCK pin within the device > can cause some sort of fault The fix for this is to pull the TCK pin > low with 1K. > > If this is so has anyone seen an errata they can point me to? > > Has anyone seen strange loading faults where CONF_DONE goes high BUT the > FPGA is not operating properly? It > happens to us only every few thousand loads. > > I am keen to resolve this in some way. Bob, The device has a weak pull-up on TCK, TMS, TDI. The potential problem: If VCCINT powers up first, then the JTAG circuit is on and waiting for inputs. As VCCIO ramps up, TCK and TDI will both go high eventually (since the pullups are connected to VCCIO). TCK may be seen as high first, or TDI. This is a potential problem since the part will behave differently. Hence the external pulldown on TCK - this ensures that there's no spurious positive edges on TCK. If the VCCINT and VCCIO ramps are close, then you could see an infrequent problem like you see. You could try forcing VCCIO to ramp up first to ensure that there's no spurious edge - or a pulldown on TCK. Another reason for seeing CONF_DONE go high, but no FPGA operation, is that the device is not initialized. After CONF_DONE goes high, the FPGA needs some number of extra clocks to go into user mode. It may be that these clocks are not getting transmitted to the FPGA. If you are configuring from a CPU, make sure that it's not stopping when it sees CONF_DONE go high. Altera has an on-line troubleshooter for FPGA configuration problems. You can take a look at this also for more specifics on your situation. http://www.altera.com/cgi-bin/ts.pl?fn=configuration Sincerely, Greg Steinke gregs@altera.com Altera CorporationArticle: 67979
In the DSP chip world, different filter forms often yield "better" results in terms of quantization, noise, magnitude of internal nodes, etc.. For example, the 4-multiply normalized lattice/ladder IIR filter often gives excellent results, though is more computationally intensive. One chooses the appropriate form for the job. The same should hold true in FPGA implementations, though I don't know if the various forms are commonly implemented, or if they usually stick to Direct Form. Maybe Ray can comment on that. (I have no experience with IIR filters in FPGAs, just in DSP chips.) "Ray Andraka" <ray@andraka.com> wrote in message news:4060D30A.E59702A1@andraka.com... > Depends on your filter design. Implementing an IIR filter in fixed point > usually has to use a rather wide word, and care needs to be taken in the > selection of the coefficients in order to avoid nasty quantization effects. > Implementation in an FPGA has little to do with the filter design other than > the physical realization of it. > > "Sam (rép. sans -no-sp-am)" wrote: > > > Hi all ! > > > > Thank you for reading this message ! > > > > I would like to know how width are the busses between the registers of an > > IIR filter (ie implemented in a FPGA), because these filters have coeffs > > > 1. I have seen that the result of b0*x(n-1) can be as large as 5e5 with a > > simple sin as input signal ! > > > > Could anybody help me ?? > > > > thanks in advance ! > > > > SamArticle: 67980
melee5@my-deja.com (Lee) wrote in message news:<a57ea28d.0403210203.40da6c2@posting.google.com>... > Thanks for looking. What I got is some .src files with > only input/output pin declarations (pin number and > variable name) and then logic equations for the output > pins VS input states. This file is representing a 16L8 > PAL supposedly. What I need is to go from here to a PAL > JEDEC file suitable for programming, by what method(s) > please? I'm new at this and would dearly like to know if > anyone can recognize this simple .src format and name any > software that can use it. Thanks, guys, I did find an almost exact match with WinCupl's gates.pld file as far as layout and section usage which means my source most likely renamed the file to .src for some obscure reason. After subbing in g16v8a; for the P16L8; line I got WinCupl to generate a GAL JEDEC file which then burnt fine and it even replaced the working PAL with no appearent problems so far. So now I've got a fuse plot and can proceed with other projects as if I know what I'm doing. Thanks again for helping this noob get his feet wet.Article: 67981
> Quartus II might be compiled with the Intel compiler... > > Opteron / Athlon 64 has SSE2 but the Intel produced code > checks if the processor is an _Intel_ with SSE2 - if not > it refuses to run... > There was a long thread on comp.arch about this > issue... > Patcing the binary to remove the check got > it to run. Roger, Quartus is not compiled with instructions specific to Intel processors. Under supported versions of Windows (see www.altera.com), it should operate fine on any x86-compatible processor, including all Intel and AMD processors. This particular issue is isolated to Linux on AMD64 machines and relates to some scripts and libraries. Please see Subroto's post in this thread for details. Regards, Paul Leventis Altera Corp.Article: 67982
Hi Pete,
> That's great. Any idea how the Opteron/Linux speed compares
> with P4/W2k speed?
While I don't have the data to answer the OS vs. OS question, here is some
info on platform vs. platform performance on three Linux systems. The
results below represent the run-time of four large designs (synthesis +
place & route) in minutes. I've also expressed the run time as a fraction
of Opteron run-time, and given geometric averages. I've also given the
synthesis only and fitter only results on average below the table (I'm too
lazy to type them all in an ASCII friendly way).
Summary:
- 3.06 Ghz Xeon is 15% slower than 2.2 Ghz Opteron overall
- 2.0 Ghz Athlon XP is 29% slower than 2.2 Ghz Opteron overall
In other words, as expected, Operton does well.
[Best viewed with fixed-point font]
CPU AMD Opteron x2 Intel Xeon x2 AMD Athlon XP 2800+
Frequency 2.2 Ghz 3.06 Ghz 2.0 Ghz
RAM 1 GB PC2700 2 GB PC2100 1 GB PC2700
Cache 1MB L2, 128KB L1 1MB L3, 512KB L2, 512KB L2, 128KB L1
20K L1
Disk 80 GB 7.2K IDE 36 GB 10K SCSI 80 GB 7.2k IDE
System IBM eServer 325 Dell PowerEdge 1750 HP d325
OS Red Hat Ent. 3.0 Red Hat 9.0 (32-bit) Red Hat 9.0 (32-bit)
(AMD64)
Fitter + Synthesis
Time (m) % Time (m) % Time (m) %
Design #1 256.52 100 322.68 126 351.32 137
Design #2 74.03 100 80.83 109 93.30 126
Design #3 122.57 100 136.60 111 157.07 128
Design #4 22.58 100 25.50 113 28.10 124
GEO. MEAN 100% 115% 129%
Fitter Only (average only)
GEO. MEAN 112% 128%
Synthesis Only
GEO. MEAN. 149% 145%
- Paul
Article: 67983hi. i'm just starting out with fpga. maybe this question has popped up many times. which one is more useful in the industry: verilog or vhdl? which one do you recommend for starter? i'm also learning with a goal to implement dsp in hardware.Article: 67984
Hello, All!
First of all, excuse me for my english. I'm russian student that have
a little problem with Exemplar Leonardo Spectrum 20001b.106.
Would you please to briefly view these simple and short file-listings
and tell me what
you think about problem with LOC (RLOC, RLOC_ORIGIN) attribute. I just
can't force Leonardo to place specific blocks at specific place on
crystall.
Need to say that other synthesys tool - that comes with Xilinx ISE
4.2i - is OK with my demand. But i need to use Leonardo (actually
that's my professor's requirement). May be the version is too old?
And need to say that other project was placed on right places by
Leonardo. That other project was more difficult than this one.
Thanks!
Hope to read from you soon!
P.S. The programs that I use - Xilinx ISE 4.2i + Leonardo for
synthesys.
========================= top.vhd ======================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top is
Port (
clock: in STD_LOGIC;
reset: in STD_LOGIC;
ce, load, dir1, dir2: in STD_LOGIC;
din1, din2: in STD_LOGIC_VECTOR(15 downto 0);
count1, count2: inout STD_LOGIC_VECTOR(15 downto 0)
);
end top;
architecture Structural of top is
component counter
port (
CLK: in STD_LOGIC;
RESET: in STD_LOGIC;
CE, LOAD, DIR: in STD_LOGIC;
DIN: in STD_LOGIC_VECTOR(15 downto 0);
COUNT: inout STD_LOGIC_VECTOR(15 downto 0)
);
end component;
attribute LOC: string;
attribute LOC of C1: label is "CLB_R1C1:CLB_R16C1"; -- HERE IT IS!
attribute LOC of C2: label is "CLB_R1C2:CLB_R16C2"; -- HERE IT IS!
begin
C1: counter port map (clock, reset, ce, load, dir1, din1, count1);
C2: counter port map (clock, reset, ce, load, dir2, din2, count2);
end Structural;
========================= counter.vhd ======================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter is
Port (
CLK: in STD_LOGIC;
RESET: in STD_LOGIC;
CE, LOAD, DIR: in STD_LOGIC;
DIN: in STD_LOGIC_VECTOR(15 downto 0);
COUNT: inout STD_LOGIC_VECTOR(15 downto 0)
);
end Counter;
architecture Behavioral of Counter is
begin
-- Required Libraries
--library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
-- 4-bit synchronous counter with count enable,
-- asynchronous reset and synchronous load
process (CLK, RESET)
begin
if RESET='1' then
COUNT <= "0000000000000000";
elsif CLK='1' and CLK'event then
if LOAD='1' then
COUNT <= DIN;
else
if CE='1' then
if DIR='1' then
COUNT <= COUNT + 1;
else
COUNT <= COUNT - 1;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
==========================================================================
--
Best regards,
SB
Article: 67985> hi. i'm just starting out with fpga. maybe this question has popped up > many times. which one is more useful in the industry: verilog or vhdl? > which one do you recommend for starter? > > i'm also learning with a goal to implement dsp in hardware. Well, the most useful thing you can learn is to write decent hardware. It doesn't matter if you start with Verilog or VHDL. You need to learn to write structured and good hardware. It's like asking if you want to start with Java or C++ in software. The most important thing is learning HOW to program and not the language itself. There are many discutions about the advantage and disadvantages of VHDL versus Verilog. So I recomend just to do a few samples in both languagues and then decide which one you like best. In the end you'll stick to one of those 2 (or both). After you mastered the delights of digital design you should take a look at SystemC ;) JanArticle: 67986
"Subroto Datta" <sdatta@altera.com> wrote in message news:ca4d800d.0403231638.293226bd@posting.google.com... > "Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message news:<40607335$0$31706$fa0fcedb@lovejoy.zen.co.uk>... > > I'm sure I've read here about problems running Quartus with > > one/some of AMD's 64 bits processors. I think the problem > > was a script checking the processor and crashing out > > because it didn't recognise the AMD64. > > > > Does anyone know if this has been fixed? Do all versions of > > Quartus work with 64 bit processors (specifically Athlon64s)? > > > > My main machine's a bit old and tired and I'm thinking of > > building myself a new one, but need it to be able to run > > tools from A and X. > > > > > > Thanks for any pointers, > > > > Nial. > > > > > > ------------------------------------------------ > > Nial Stewart Developments Ltd > > FPGA and High Speed Digital Design > > Cyclone based 'Easy PCI' proto board > > www.nialstewartdevelopments.co.uk > > Hi Nial, > > Quartus II 4.1 will be qualified to work on Opteron processors with > Red Hat Enterprise and Red Hat 8.0. In the meantime there are two > scripts that can be easily modified to avoid the problem. Here are the > details on the changes to make it work on an Opteron. > Why are you so specific about the Linux distribution? I can fully understand that you only test and support Quartus under specific distributions, but having your scripts specifically check for pre-defined versions seems like you are going out of your way to make life hard for users. If you need specific features (say, a particular version of tcl), then make a single "check installation" script that checks the features required - and lets the user continue anyway, since maybe some parts work even if there are problems. I can't imagine that more than a small fraction of your potential linux users would be using Red Hat 8 (at least, given a choice). It's not the current version, and especially in Europe there are other distros (such as SuSE) which are more popular. Also, are you going to have a web edition for linux? I have a full license for Quartus for my windows pc at work, but if there were a web edition for linux I could play with it on my gentoo system at home. If you were to release a web edition for linux, and remove the most instrusive distribution testing, then I'm sure users would quickly give you feedback regarding tweaking to get the system running under all sorts of different distributions. David > > 1) Add this statement after line 130 in the <quartus > rootdir>/adm/qenv.csh file: > if ( "$redhat_ver" =~ "Red Hat Enterprise Linux WS release 3") set > redhat_ver=3.0ws > > Description: We try to extract the Red Hat version from the > /etc/redhat-release file but under Enterprise Linux the pattern has > changed, causing problems later in the script. This will be fixed in > Quartus II 4.1. > > 2) Edit line 65 in <quartus_rootdir>/mw/setup-mwuser.csh. Change the > line from: > if ((`arch` =~ i*86) || (`arch` =~ ia64)) then > to > if ((`arch` =~ i*86) || (`arch` =~ ia64) || (`arch` =~ x86_64)) then > > > Description: Mainwin startup scripts (which are sourced/included even > in the non-GUI executable wrapper scripts) don't support AMD64 (only > IA64 -- Itanium). Need to add a check that accepts the result of > "arch" on AMD64-based systems. This should be fixed in Quartus II > 4.1. > > > 3) Copy /lib/libuuid.so.1 from Red Hat 8.0 or Red Hat 9.0 (32-bit) > into the <quartus_rootdir>/linux directory. This 32-bit library was > missing from Red Hat Enterprise 3.0 for AMD64 in our installation. > > I hope this enables to you use the software on Opteron successfully. > If you have any questions, please feel free to contact me. > > - Subroto Datta > Altera Corp.Article: 67987
Dear Sir or Madam, I have a problem with the speed of my design: The module "decode_destuff.vhd" works with a 90MHz clock in order to do signal processing on incoming parallel 16bit data which have a data rate of 30MHz, that is three clock cycles time to NRZI unstuff the parallel data and to arrange the unstuffed in that way to discard the gaps of the removed bits. The problem is that I only reach about 32MHz instead of 90MHz. If you have the time you can look at the details at http://mitglied.lycos.de/vazquez78 I would appreciate your help. Thank you in advance. Kind regards Andrés Vázquez System DevelopmentArticle: 67988
>> > after reporting that XCV2000E survived 3.3V core voltage I now have a >> > completly dead XC2S200E-PQ208 !!! >engineering stress I guess, there is cheap 5V to 3.3V level converter >to accept 5V level external RS232 signal from MAX232, and... >well if you use 5V6 TVS instead of 3V3 TVS then you get full 5V on FPGA pins. >I still wonder it did damage the FPGA, there is a 2K7 series resistor Usually a good data sheet will have a spec for how much current you can safely dump into the clamp diodes. The footnote below the Absolute Max Ratings table says 10 mA. 2K7 on (5-3) V is under 1 mA. I'd be surprised if that damaged the chip. One way to kill chips is to do something that triggers latchup. Have you put a scope on all the IO signals? Could a wire have slipped while you weren't watching and dumped a lot of current into an IO pin? Latchup by itself doesn't kill the chip, but it will try to draw a lot of power and if you have a good sturdy power supply that gives it a lot of current while holding the target voltage you will be dumping a lot of energy into the chip. It will get real hot very quickly. If you turn the power off fast enough it will recover. (That usually requires electronics rather than human timings.) If you are good (and maybe lucky) you can set the current limit on your lab power supply low enough so that it keeps the chip from frying. Or build in a current limit circuit on your local power supply. I've been (very) glad we used that with a soft-start chip on one board. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 67989
"Paul Leventis \(at home\)" <paul.leventis@utoronto.ca> writes: > > Quartus II might be compiled with the Intel compiler... > > > > Opteron / Athlon 64 has SSE2 but the Intel produced code > > checks if the processor is an _Intel_ with SSE2 - if not > > it refuses to run... > > There was a long thread on comp.arch about this > > issue... > > Patcing the binary to remove the check got > > it to run. > > Roger, > > Quartus is not compiled with instructions specific to Intel processors. > Under supported versions of Windows (see www.altera.com), it should operate > fine on any x86-compatible processor, including all Intel and AMD > processors. > > This particular issue is isolated to Linux on AMD64 machines and relates to > some scripts and libraries. Please see Subroto's post in this thread for > details. I posted two issues. One was related to AMD64, but the other was related to a plain old AMD 32-bit Athlon system running Linux: $cat /proc/cpuinfo processor : 0 vendor_id : AuthenticAMD cpu family : 6 model : 4 model name : AMD Athlon(tm) Processor stepping : 2 cpu MHz : 1202.768 cache size : 256 KB fdiv_bug : no hlt_bug : no f00f_bug : no coma_bug : no fpu : yes fpu_exception : yes cpuid level : 1 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 sep mtrr pge mca cmov pat pse36 mmx fxsr syscall mmxext 3dnowext 3dnow bogomips : 2398.61 $quartus_sh -h The Quartus II software is optimized for the Intel Pentium III processor and newer processors. The required extensions were not found on: 'AMD Athlon(tm) Processor' The Quartus II software will not function properly on this processor model. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 67990
"Hendra Gunawan" wrote: > typically how many times can I burn/download an FPGA before it becomes > unreliable. Burn. Only once. After the smoke is removed they are no longer usable. Download. As in bit-pattern loading on power-up, no limit. Sometimes I wonder about this terminology. When was the last time someone "burned" a bit pattern into a chip, really? A couple of decades ago? Also, shouldn't "download" really be "upload"? :-) -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 67991
Hal Murray <hmurray@suespammers.org> wrote: : >> > after reporting that XCV2000E survived 3.3V core voltage I now have a : >> > completly dead XC2S200E-PQ208 !!! : >engineering stress I guess, there is cheap 5V to 3.3V level converter : >to accept 5V level external RS232 signal from MAX232, and... : >well if you use 5V6 TVS instead of 3V3 TVS then you get full 5V on FPGA pins. : >I still wonder it did damage the FPGA, there is a 2K7 series resistor : Usually a good data sheet will have a spec for how much current you : can safely dump into the clamp diodes. The footnote below the : Absolute Max Ratings table says 10 mA. : 2K7 on (5-3) V is under 1 mA. I'd be surprised if that damaged the chip. : One way to kill chips is to do something that triggers latchup. : Have you put a scope on all the IO signals? Could a wire have slipped : while you weren't watching and dumped a lot of current into an IO pin? As these chips were used chips, unsoldered, then sold and reused by Anti, they have quite a long history of possible (miss-)treatment... Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 67992
"David Brown" <david@no.westcontrol.spam.com> writes: > Why are you so specific about the Linux distribution? I can fully > understand that you only test and support Quartus under specific > distributions, but having your scripts specifically check for pre-defined > versions seems like you are going out of your way to make life hard for > users. If you need specific features (say, a particular version of tcl), > then make a single "check installation" script that checks the features > required - and lets the user continue anyway, since maybe some parts work > even if there are problems. I agree!!! (see http://tinyurl.com/22c86). I think it makes perfect sense that a company only *qualify* a specific distribution, but I hate to see that it checks for a specific string to match /etc/redhat-release and quits with a message saying «unsupported system» when it would most likely run on lets say a SuSE distribution. I've seen scripts checking dozens of permutations of /etc/redhat-relese, various uname outputs etc. to figure out if they are running on an X86 or IA64 based Linux. One could have included two small hello world style precompiled binaries (compiled with the same options, libraries, and features as the target application). One would give the expected output, the other would crash (with cannot execute binary or similar). Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 67993
> Hi Nial, > > Quartus II 4.1 will be qualified to work on Opteron processors with > Red Hat Enterprise and Red Hat 8.0. In the meantime there are two > scripts that can be easily modified to avoid the problem. Here are the > details on the changes to make it work on an Opteron. Subroto, I'll be installing Win2K, has everything always worked under Windows? (From what Paul says above I think the answer's yes). Nial.Article: 67994
Jerry Avins wrote: (snip) >> I would like to know how width are the busses between the >> registers of an IIR filter (ie implemented in a FPGA), >> because these filters have coeffs > 1. >> I have seen that the result of b0*x(n-1) can be as large >> as 5e5 with a simple sin as input signal ! (snip) > FPGA stands for field-programmable gate array. With one, you implement > whatever circuit you design (or choose). The number of bits in a design > is whatever the designer decides. In parallel designs, the width of the > busses is the bit count. In bit-serial designs, those numbers are > uncoupled. With proper scaling, the size of a number and the bit count > aren't necessarily related. Most FPGA designs that I know of are parallel, though you can choose the bit width often in units of 2, instead of 8 or 16 or 24, as on DSPs. I believe it is usual to keep some extra bits for intermediate values and truncate them later. Exactly how many and how often are implementation details. -- glenArticle: 67995
>I want to synchronize 90MHz data which come from an external >90MHz clock domain (GMII transceiver device) >to my internal FPGA 90MHz clock. >So I have two clocks with the same frequency >but they are asynchronous to each other. Are they really the same frequency? Do they come from the same clock source, just by different paths, say using GMII to get from one board to another over a backplane which has a master clock. Or are they two separate systems with different clock sources that are "almost" the same? They have the same number printed on the osc package, but may be off by a few hundred ppm. The usual way to get high speed data from one clock domain to another is through a FIFO. The FIFO needs to be big enough to hold the difference between a fast write clock and a slow read clock for long enough that you can send back a "wait a bit" type signal to the source. (Ethernet pause frames) Or so that you can drop data at a convenient time/place, for example drop a whole packet rather than trashing a whole chain of packets by dropping one byte of each. >What possibilities can be used for synchronization? If the clocks are really the same frequency but just unknown phase, then you don't need a big memory on the FIFO. I think the clean/simple case needs 4 words. You can implement it with raw logic rather than RAMs. The idea is that when you come out of reset, you arrange for the read side to start 2 cycles behind the write side, perhaps by running an "OK" signal through the classic 2 FF synchronizer. That 2 could be 1 or 3, depending on the timing, and when running you might drift from 2 to 1 or 3 as delays change with temperature. So 4 words of buffering covers all cases. (I think.) >Is the following method possible and useful ? : >http://mitglied.lycos.de/vazquez78/ The PLL doesn't make sense to me. The read clock needs to be in phase with the rest of your logic that's going to use the data, so why connect it to the external/write clock? PLL's usually have 2 inputs, a reference signal and the target signal. I only see one going into that box. It might make sense to use a PLL to cleanup the clock, say to reduce jitter, and then run the whole local system off that clock. If you do that, you have to figure out what you will do when the GMII clock dies, say because somebody unplugged the cable. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 67996
Ray Andraka wrote: > Depends on your filter design. Implementing an IIR filter in fixed point > usually has to use a rather wide word, and care needs to be taken in the > selection of the coefficients in order to avoid nasty quantization effects. > Implementation in an FPGA has little to do with the filter design other than > the physical realization of it. (snip) I was about to disagree with this, but then decided not to. One difference is the size of the building blocks. In a DSP you have a small number of sized words you can operate on, usually multiples of 8 or even 16. Once you decide 16 isn't enough, even for processing 16 bit data, you go to 24 or 32. There is little difference between 17 and 24 bits. Most FPGAs let you build ALU's in multiples of two bits. Multipliers and look up tables are somewhat different though, and may be quantized with other sizes. The constraints are a little different, and some of that difference is going to come out in the implementation. -- glenArticle: 67997
who has the lowest price FPGA development kit with hardware and software included? Most affordable? Best Bang for the buck? So, I can learn how to program FPGAs.. please post here.. TIAArticle: 67998
> > 1. I have seen that the result of b0*x(n-1) can be as large as 5e5 with a > > simple sin as input signal ! GRPWD!Article: 67999
On Mon, 22 Mar 2004 17:43:12 -0000, "Tim" <tim@rockylogic.com.nooospam.com> wrote: >The current XCell talks about the Virtex-4. Presumably >there will be no Virtex-3. And, sadly, no Virtex-IV. >We rather looked forward to the Virtex-MCMLXXIX - is it >an FPGA or is it the Pope? > >Scarcely less off-topic, why do decent clocks always show >the 4 o'clock as IIII? One reason is simply to visually balance VIII on the other side. - Brian
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