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"Sam (rép. sans -no-sp-am)" <totalsam-no-sp-am@hotmail.com> wrote in message news:4061ec72$0$702$5402220f@news.sunrise.ch... > Thank you for all these answers ! > > The only thing I would know is how many bits wide should I take for the > intermediate results when I use an IIR filter. The input data is 24 bit. > Should I use more than 24 bits to calculate the partial products, or not ? > > Thank you ! > > Sam There is no one answer for all IIR filters. You need to figure out what the maximum value *your system* can produce relative to the input scale for *your* desired IIR structure and how many bits you need for *your* desired IIR structure to get the stability and noise to acceptable levels.Article: 68026
"Jack" <dreamguy007@hotmail.com> wrote in message news:b7c82826.0403232250.4e3fbf5e@posting.google.com... > which one is more useful in the industry: verilog or vhdl? In the United States, Civilian Companies like Verilog, Defense Companies like VHDL. > which one do you recommend for starter? I recommend Verilog. I was a newbie a year ago in both HDLs and I started with Verilog. Since that time, I have built some projects with Verilog. Now I started to learn VHDL (Very Hard and Difficult to Learn). There are too many stuffs in VHDL that don't exist in Verilog. Man, I hate those ugly VHDL data types and packages! With either languages, you can built the same hardware. So, why not implement the hardware with the easiest of the two languages. > i'm also learning with a goal to implement dsp in hardware. Are you familiar with Matlab? I think Xilinx has a software called Xilinx System Generator. With it, you can write your code in Matlab and the software will convert it to VHDL automatically. With the VHDL code, you can implement your DSP project with Xilinx FPGAs. P.S A good book for starter in Verilog is "Verilog HDL" by Samir Palnitkar. It's definetly the best Verilog book for beginner. I don't know any good starter book for VHDL. I am still searching! HendraArticle: 68027
you use UCF file ( constraints file to specify a pullup) and not in VHDL Ram "Matija" <matija.habek@fer.hr> wrote in message news:<c3s994$p5$1@bagan.srce.hr>... > Hi, > > how can I drive pull-up on external inout port (using VHDL) > Thanks > Regards, MatijaArticle: 68028
"mindy" <mindy@hotmail.com> wrote in message news:4cu3605e1vad3mjged49b7a858j2mdih4s@4ax.com... > ADVERTISEMENT ?? ... > I have two ideas how to do this but don't know enough about the > Spartan-3 products to know if it will work. > > 1) Create Four 8-bit shift registers each running off a different > phase clock source (IE: 0-90-180-270) and run them at 250mhz. ... The shift registers and RAMs in the Spartan-3 can meet 250 MHz with margin. There may be nuance (with both techniques) in the clock skew between the phases that makes your error a bit more. Please note that sampling a start with 1 ns resolution and a stop with 1ns resolution will give you +/- 1 ns total error, not +/- 1/2 ns. ... > 2) Create Four counters with each one running off a different phase > clock source (IE: 0-90-180-270) and run them at 250mhz. ... The counters can also run at 250 MHz without trouble. You need to be aware of synchronization issues so you don't try to asynchronously sample a counter value with your live signal - standard design techniques apply. ... > Any other suggestions for making these type of measurements ? > > Thanks > Mark If you're into small production, consider the Virtex-IIPro (XC2VP2 is the smallest) with the Rocket I/O giving you over 3 GHz sampling if you want it. The additional cost will easily be offset by lower development costs and a better measurement. You might be able to find a Virtex-IIPro seminar in your area in the next few weeks where you can get the seminar and an XC2VP4 board for $150 US. I'd go for sampling a sine/cosine analog signal pair with a dual-channel ADC to get multi-picosecond resolution after converting angle to phase just because it's fun. - John_HArticle: 68029
> I posted two issues. One was related to AMD64, but the other was > related to a plain old AMD 32-bit Athlon system running Linux: > [snip] > > The Quartus II software is optimized for the Intel Pentium III processor > and newer processors. The required extensions were not found on: > 'AMD Athlon(tm) Processor' > > The Quartus II software will not function properly on this processor model. Hi Petter, I erred in my earlier posting. The Linux version of Quartus is compiled with SSE instructions enabled. This means that you need a Pentium III/4 or Athlon XP/MP/64 to run the code. In addition to providing some SIMD and multimedia-specific instructions, SSE is now the preferred approach to implementing floating-point instructions (rather than the old x87 stack-based instruction set). Our Windows versions of Quartus do not use SSE instructions (at least, for now), and so it should work on a plain-old Athlon. Sorry about the erroneous reply, - PaulArticle: 68030
Jack wrote: > hi. i'm just starting out with fpga. maybe this question has popped up > many times. which one is more useful in the industry: verilog or vhdl? > which one do you recommend for starter? > > i'm also learning with a goal to implement dsp in hardware. Jack, The FPGA market is predominantly VHDL. US commercial ASIC market is predominantly Verilog. Europe commercial ASIC market is predominantly VHDL. The defense ASIC market is predominantly VHDL. The big difference between the two is that VHDL is strongly typed. This means there are some basic expression rules you must learn. If you learn them, VHDL is easy. If you fail to learn them, you will hate it forever and claim it is hard. Strong typing is actually a good thing and many of the Verilog methodology experts recommend buying a lint tool to get this capability. On a bad day coding with strong typing, the compiler will abuse you, however, without it, you better have a good testbench and good debugging skills. Cheers, Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Article: 68031
As John_H indicated, this job is easily done with the Multi-Gigabit Transceiver in the smallest Virtex-IIPro device. Use the MGT as receive only. Clock it with a reference frequency of 100 MHz, which via a built-in PLL results in a 2 Gbps input sampling rate, i.e. a resolution of 0.5 ns. Then read the 20-bit parallel side at 100 MHz and either store the words in a BlockRAM for later casual evaluation, or convert the 20-bit code on-the-fly into a binary number that you accumulate. A dual-ported 2k x 9 BlockRAM can do this conversion.. If you have questions, I can help. I am always interested in innovative and unusual applications of our devices... Peter Alfke, Xilinx ================================ > From: "John_H" <johnhandwork@mail.com> > Organization: Xerox Officeprinting NewsReader Service > Reply-To: "John_H" <johnhandwork@mail.com> > Newsgroups: comp.arch.fpga > Date: Wed, 24 Mar 2004 22:42:09 GMT > Subject: Re: Time measurement with Xilinx Spartan-3 - Help > > "mindy" <mindy@hotmail.com> wrote in message > news:4cu3605e1vad3mjged49b7a858j2mdih4s@4ax.com... >> ADVERTISEMENT > > ?? > ... > >> I have two ideas how to do this but don't know enough about the >> Spartan-3 products to know if it will work. >> >> 1) Create Four 8-bit shift registers each running off a different >> phase clock source (IE: 0-90-180-270) and run them at 250mhz. > ... > The shift registers and RAMs in the Spartan-3 can meet 250 MHz with margin. > There may be nuance (with both techniques) in the clock skew between the > phases that makes your error a bit more. Please note that sampling a start > with 1 ns resolution and a stop with 1ns resolution will give you +/- 1 ns > total error, not +/- 1/2 ns. > ... >> 2) Create Four counters with each one running off a different phase >> clock source (IE: 0-90-180-270) and run them at 250mhz. > ... > The counters can also run at 250 MHz without trouble. You need to be aware > of synchronization issues so you don't try to asynchronously sample a > counter value with your live signal - standard design techniques apply. > ... >> Any other suggestions for making these type of measurements ? >> >> Thanks >> Mark > > If you're into small production, consider the Virtex-IIPro (XC2VP2 is the > smallest) with the Rocket I/O giving you over 3 GHz sampling if you want it. > The additional cost will easily be offset by lower development costs and a > better measurement. You might be able to find a Virtex-IIPro seminar in > your area in the next few weeks where you can get the seminar and an XC2VP4 > board for $150 US. > > I'd go for sampling a sine/cosine analog signal pair with a dual-channel ADC > to get multi-picosecond resolution after converting angle to phase just > because it's fun. > > - John_H > >Article: 68032
Peter Alfke wrote: > As John_H indicated, this job is easily done with the Multi-Gigabit > Transceiver in the smallest Virtex-IIPro device. Use the MGT as receive > only. Clock it with a reference frequency of 100 MHz, which via a built-in > PLL results in a 2 Gbps input sampling rate, i.e. a resolution of 0.5 ns. > Then read the 20-bit parallel side at 100 MHz and either store the words in > a BlockRAM for later casual evaluation, or convert the 20-bit code > on-the-fly into a binary number that you accumulate. A dual-ported 2k x 9 > BlockRAM can do this conversion.. > If you have questions, I can help. I am always interested in innovative and > unusual applications of our devices... > > Peter Alfke, Xilinx > ================================ Sounds a good idea. Any numbers on the Jitter and Apertures of the MGT, as the OP may be able to take multiple readings to get even finer resolutions. ( similar to the vernier principle, if you can control phase creep accurately, or just statistical if you can vary phase in a more random manner ) -jg > >>From: "John_H" <johnhandwork@mail.com> >>Organization: Xerox Officeprinting NewsReader Service >>Reply-To: "John_H" <johnhandwork@mail.com> >>Newsgroups: comp.arch.fpga >>Date: Wed, 24 Mar 2004 22:42:09 GMT >>Subject: Re: Time measurement with Xilinx Spartan-3 - Help >> >>"mindy" <mindy@hotmail.com> wrote in message >>news:4cu3605e1vad3mjged49b7a858j2mdih4s@4ax.com... >> >>>ADVERTISEMENT >> >>?? >>... >> >> >>>I have two ideas how to do this but don't know enough about the >>>Spartan-3 products to know if it will work. >>> >>>1) Create Four 8-bit shift registers each running off a different >>>phase clock source (IE: 0-90-180-270) and run them at 250mhz. >> >>... >>The shift registers and RAMs in the Spartan-3 can meet 250 MHz with margin. >>There may be nuance (with both techniques) in the clock skew between the >>phases that makes your error a bit more. Please note that sampling a start >>with 1 ns resolution and a stop with 1ns resolution will give you +/- 1 ns >>total error, not +/- 1/2 ns. >>... >> >>>2) Create Four counters with each one running off a different phase >>>clock source (IE: 0-90-180-270) and run them at 250mhz. >> >>... >>The counters can also run at 250 MHz without trouble. You need to be aware >>of synchronization issues so you don't try to asynchronously sample a >>counter value with your live signal - standard design techniques apply. >>... >> >>>Any other suggestions for making these type of measurements ? >>> >>>Thanks >>>Mark >> >>If you're into small production, consider the Virtex-IIPro (XC2VP2 is the >>smallest) with the Rocket I/O giving you over 3 GHz sampling if you want it. >>The additional cost will easily be offset by lower development costs and a >>better measurement. You might be able to find a Virtex-IIPro seminar in >>your area in the next few weeks where you can get the seminar and an XC2VP4 >>board for $150 US. >> >>I'd go for sampling a sine/cosine analog signal pair with a dual-channel ADC >>to get multi-picosecond resolution after converting angle to phase just >>because it's fun. >> >>- John_H >> >> > >Article: 68033
Verilog. 1. I don't know ANYBODY that is fluent in both VHDL and Verilog that prefers VHDL. The only advantage of VHDL is the signed arithmetic. That doesn't make up for the useless type-checking and lack of ifdef's. 2. Remember the infamous Verilog vs. VHDL competition that Cooley did a few years back? See this link: <http://www.deepchip.com/items/snug99-42.html> In this contest, not a single VHDL contestant was able to finish the problem. Not one. 3. I hope the competition is using VHDL.Article: 68034
hi sorry i got the context wrong what Mr.Dave wrote is the correct solution RAm ramntn@yahoo.com (ram) wrote in message news:<61c2cc9d.0403241424.27530e1a@posting.google.com>... > you use UCF file ( constraints file to specify a pullup) and not in VHDL > Ram > > > > "Matija" <matija.habek@fer.hr> wrote in message news:<c3s994$p5$1@bagan.srce.hr>... > > Hi, > > > > how can I drive pull-up on external inout port (using VHDL) > > Thanks > > Regards, MatijaArticle: 68035
I expect it is a marketing issue where they don't want to use the same number for the Virtex at the 90 nm node as they do for the Spartan at the same node. Virtex 4 sounds much more advanced than Spartan 3! Brannon King wrote: > > I hear the V2Pro was known at various locations internally as the V3. To > avoid the confusion they just skipped to V4. > > I don't understand the clock issue. Mine lookes like this all the way > around: > > /^^\__/^^\__/^^\__/^^\........ > > And I assume they will add an Over-Score key about the time I get my clock > looking smooth on top. > > "Tim" <tim@rockylogic.com.nooospam.com> wrote in message > news:c3n9pa$dqu$1$8302bc10@news.demon.co.uk... > > The current XCell talks about the Virtex-4. Presumably > > there will be no Virtex-3. And, sadly, no Virtex-IV. > > We rather looked forward to the Virtex-MCMLXXIX - is it > > an FPGA or is it the Pope? > > > > Scarcely less off-topic, why do decent clocks always show > > the 4 o'clock as IIII? > > > > -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 68036
Hi, Does anyone know the syntax for a comment in a UCF? The Xilinx documentation just says "You can add comments to the UCF/NCF file by beginning each comment line with a pound (#) sign." I find that PACE (and only PACE) will complain about lines in my UCF that are commented out, if those lines contain a semicolon (;). Is this a bug in PACE, or is the comment terminated by a semicolon? E.g. UCF contains this comment: # NET "vccint" LOC = "AC12" ; # - VCCINT PACE says: ERROR:Pace - Could not apply constraint: # - VCCINT # NET "vccint" LOC = "AC12" ; All the other Xilinx tools parse this particular UCF without problem. Thanks, Allan.Article: 68037
Vaughn Betz wrote: > > Tommy Thorn <TommyAtNumba-Tu.Com--not@yahoo.com> wrote in message news:<4054D4B5.5040504@yahoo.com>... > > Vaughn Betz wrote: > > > You can directly instantiate any legal logic cell from within verilog > > > code by instantiating "WYSIWYG" logic cells. This lets you do any > > > amount of technology mapping you like, and mix it with HDL. > > > > > > The Verilog syntax that is used for instantiating a logic cell is > > > described in QUIP (Quartus University Interface Program), in the > > > document "stratix_wysuser_doc.pdf". You can instantiate logic cells > > > from inside VHDL code by writing a verilog file with the logic cells > > > you want, then instantiating that entity in your VHDL code. > > > > Thanks, that's useful and gets access to _everything_ but it's also a > > rather radical. > > > > Is there a less direct way to achieve parts of this, eg. will Quartus > > use the cascade chain for conjunctions when it could? > > Quartus will use the and-cascade chain in architectures that have it > when it can, automatically. So yes, this stuff is used automatically. > > As for controlling synthesis, direct instantiation of WYSIWYGs (Lcells > etc.) is the most powerful technique, since it lets you do anything. > To use it, you'd normally only code up certain low-level primitives > (e.g. ALUs) where you found you could beat the synthesis tool using > WYSIWYGs. Then you'd use this low-level library as appropriate. > > If you don't want to do that, there are alternative techniques that > are less radical. From least radical to most radical, I'd say these > are: > > 1. Write in a "vanilla" HDL style and let the synthesis tool do all > the work. Generally more straightforward code will result in better > synthesis, since synthesis will recognize what you are doing more > easily. For example, code muxes as binary muxes using a case or > select statement to ensure the compiler recognizes them as muxes and > gives you the best implementation. I don't know what you mean by a "binary" mux. In order to use the cascade chain as the OR of a bus mux (which is the application I was describing) I separately decode the condition for enabling each bus input. Then I AND the bus with the condition decode and the outputs of all the ANDs are ORed. This could map directly to two ANDs in a LUT and the cascade chain for the OR backbone. The speed should also be very good. I had little success getting this to work however. > 2. Replace parts of your HDL with calls to Altera LPMs and > megafunctions. Use the Megawizard plug-in manager in Quartus to > create the megafunctions, then instantiate them in your code. Note > that synthesis tools will automatically infer megafunctions where they > think appropriate, so when you use technique #1 above you will still > likely be making use of megafunctions & lpms. The point of my comment was that this sort of Altera specific coding is necessary although undesired to facility the reuse of code in designs implemented in different (brand or architecture) chips. > 3. Write portions of your HDL in a very structural manner, and use > lcell, carry and (for APEX and the 10K, cascade) buffers in your HDL > to force a certain mapping to logic cells. The Quartus on-line help > will show you the syntax -- basically you pass a signal through an > lcell buffer primitive when you want to ensure that signal will form > the output of a logic cell. Still brand and architecture specific. Less intrusive in the code, but also less effective. > 4. Directly instantiate logic cells from your HDL using the techique > described in QUIP. > > As for the question of why you never see cascade chains longer than 2, > it is probably because the "Cascade Chain Length" is set to 2 (the > default) in "Assignments->Settings->Analysis & Synthesis > Settings->More Settings". Change it to a bigger number to enable > longer cascade chains. Note that longer cascade chains will constrain > the fitter more, so you can sometimes give up the speed you think > you'll gain to reduced fitter flexibility. I had found that setting and tweeked it upward to as high as 16 with no change in the result. I will say that this was some three years ago, so the tools may work better in this regard now. I don't understand why this would result in lower speeds. The point is to optimize the signal flow and speed up the result as well as reducing routing congestion since more of the signals now do not leave the LE/LAB. > All the suggestions above definitely have the potential to hurt > performance instead of helping -- it is definitely possible for a > human to beat the synthesis tools, but it's not trivial. So it's best > to always compare the results of your carefully optimized design > against flow #1 -- fully automated implementation of your HDL -- to > make sure you've really optimized the design, and not de-optimized it. I always start with "unoptimized" code, just like with software, and try to "improve" it with selective and incremental adjustments. I find this is the best way when working with "black boxes". -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 68038
hmurray@suespammers.org (Hal Murray) wrote in message Dear Mr Murray, thank you for your detailed answer. What do you mean when you say that a pll has two inputs, a target one and a reference one? I use the ALTPLL from Altera (Cyclone) and there is only one input. It is the clock from which other clocks can be derivated (change of phase also possible). At http://mitglied.lycos.de/vazquez78/ there is a symbol picture of the pll in Cyclone Devices. It shows just one input. Best regardsArticle: 68039
Dear Sir or Madam, I am using Cyclone FPGAs from Altera. Is the following idea possible ? My entire logic within my "receiver"-FPGA works with a clock that has its source in the "transmitter"-FPGA. That is the clock information generated in the "transmitter"-FPGA is transmitted over a cable into the "receiver"-FPGA. That is that the clock in the "receiver"-FPGA (rec-clock) is synchronous to the the clock in the "transmitter"-FPGA (with the exception of phase which arises from the cable length etc.). This rec-clock feeds my entire logic in the "receiver"-FPGA. As a consequence the rec-clock is put on a global clock tree by the fitter. Let's assume the following case: The cable between transmitter and receiver is unplugged. That is the clock in the global clock tree in the "receiver"-FPGA cuts off. My question: Is it possible to switch the clock in the "receiver"-FPGA in the case of loss to an alternative "security" clock in the "receiver"-FPGA so that some basic functions can still be performed in the "receiver"-FPGA ? My processes in the VHDL modules of course have only one clock in the sensitivity list. So what I am asking for is a kind of clock multiplexing within the global clock tree within the "receiver"-FPGA in the case of cable loss. Is somethning like that practicable ? I would appreciate your help. Thank you very much in advance. Best regards Andrés Vázquez System DevelopmentArticle: 68040
"Paul Leventis (at home)" <paul.leventis@utoronto.ca> wrote in message
news:J%o8c.48201$uz5.9698@twister01.bloor.is.net.cable.rogers.com...
> > I posted two issues. One was related to AMD64, but the other was
> > related to a plain old AMD 32-bit Athlon system running Linux:
> > [snip]
> >
> > The Quartus II software is optimized for the Intel Pentium III
processor
> > and newer processors. The required extensions were not found on:
> > 'AMD Athlon(tm) Processor'
> >
> > The Quartus II software will not function properly on this processor
> model.
>
> Hi Petter,
>
> I erred in my earlier posting. The Linux version of Quartus is compiled
> with SSE instructions enabled. This means that you need a Pentium III/4
or
> Athlon XP/MP/64 to run the code. In addition to providing some SIMD and
> multimedia-specific instructions, SSE is now the preferred approach to
> implementing floating-point instructions (rather than the old x87
> stack-based instruction set).
>
> Our Windows versions of Quartus do not use SSE instructions (at least, for
> now), and so it should work on a plain-old Athlon.
>
> Sorry about the erroneous reply,
>
> - Paul
>
Are you ("you" being Altera, not you personally) honestly saying that you
have specifically built the software for only certain specific processors?
I'm all for taking advantage of newer features such as SSE, but making the
software unusable on Athlon XP processors is hard to comprehend - after all,
they are in common use (I've only bought one Intel-based computer in the
last 5 years, and that was a mistake). Why do you not just do as every
other heavily optomised software package does - have the software check for
SSE, and use it if available, or fall back to x87 versions of the code when
it is not?
These compatibility issues don't affect me for now, and I expect that
compatibility with AMD64 chips will be far more relevant, but it would be a
problem if you used the same Intel-only code on the windows build.
Article: 68041Austin Lesea wrote: >> Burn. Only once. After the smoke is removed they are no longer usable. > How many times have you been burned by a download? It was a joke, you know that, right? Darn email. So hard to communicate! :-) Actually, burned by download ... well I don't do servo motor controls any more and I never did them with FPGA's. I would imagine that downloading a "problem" bitstream into an FPGA-based motor/servo control can have explosive consequences. > Someone I know well once said to me that the main advantage of an FPGA > is that it enables the engineer to make mistakes faster. Sure...if you ignore the tools' compile time. On the positive side, I've learned to use the long compile times to do productive work. It's multitasking. The secret, at least for me, is to have another computer. > Up, down, of course it is all relative. I know, this is a silly discussion. But, consider this. The FPGA/Flash is being sent a file. That's an upload. I'm perfectly willing to stand alone and uphold this as fact. :-) -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 68042
> Are you ("you" being Altera, not you personally) honestly saying that you
> have specifically built the software for only certain specific processors?
> I'm all for taking advantage of newer features such as SSE, but making the
> software unusable on Athlon XP processors is hard to comprehend
Paul Said....
> > with SSE instructions enabled. This means that you need a Pentium III/4
> > or Athlon XP/MP/64 to run the code.
.. it'll work on an XP, not on an old Althlon.
Nial
Article: 68043Hello, Here is the context: I work on a Memec xc2vp7-fg456 and I try to make a reconfigurable multiprocessor architecture on it. For now I'm trying to put two MicroBlazes on the same opb bus [On-Chip Peripheral Bus v2.0 with OPB Arbiter (v1.10b)]. One of the MicroBlaze is connected to 4 leds and the other one is connected to the RS232. When I program the fpga, only the leds are working. So I think that the arbitrer is the problem. I tryed to configure some parameters on the *.mhs: [ PARAMETER C_NUM_MASTERS = 2 PARAMETER C_NUM_SLAVES = 16 ] but it's not working. Does anybody knows where I could find some answear? thanks a lot.Article: 68044
"Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message
news:4062bbfa$0$31689$fa0fcedb@lovejoy.zen.co.uk...
> > Are you ("you" being Altera, not you personally) honestly saying that
you
> > have specifically built the software for only certain specific
processors?
> > I'm all for taking advantage of newer features such as SSE, but making
the
> > software unusable on Athlon XP processors is hard to comprehend
>
> Paul Said....
>
> > > with SSE instructions enabled. This means that you need a Pentium
III/4
> > > or Athlon XP/MP/64 to run the code.
>
> .. it'll work on an XP, not on an old Althlon.
>
>
You are right, I didn't notice that, and I wouldn't have reacted as badly if
I had (sorry Paul / Altera). But that also means that it won't run on a
PII. I guess that are not many designers using such old machines, but there
will always be some - a PII or old Athlon would be perfectly good for small
designs - I still have my PII under my desk for use with old software. I
don't have a compatibility problem at the moment (or at least I don't expect
to - I'm just about to upgrade to QII-4.0 ...). There always comes a point
where it is not worth continuing support for older systems (such as QII-4.0
dropping W98 support), when it makes live much easier for the developers,
and support for newer platforms like AMD64 Linux is more relevant than
supporting older chips, but this case strikes me as unnessarily limiting the
supported platforms.
Article: 68045mdini@dinigroup.com wrote: > That doesn't make up for the useless type-checking... You are right. Type checking is for those lazy people who do not like to debug really complicated errors. :-)) Janos EroArticle: 68046
> The only thing I would know is how many bits wide should I take for the > intermediate results when I use an IIR filter. The input data is 24 bit. > Should I use more than 24 bits to calculate the partial products, or not ? You need to add some MSBs. The number of them depends on the filter sharpness. If the filter is rather selectable you have to add even 8-12 MSBs. Therefore the best solution is to simulate the filter with real signals, investigate the overflows, and select the minimum bit number which does not make the overflow. A.Ser.Article: 68047
Hi all, Just going through the RocketIO documentation and was wondering if anyone had 2 cents to add to my understanding-- I'm using the RocketIO in receive only mode for a custom app, no 8/10b coding (transitions are guaranteed, though). Hopefully generating the RXUSRCLK from the RXRECCLK. I'd like to use the 20 or 40-bit wide data path. The User's guide only gives an example for the 10 bit wide path -- does anyone know where the extra bits are kept for the wider paths? e.g. the 10-bit path is as follows (earliest... latest) RXCHARISK[0] & RXUNDISP[0] & RXDATA[7 downto 0] I'm guessing that this sequence is repeated for the wider paths, that is the 20-bit path is RXCHARISK[1] & RXUNDISP[1] & RXDATA[15 downto 8] & RXCHARISK[0] & RXUNDISP[0] & RXDATA[7 downto 0] but it's never spelled out anywhere. Any advice/experience is much appreciated. Thanks, --Josh ModelArticle: 68048
Hello: I'm creating a design usine an Altera Cyclone and the NIOS processor. The SOPC builder is the Altera graphical tool for entering system details and peripherals. I have several memory devices (20) that I need to enter and probbly change diring the design progresses. My questions is, can I get into a text file and do these same edits? This would be so much faster. GeorgeArticle: 68049
"Nial Stewart" <nial@nialstewartdevelopments.co.uk> writes: > > > with SSE instructions enabled. This means that you need a Pentium III/4 > > > or Athlon XP/MP/64 to run the code. > > ... it'll work on an XP, not on an old Althlon. It's only under Linux, not Windows. I'm probably the only one in the world using Quartus II under Linux on an AMD Athlon :-) Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?
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