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Hi, Does anyone know if 4ns ASYNC SRAM is available? I am designing a system which connects to a 64-bit TS202 tigersharc DSP at a system clock of 100MHz and in order to get a zero-wait state system I need 4ns ASYNC SRAM.. perferably in a 64-bit package (but highly unlikely)... I'd be happy to find a 16 bit device and just populate 4 of them. Any help is appreciated. NevenArticle: 68076
Hi all, I was wondering what the most popular method of applying timing constraints on your design within ISE is? Do most people use the Constraints Editor Is there any other flow? Thanks AnilArticle: 68077
This helps replicate the 500MHz duty cycle in the 50 MHz output how? "paris" <malaka@email.it> wrote in message news:c3vftm$1mbd$1@avanie.enst.fr... > then use analog :) > like in heterodyne reveivers, just choose a Local Oscilator Frequency 50MHz > less than your input frequency, say 450MHz, then multiply it with your input > frequency. The multiplier is analog, a non linear device, i made one with a > small 16 DIP CI a long LONG time ago and it was very cheap (though i dont > remember if it went so high in frequency, but TV circuits have them in the > receiver and TV uses frequencies about 400MHz or more) > at the output of the multiplier you'll get two signals (plus de ones you > injected, so a total of four), one at 50MHz (500-450) and another at 950MHz > (500+450), you can easily filter the 50MHz for your purposes. [large snip] > > "john" <cdufourfour@yahoo.ca> wrote in message > > news:79cc958c.0403250737.5703e059@posting.google.com... > > > Hi, > > > > > > I'm looking for a way to divide a clock frequency with keeping the > > > duty-cycle of the input clock . Unfortunatly, the input duty-cycle is > > > unknown and I had to preserve it ! > > > > > > For example: > > > input : 500MHz , x% duty-cycle > > > output : 50 MHz , x% duty-cycleArticle: 68078
Hello Mr. Dutra, Thank you in advance for your answer, I'll try to explain my think. I'm working (with a colleague) on this card since the beginning of February and we managed to handle several aptitudes: - A design with one MicroBlaze (using the 4 leds, the 8 dip switches, the 3 push buttons and the rs232) - A design with two separate MicroBlaze (the first one using 2 leds and rs232, the second using 2 leds, 8 dips switches and 3 push buttons). The two MicroBlazes had their own opb, lmb, ... they were separated. - a design with the ppc and the two separated MicroBlaze (ppc using the rs232, the first MicroBlaze using 2 leds and the other one using 2 leds and 8 dip switches) We never used EDK before, nor ISE (EDK 6.1, ISE 6.1 and Modelsim 5.5f with compiled libraries). We learned from scratch and I'm sure we didn't choose the good way all the time. While I was trying to handle the MicroBlaze, my colleague worked on the reconfigurable part of the xc2vp7. He managed to make a modular design (two small modules passing the value of the dip switches to the leds), and today (yes, yes!) he finally made them reconfigurable (in fact, for now it is only working with the difference-based method). So that is our experiences till now. Our goal is to make a design that could reconfigure itself when needed: imagine that we have one MicroBlaze doing a task and suddenly there is an application that needs more power! We think that the MicroBlaze could reconfigure part of the fpga to handle the excess of work (with another MicroBlaze, or an IP). Now, we are trying to mix our competencies, and we are facing some problems: - How to reconnect the reconfigured part to the fixed one? (Through the opb) So that's where I am stuck. I tried to divide the job in small parts: 1) Imagine that I manage to connect a new MicroBlaze to the opb, how will it work (since there are now two master on the opb) So I tried to put two MicroBlazes (the first counting on the leds, the second counting to the rs232) on the same opb but it seems that there's only one working (the first one). I tried to exchange the role of the MicroBlaze (the second counting on the rs232 and .) but in that case, none of them worked! So that's were I thought that the problem may come from the arbiter. I tried to find some documentation about it but I only found papers talking about how the arbiter work and not how it is activated. 2) Reconfiguration method problems (bus macro with opb?) - How can we put the bitstream (who will partially reconfigure the fpga) into the fpga, and how will it be we activate?. - And more questions but I don't want to scare you ;-) Thank you very much in advance. Best regards, Jonathan Debrouwere "Paulo Dutra" <paulo.dutra@xilinx.com> wrote in message news:406325F3.8040606@xilinx.com... > Whenever, there are multiple masters/slaves on the opb_v20_v1_10_b > (parameter C_NUM_MASTERS/C_NUM_SLAVES are calculated by platgen), > the arbiter is automaticaly included into the bus logic. You can > not change C_NUM_MASTERS/C_NUM_SLAVES values through the MHS. > > Debugging embedded systems are a complicated process. You should > debugg your design through hw simulation. On hw, you can use > xmd to talk to microblaze. Have you tried removing the microblaze > that go to the leds and isolating the system that talks to the > rs232? How did you come to conclusion that the arbiter is the issue? > > Jonathan Debrouwere wrote: > > Hello, > > > > Here is the context: > > I work on a Memec xc2vp7-fg456 and I try to make a reconfigurable > > multiprocessor architecture on it. > > > > For now I'm trying to put two MicroBlazes on the same opb bus > > [On-Chip Peripheral Bus v2.0 with OPB Arbiter (v1.10b)]. > > > > One of the MicroBlaze is connected to 4 leds and the other one is connected > > to the RS232. When I program the fpga, only the leds are working. So I think > > that the arbitrer is the problem. > > I tryed to configure some parameters on the *.mhs: > > [ > > PARAMETER C_NUM_MASTERS = 2 > > PARAMETER C_NUM_SLAVES = 16 > > ] > > but it's not working. > > > > Does anybody knows where I could find some answear? thanks a lot. > > > > > > > -- > / 7\'7 Paulo Dutra (paulo.dutra@xilinx.com) > \ \ ` Xilinx hotline@xilinx.com > / / 2100 Logic Drive http://www.xilinx.com > \_\/.\ San Jose, California 95124-3450 USA >Article: 68079
dreamguy007@hotmail.com (Jack) wrote in message news:<b7c82826.0403232250.4e3fbf5e@posting.google.com>...
> hi. i'm just starting out with fpga. maybe this question has popped up
> many times. which one is more useful in the industry: verilog or vhdl?
> which one do you recommend for starter?
>
> i'm also learning with a goal to implement dsp in hardware.
If you're asking the question, this implies you're not already locked
into one or the other, and you're open to alternatives.
Verilog is "used" more in industry, but this does not mean it's the
most "useful".
If you are looking for language to describe complex hardware
structures in the fewest lines of code, and with the fewest errors,
consider Confluence.
From a novice's standpoint, Confluence is advantageous because it
enforce a correct-by-construction design mentality. Unlike either
HDL, which promotes habits, Confluence forces you to use a hardware
design mindset. If you can get your design passed the compiler,
you're guaranteed it will synthesize. (Fitting the device and meeting
timing still takes design prowess.)
A few other nice features:
- Only does synchronous logic. Perfect for FPGAs.
- Very simple syntax. SystemVerilog's syntax grammar takes up
41 pages. Confluence's grammar can be printed on 3.
- Compact coding. Typically 2-5X fewer lines than Verilog.
- Generates Verilog, VHDL, and C from one source.
- Produces executable simulation models, so you don't need to buy
an HDL simulator. Allows you to write test-benches in any
high-level language (Perl, Python, Java, etc.).
- Plugs into NuSMV: an open source formal verification tool.
- Includes many advanced features to won't find in SystemVerilog --
even when it gains support in 5 to 7 years.
- Confluence was initially created for DSP design.
- Confluence is open source (GPL).
I put a basic language comparison on-line. Note that some of the CF
component names are a bit out of date:
http://www.launchbird.com/cgi-bin/language.py
Regards,
Tom
Article: 68080Neven Colak wrote: > > Hi, > > Does anyone know if 4ns ASYNC SRAM is available? I am designing a > system which connects to a 64-bit TS202 tigersharc DSP at a system > clock of 100MHz and in order to get a zero-wait state system I need > 4ns ASYNC SRAM.. perferably in a 64-bit package (but highly > unlikely)... I'd be happy to find a 16 bit device and just populate 4 > of them. > > Any help is appreciated. I have never seen any. I know they make 8 ns parts as of a few years ago. They may be making as fast as 6 ns now, but I seriously doubt that 4 ns parts exist. Heck even sync rams barely run at the equivalent to that, 250 MHz. Async rams are becoming specialty parts as most apps move to sync rams. Most current design efforts are in multi-port async rams for comms work. So don't expect async rams to continue to improve performance. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 68081
Craig, Glitch free. Austin Craig Conway wrote: > Is the mux in a Xilinx Virtex2Pro DDR output pad glitch-free if the only > signal toggling is the select? In other words, if I tie the D-inputs of the > two DDR flip-flops to '1', will the output always be '1', or could I get > glitches corresponding to the rising or falling edge of the clock? > > Thanks very much. > > Craig > >Article: 68082
well i cant go into deep math details to prove it cause as i said, i did that a long time ago, and im sure you can find the maths in the internet, like in the link i posted (ok, the link is not so detailed, but it was one of the first results of google) anyhow the procedure i explained, "heterodyning", can be thought as "harmonic" i dont know if in english is called like that, anyway, it means that all the "band" will be transposed (to be moved?) to the two "center" frequencies i said, 50MHz and 950MHz. The "band" im talking about is the spectrum of the 500MHz signal, the spectrum contains the information about the signal, the phase, the shape, the frequency, etc. so it contains also the duty cyle. That's the way most (if not all) receivers work, your mobile phone (well, maybe its a bit more complicated as new ones have "zero IF", but anyway), your TV, your radio, satellite, etc. There's no loss of information (ok, that's never strictly speaking true, according to information theory all treatments increase the entropy, but that's another story, anyway, the thing is that is perfectly good for all uses) so all the characteristic things about the 500MHz signal will be mantained, mathematically, in the real world, filters are not with constant phase, but linear, and a long etc. but, that doesnt prevents your TV from working, there is always some sort of compromise. And Im confident that if it can be made for TV receivers, it can be made for this thing (but i might be wrong as well :) ) I hope this helps, if not and you're not convinced, maybe you could try the basics of radiocommunications, it has been the basis of radiocommunications since the invention of radiocom, now there are other techniques "zero IF" and "digital baseband" but the basics are pretty much the same (though i havent studied in detail these latest technologies) "John_H" <johnhandwork@mail.com> escribió en el mensaje news:d0K8c.20$V4.250@news-west.eli.net... > This helps replicate the 500MHz duty cycle in the 50 MHz output how? > > "paris" <malaka@email.it> wrote in message > news:c3vftm$1mbd$1@avanie.enst.fr... > > then use analog :) > > like in heterodyne reveivers, just choose a Local Oscilator Frequency > 50MHz > > less than your input frequency, say 450MHz, then multiply it with your > input > > frequency. The multiplier is analog, a non linear device, i made one with > a > > small 16 DIP CI a long LONG time ago and it was very cheap (though i dont > > remember if it went so high in frequency, but TV circuits have them in the > > receiver and TV uses frequencies about 400MHz or more) > > at the output of the multiplier you'll get two signals (plus de ones you > > injected, so a total of four), one at 50MHz (500-450) and another at > 950MHz > > (500+450), you can easily filter the 50MHz for your purposes. > > [large snip] > > > > "john" <cdufourfour@yahoo.ca> wrote in message > > > news:79cc958c.0403250737.5703e059@posting.google.com... > > > > Hi, > > > > > > > > I'm looking for a way to divide a clock frequency with keeping the > > > > duty-cycle of the input clock . Unfortunatly, the input duty-cycle is > > > > unknown and I had to preserve it ! > > > > > > > > For example: > > > > input : 500MHz , x% duty-cycle > > > > output : 50 MHz , x% duty-cycle > >Article: 68083
Matthew E Rosenthal <mer2@andrew.cmu.edu> wrote in message news:<Pine.GSO.4.58-035.0403231523110.3481@unix3.andrew.cmu.edu>... > Can someone point me to some documentation explaining the map file. > I have taken the EDK tutorial sample on a memec board and I want to > expand it to do more stuff. It looks like i need more addressable memory > to do this. > The memec board ccomes with a SDRAM chip that I would like to use as > memory but I can't find much documentation about the map file to make use > of this. > > Thanks for your help > > Matt http://www.xilinx.com/ise/embedded/est_guide.pdf Go to Address Management Chapter. RamArticle: 68084
http://xilinx.openchip.org/proto/ BOM for 2MGate FPGA DIY Development system and system closeup photos. pure fun! and relaxing :) need to be or would miss the balls! Antti http://xilinx.openchip.orgArticle: 68085
I am doing back annotated gate level simulations. I have synthesized my design with Synplify and put it through ISE 6.2, generating "Simulation Model" for NC_Verilog (which I use). It generated a verilog netlist and a sdf file which are both properly read. The DUT works just fine and passes all tests, BUT, generates a ton weired error messages (all same) which I can not understand: Timing Violation Error : Setup time 0.000 ns violated on X_RAMB16_S2_S2 instance test.soc2.\i_sram/mem_l.I_2 .display_zero on CLKA port at simulation time 53678.100 ns with respect to CLKB port at simulation time 53678.100 ns. Expected setup time is 0.284 ns Well, I understand the error message, but don't understand what is causing it/how to fix it. The memories have been synthesized from Verilog RTL. So I have no direct control over the clock inputs to the Block Rams. All other timing parameters appear to have been met. Regards, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/ <- FREE EDA ToolsArticle: 68086
I am compiling a 400K gate design with XC2V6000...but ISE-6 failed to route it in 3 days... and it hang arround 500+ wires not routed, the slice usage is 60%... May I assume a system gate of N kilogates in Xilinx's datasheet can only hold an ASIC design of up to N/15 kilogates? KelvinArticle: 68087
> As you mentioned you want to implement DSP in hardware, > I would suggest you to learn verilog. Verilog simulation On the other hand DSP functions might need signed mathematics etc. which is easier to do in VHDL. I have used both languages and both have their good thing and bad things. I couldn't say which one is a better language. In Verilog there are just too many "we have always done this way" things, especially in the scheduling. Many commercial models/libraries assume that events are executed in the same order than they are declared etc. Usually in modern simulators you need to set all flags to emulate VerilogXL and disable all fancy optimisations to be sure that nothing breaks. On the other hand in VHDLs type conversions and verbosity can sometimes be quite a burden. But usually they save quite many bugs. Without good linter it's almost impossible to do big Verilog designs. In VHDL linter is just nice to have feature for some common errors (sensitivity lists, default values for signals, asynchronous paths, naming rules etc.). At the verification side of the fence, VHDL is much easier. No headbanding to the wall when different simulators simulate Verilog completely differently. Good VHDL code is usually easier to read because of higer abstraction level (records, aliases, enums, custom types etc.). Also range checks etc. catch very hard to find bugs sometimes (and sometimes trigger unnecessarily when some value is in wrong value for one delta cycle). > is faster than VHDL (if you have access to Synopysy VCS), Verilog is a little faster to simulate, but the difference is quite small. For reasonable sized RTL designs I don't keep that as a problem (reasonable <10M asic gates). Also in VHDL regression runs which have been already run many times the checks can be removed. Just run with checks once a week. That can save some time from the simulations. And at least in gate level simulations new Modelsim versions seem to be much faster compared to VCS, the story might be different at RTL side. > so if you want to do a simulation of a complete DSP system > it is better to do it in verilog. For DSP like designs it might be wisest to simulate first with Matlab, Fortran etc. And only verify that the RTL version of the idea follows the results. > - Verilog simulate faster (if you have the right simulator) > For VHDL due to strong type nature, it need to do > a lot of checking during compile and simulation. > Also VHDL have more detail timing model which requires > more computation time. The more detailed event system also makes coding easier. And for gate level simulations just don't use VHDL. VHDL netlists are so uncommon that VITAL was never really optimised in simulators. Even if the RTL is in VHDL, the netlists are normally Verilog. > - Smaller memory requirement. In VHDL a signal can have > "1", "H", "0", "L", "Z", "X", "U", "W" and various > attribute including last values, last event, etc. > While in verilog you got only "1","0", "X" and "Z". That is usually not a problem. ~10M gate designs fit easily into ~200M of memory. Even basic desktops have more memory. The signal problem usually bites in memory models. But in memory models one should use variable for the memory array, in that way memory consumption is just a fraction of the signal version. Of course in VHDL it's quite easy to do dynamic memory allocation for the memory model if it is sparce enough. --Kim ps. Verilog vs. VHDL is nice discussion on luch. It has never an end if you have two passionate users of both languages :)Article: 68088
Please post in plain text, not html. <thangkho> wrote in message news:ee83736.0@WebX.sUN8CHnE... >There're several things you need to consider: >1) How complexity/how fast your cpld design is? >2) How difficult your pcb layout >will be? >If your pcb layout is simple and easy to meet timing requirement, then I would like to let >SW assign pins for you. Otherwise you need to be careful assign CPLDs pins and make >sure the design still fit in target device and pass all timming constraint. This task >sometime very difficult (sometime impossible) when your design is closed to edge of >limitation for a particular target...(well, you can always jump to a bigger/faster device if >you can afford...) >regard, In general, the fitter and router software will have an easier job if it is free to place the pins where it wants. However, if you want to wait until the PLD design is complete before finishing the pcb design, there will be a long delay in your development process as you wait for the prototype cards. So often it boils down to a question of how long you expect the PLD design to take, and how complex the board is - perhaps you can do a bit of the PLD design and get an idea of the pins from the software, and then fix them and do the pcb layout. It is also going to depend on the PLD architecture - they vary in how their routing resources are organised, and how features such as output enables are organised. For example, if your PLD only has one output enable signal per bank, there is no point in trying to put two independant bidirectional signals in the same bank, or if your PLD has output macrocells tied tightly to particular pins, and you have a lot of signals going into these macrocells, then you might swamp the routing resources in that block and force the software to use extra macrocells internally, whereas if outputs were spread out more evenly on the pins, your resource usage would drop (I'm talking from experiance here, using older PLD architectures). I can't really comment about other modern PLDs, but I was impressed by how easily Quartus fitted a 63-macrocell design into a 64-macrocell Max3000 PLD, with every pin in use and pre-defined.Article: 68089
vax,3900 wrote: > I need to know when is > the right time to assign pins. My case is a bit different, as I use Altera/Quartus... I always let to=20 compile without pin assignment first. At the end of this I=20 back-annotate, do the pin assignment and recompile/fit. > Do I assign pins after the content is > designed and tested, or before? Depends what you mean =A8content is designed and tested=A8. If you perfor= m=20 simulation on the behavioral or RTL model then this comes first. It=20 makes IMO little sense to test and simulate a chip that has not yet the=20 final pinout. After recompiling and fitting with a different pinout=20 almost all timing issues will be different. > How flexible are CPLDs about assigning > pins? They (Altera in my case) are rather flexible. Important is not to move=20 dedicated clock and other general resource pins. Older smaller Altera=20 chips had limited number of internal interconnects. This means they=20 often could not get fitted with fully prearranged pins. Usually one=20 could find the most critical buses, signal groups and when these were=20 left unassigned the fitting was OK. With modern large FPGAs this is a=20 smaller problem. You can fully arrange pins according the board layout=20 requirements (except clocks, resets) and it can be fitted. Problematic=20 might be if the chip is at its limits (over 95% LCs, I/O pins used) or=20 if you have fast design with timing constraints. FPGAs with arranged=20 pins usually compile with more resources used and slower timing. This is my experience. Janos Ero CERN Div. EPArticle: 68090
Rudolf Usselmann wrote: > Timing Violation Error : Setup time 0.000 ns violated on > X_RAMB16_S2_S2 instance test.soc2.\i_sram/mem_l.I_2 .display_zero > on CLKA port at simulation time 53678.100 ns with respect to > CLKB port at simulation time 53678.100 ns. Expected setup > time is 0.284 ns I think it is normal for Gate Level Chip simulations that you get a bunch of error messages for the time 0.000ns. Janos Ero CERN Div. EPArticle: 68091
Hi, I am searching for a VHDL package which I can use to generate USB traffic for my VHDL testbench simulation in Modelsim. That is some kind of Test Pattern which I can convert to VHDL test pattern or maybe there exists some USB patterns in VHDL yet ? I would appreciate your information. Thank you in advance Andrés Vázquez G & D System DevelopmentArticle: 68092
Hi Sergey, I would suggest you email Mentor educational services (education_services@mentor.com) to get hold of a current license (current version 2004a, your version is 3 years old which in terms of EDA software is very old :-). In Europe we have Europractice (http://www.te.rl.ac.uk/europractice/welcome.html) which enables Universities to get access to expensive EDA tools for a fraction of the price, there might be a similar organisation in Russia. Good luck, Hans www.ht-lab.com "Sergey Baranov" <bars@torec.ru> wrote in message news:c3rdh6$2tfc$1@gavrilo.mtu.ru... > Hello, All! > > First of all, excuse me for my english. I'm russian student that have > a little problem with Exemplar Leonardo Spectrum 20001b.106. > > Would you please to briefly view these simple and short file-listings > and tell me what > you think about problem with LOC (RLOC, RLOC_ORIGIN) attribute. I just > can't force Leonardo to place specific blocks at specific place on > crystall. > > Need to say that other synthesys tool - that comes with Xilinx ISE > 4.2i - is OK with my demand. But i need to use Leonardo (actually > that's my professor's requirement). May be the version is too old? > > And need to say that other project was placed on right places by > Leonardo. That other project was more difficult than this one. > > Thanks! > Hope to read from you soon! > > P.S. The programs that I use - Xilinx ISE 4.2i + Leonardo for > synthesys. > > ========================= top.vhd ====================== > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > entity top is > Port ( > clock: in STD_LOGIC; > reset: in STD_LOGIC; > ce, load, dir1, dir2: in STD_LOGIC; > din1, din2: in STD_LOGIC_VECTOR(15 downto 0); > count1, count2: inout STD_LOGIC_VECTOR(15 downto 0) > ); > end top; > > architecture Structural of top is > component counter > port ( > CLK: in STD_LOGIC; > RESET: in STD_LOGIC; > CE, LOAD, DIR: in STD_LOGIC; > DIN: in STD_LOGIC_VECTOR(15 downto 0); > COUNT: inout STD_LOGIC_VECTOR(15 downto 0) > ); > end component; > > attribute LOC: string; > > attribute LOC of C1: label is "CLB_R1C1:CLB_R16C1"; -- HERE IT IS! > attribute LOC of C2: label is "CLB_R1C2:CLB_R16C2"; -- HERE IT IS! > > begin > > C1: counter port map (clock, reset, ce, load, dir1, din1, count1); > C2: counter port map (clock, reset, ce, load, dir2, din2, count2); > > end Structural; > > > ========================= counter.vhd ====================== > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > entity Counter is > Port ( > CLK: in STD_LOGIC; > RESET: in STD_LOGIC; > CE, LOAD, DIR: in STD_LOGIC; > DIN: in STD_LOGIC_VECTOR(15 downto 0); > COUNT: inout STD_LOGIC_VECTOR(15 downto 0) > ); > end Counter; > > architecture Behavioral of Counter is > > begin > > -- Required Libraries > --library IEEE; > --use IEEE.STD_LOGIC_1164.ALL; > --use IEEE.STD_LOGIC_UNSIGNED.ALL; > --use IEEE.STD_LOGIC_ARITH.ALL; > > -- 4-bit synchronous counter with count enable, > -- asynchronous reset and synchronous load > > > process (CLK, RESET) > begin > if RESET='1' then > COUNT <= "0000000000000000"; > elsif CLK='1' and CLK'event then > if LOAD='1' then > COUNT <= DIN; > else > if CE='1' then > if DIR='1' then > COUNT <= COUNT + 1; > else > COUNT <= COUNT - 1; > end if; > end if; > end if; > end if; > end process; > > > > end Behavioral; > > ========================================================================== > > -- > Best regards, > SBArticle: 68093
vax,3900 wrote: > I am using a CPLD(XC95144) in my board and since it is my first time to play > CPLD, I have the question when to assign pins. The CPLD will have a 22 bit > parallelly loadable counter and two state machines. I need to know when is > the right time to assign pins. Do I assign pins after the content is > designed and tested, or before? How flexible are CPLDs about assigning > pins? Thank you. > > vax, 3900 You will need to map to the CPLD resource, to a certain extent. CPLD have dedicated CLK pins, which are both faster and save product terms, so it would be silly NOT to use these. CPLD also are block structured, with 16-18 Macrocels per block, and they have Product Term and Fan-In limits too. So, you can hit any of these ceilings within a block, but having done that, CPLDs are normally quite tolerant of pinswap WITHIN that block. Best results come when you do the PCB and PLD designs in parallel, and swap the PCB pins as needed for best layout, and then track that within the PLD design. -jgArticle: 68094
I try to realize a partial reconfiguration design, following the Development guide (for modular design) and the xapp290 note. I use a Virtex-II Pro. When I try tu use bus macros, the PAR program cannot complete the route operation (with ISE6.1 SP3 as well as with SP2). This happen for each active module, and in the final assembly too. I found that the signal that is not routed is always the 4th bit of the bus macro. So I think of a problem in the bus macro I use, which has the poetic name of bm_4b_v2p.nmc. Do anyone know where to find a reliable version? Or maybe there is a bug in the PAR program? Thanks for help. Amaury Anciaux.Article: 68095
Tom, tom1@launchbird.com (Tom Hawkins) wrote in message news:<833030c0.0403251544.1f7c5935@posting.google.com>... > If you are looking for language to describe complex hardware > structures in the fewest lines of code, and with the fewest errors, > consider Confluence. <...> > A few other nice features: <...> > - Generates Verilog, VHDL, and C from one source. > - Produces executable simulation models, so you don't need to buy > an HDL simulator. Allows you to write test-benches in any > high-level language (Perl, Python, Java, etc.). <...> > I put a basic language comparison on-line. Note that some of the CF > component names are a bit out of date: > > http://www.launchbird.com/cgi-bin/language.py This is fascinating information. Thanks for taking the trouble to put together the comparison. A few questions, 1. The 4-bit register (for example) in Confluence did not show any clock or reset signals. How big a headache is it to deal with situations where different portions in a design use different clock or reset ? 2. I presently use Quartus + VHDL => Stratix, and am trying out the Simulink + Altera DSP Builder design flow. I can see using Confluence to generate modules in a design, then export VHDL to build into the complete chip design in Quartus. Would this be a reasonable way to go ? 3. Any comments on high-level test and simulation vs Vector Waveform simulation ? I personally find the waveforms intuitive. 4. Have you any experience with how well FPGA tools are able to infer from the Confluence-generated VHDL ? 5. Where can one see an example of a Confluence component and the corresponding exported VHDL ? Did you make the VHDL and Verilog portions of your table by hand, or are they output from the Confluence tool ? Regards, -rajeev-Article: 68096
it's normal for the active modules. they will usually have a few wires unrouted. if you get the final assembly 100% routed then it is working... Kelvin "Amaury Anciaux" <amaury.anciaux@tiscali.be> wrote in message news:c413sa$fak$1@ail.sri.ucl.ac.be... > I try to realize a partial reconfiguration design, following the Development > guide (for modular design) and the xapp290 note. I use a Virtex-II Pro. > > When I try tu use bus macros, the PAR program cannot complete the route > operation (with ISE6.1 SP3 as well as with SP2). This happen for each active > module, and in the final assembly too. > > I found that the signal that is not routed is always the 4th bit of the bus > macro. So I think of a problem in the bus macro I use, which has the poetic > name of bm_4b_v2p.nmc. Do anyone know where to find a reliable version? > Or maybe there is a bug in the PAR program? > > Thanks for help. > > Amaury Anciaux. > >Article: 68097
RocketIO seems to be fun too - we are about to evaluate the use of RocketIO suitability to generate and detect Serial ATA OOB signalling. At first I tried to recompile the BERT error test application from Xilinx website, but it is made for some mysterious Development Board ML320 (There is no info about those boards). Also even though the application note has date Feb. 2004 the actual application note files are for ISE 5.1 and EDK 3.2 what both are way past and obsoleted. The system conversion did work to EDK 6.1 but the resulting system did not. So wanted to see something fast and no luck. So created a simple custom config for RocketIO, wired the connections and connected the TXDATA to our special nano IP core that we use to test crystal frequency (it blinks a LED and beeps a buzzer). Got a SATA cable, cut it in half, soldered a buzzer to it, plugged it into SATA connector named "host" on ML300, download ready, and voila RocketIO is beeping!!! ASFAIK this is the first ever documented real life use of the SATA connectors on ML300 board (except simple loopback that xilinx claims they are doing). Sure using MGT's to make a beep may sound silly, but there might be some very clever use of MGT's as delta-sigma Digital Analog Convertor. Cheers! and may you all have a nice weekend! (I am just about to get warmed up for weekend-work) Antti PS I possible posted this story only because I felt my last posting about making 2M gate FPGA board (by soldering wires to BGA) wasnt hardcore enough ;) PPS if anyone has any example that is fully working and doing something with RocketIO (on ML300!) I would be glad to get a copy of that project. Xilinx? Anyone?Article: 68098
Yes, but in this case, even in the final assembly, this signal stays unrouted. I attach some example files: the NCD routed designs of the two modules, and the final assembly. The signals conerned are controlL<3> and controlL<7> (in module 1 and final assembly). Other unrouted signals in the modules are normal. As you can see, they are connected to the same TBUF in both bus macros. BTW, do you know if the T input of a TBUF has to be "1" or "0" to be in high impedance? Thanks, Amaury "Kelvin" <kelvin8157@hotmail.com> wrote in message news:c4183o$edd$1@mawar.singnet.com.sg... > it's normal for the active modules. they will usually have a few wires > unrouted. > if you get the final assembly 100% routed then it is working... > > Kelvin > > > > > "Amaury Anciaux" <amaury.anciaux@tiscali.be> wrote in message > news:c413sa$fak$1@ail.sri.ucl.ac.be... > > I try to realize a partial reconfiguration design, following the > Development > > guide (for modular design) and the xapp290 note. I use a Virtex-II Pro. > > > > When I try tu use bus macros, the PAR program cannot complete the route > > operation (with ISE6.1 SP3 as well as with SP2). This happen for each > active > > module, and in the final assembly too. > > > > I found that the signal that is not routed is always the 4th bit of the > bus > > macro. So I think of a problem in the bus macro I use, which has the > poetic > > name of bm_4b_v2p.nmc. Do anyone know where to find a reliable version? > > Or maybe there is a bug in the PAR program? > > > > Thanks for help. > > > > Amaury Anciaux. > > > > > >Article: 68099
erojr wrote: > Rudolf Usselmann wrote: > >> Timing Violation Error : Setup time 0.000 ns violated on >> X_RAMB16_S2_S2 instance test.soc2.\i_sram/mem_l.I_2 .display_zero >> on CLKA port at simulation time 53678.100 ns with respect to >> CLKB port at simulation time 53678.100 ns. Expected setup >> time is 0.284 ns > > I think it is normal for Gate Level Chip simulations that you get a > bunch of error messages for the time 0.000ns. > > Janos Ero > CERN Div. EP Actually simulation time in that specific case is 53678.1 ns. This is not a one time message it appears over and over again. Regards, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/ <- FREE EDA Tools
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