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In article <aEQCb.55682$dt3.19182@news.chello.at>, Sandor Jager <sanyi@villamvadasz.hu> wrote: >I've bought a lot of XC2018 (yes I know, antic pieces), >but they were very-veyr cheap, I've had no heart not to >get them :) I hope you mean $.25/each or less. Use em for an art project, not a digital design. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 64076
Norbert, You can download the ISE WebPACK at: http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=ISE+WebPack The main difference between WebPACK and Foundation is that WebPACK does not include FPGA Editor, CoreGen and the larger devices. Steve Norbert wrote: >could you tell me where i can download xilinx ise foundation (version >unimportant)? >i couldn't find anything in the web. on xilinx website i can only order >foundation evaluation kit, but shipping and handling charges amount $20 and >i'm a poor student ;) > >thanks for any help > >Norbert >kolek@interia.pl > > > >Article: 64077
Hi I was trying to program a digilent board featuring xilinx spartan 2E XC2S200E Fpga ...the problem lies with the pin naming. According to the digilaent manuals the pins are numbered from 1 to 208 where as the constraints editor in ISE 6.1 the PACE software names this same FPGA as A1,A2....etc to T16.... My problems comes as I donot know which pin is which so that i can perform some in/out operations with an expansion board. please help me with thius Thanks Paraag UNC CHARLOTTEArticle: 64078
User "Steve Lass" wrote: > Norbert, > > You can download the ISE WebPACK at: > http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=ISE+WebPack > > The main difference between WebPACK and Foundation is that WebPACK does > not include > FPGA Editor, CoreGen and the larger devices. > > Steve > i know that. the problem is that i have to have core and system generator, because they are necessary to install matlab/simulink xilinx dsp toolbox. i have to make project on the university using this toolbox and i don't want to work there, but at home.Article: 64079
I would also ask them to read very carefully the good white papers out of Xilinx and Altera that talk about efficient HDL coding styles for FPGAs. If you want performance, then coding for FPGAs is not the same as coding for ASICs. Gated clocks, latch inference, combinatorial feedbacks, product-term clocks etc are strict no-nos for FPGAs. "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:BrnCb.70495$Zj.20324@newssvr25.news.prodigy.com... > > It was easy to identify a culprit: almost all the conditional assignments > > are incompletely specified. > ... > > Anyway, I'm having problems describing to the design team why their coding > > style is incomplete, especially because they claim that it works perfectly > > in a back-annotated simulation. > > If your design team doesn't understand this I would be afraid, very afraid > to place a design of any significance in their hands. > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" > >Article: 64080
Has anyone given any thought to rocket IO testing. I have to write some test firmware and can't find any advice of the XILINX site. Lets assume that all my links go between FPGA's but that I don't want to have to control the transmitter and receiver as each FPGA is coupled to a different processor across a subrack. My best option seems to be to free run the transmitter with a clock correction packet, followed by a byte sync(Comma) followed by a 1024 byte packet( each byte from an LFSR) with CRC enabled. Each receiver can then throw away the data and check that it's getting the correct number of packets/second and that none of the many error flags (in particular the CRC of course) are getting set. In the long term it would be nice if I could control the transmitter at the same time so that I could force CRC errors and watch for them being received or turn off 8B10B for a while and plot BER against edge transitions so that getting a BER for the application becomes easier. Any suggestions or url's greatly appreciated. Rob DArticle: 64081
There is a product (Focus) from Fish Tail Design Autmation that does this. http://www.fishtail-da.com "Hans" <hansydelm@no-spam-ntlworld.com> wrote in message news:BPBBb.85$FN.37@newsfep4-winn.server.ntli.net... > Hi Muthu, > > I don't believe you will find a script to do this. However, static property > checkers like Averant's Solidify (www.averant.com) can autocheck for > multicycle path violations. > > Regards, > > Hans. > > www.ht-lab.com > > "Muthu" <muthu_nano@yahoo.co.in> wrote in message > news:28c66cd3.0312080539.703aff20@posting.google.com... > > Hi, > > > > Is there any script kind of, which can scan the RTL files and list out > > the Available Multicyle paths ? > > > > It is possible. Isn't it? > > > > Regards, > > Muthu > >Article: 64082
Norbert, ISE Foundation is over 1G bytes and we do not have a way to download it yet. The Eval is free, but we do charge shipping, which is about $6 in the US and around $20 international. If the school has the ISE CDs, maybe you could use those to install the eval (which is on the ISE Foundation CDs). If you have trouble with this, contact me directly to get an eval product ID. Another option would be to talk to a local FAE. They should have Eval CDs. Steve Norbert wrote: >User "Steve Lass" wrote: > > >>Norbert, >> >>You can download the ISE WebPACK at: >>http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=ISE+WebPack >> >>The main difference between WebPACK and Foundation is that WebPACK does >>not include >>FPGA Editor, CoreGen and the larger devices. >> >>Steve >> >> >> >i know that. the problem is that i have to have core and system generator, >because they are necessary to install matlab/simulink xilinx dsp toolbox. i >have to make project on the university using this toolbox and i don't want >to work there, but at home. > > > >Article: 64083
Hi, I am reminded of my British Literature class in high school, where (for a project) I built a castle out of scrapped MMI PAL's and a hot glue gun. I got a barrel of PALs for free. I can't tell you how many times I stabbed my fingertips with the DIP device pins while putting this together. Here's hoping your XC2000's are PLCC or SOJ!!! Eric > I hope you mean $.25/each or less. > > Use em for an art project, not a digital design. > -- > Nicholas C. WeaverArticle: 64084
Rob, We have a BERT core that provides for bit error rate testing, both generation of anything you want (8b10b, 2^n-1 patterns, XAUI stress, etc.) as well as registering the errors at the other end. When used with Chipscope Pro(tm), you save a few hundreds of thousands of dollars, and you can actually see what is going on, and really characterize your backplane. Please work with your local FAE to get the BERT designs (covered by an app note), as well as to get the characterization report which will also be useful to you. We have been able to walk into a "problem" situation, put the BERT core in place, cable the JTAG to a laptop, run Chipscope, and find and fix the problems in less than an afternoon. http://www.xilinx.com/bvdocs/appnotes/xapp661.pdf Austin rob d wrote: > Has anyone given any thought to rocket IO testing. I have to write > some test firmware and can't find any advice of the XILINX site. > > Lets assume that all my links go between FPGA's but that I don't want > to have to control the transmitter and receiver as each FPGA is > coupled to a different processor across a subrack. > > My best option seems to be to free run the transmitter with a clock > correction packet, followed by a byte sync(Comma) followed by a 1024 > byte packet( each byte from an LFSR) with CRC enabled. Each receiver > can then throw away the data and check that it's getting the correct > number of packets/second and that none of the many error flags (in > particular the CRC of course) are getting set. > > In the long term it would be nice if I could control the transmitter > at the same time so that I could force CRC errors and watch for them > being received or turn off 8B10B for a while and plot BER against edge > transitions so that getting a BER for the application becomes easier. > > Any suggestions or url's greatly appreciated. > > Rob DArticle: 64085
User "Steve Lass" wrote: > Norbert, > > ISE Foundation is over 1G bytes and we do not have a way to download it > yet. The Eval is free, but we do charge shipping, which is about $6 in the US and > around $20 international. > > If the school has the ISE CDs, maybe you could use those to install the > eval (which is on the ISE Foundation CDs). If you have trouble with this, > contact me directly to get an eval product ID. > Another option would be to talk to a local FAE. They should have Eval CDs. > > Steve I'll find out on wednesday if my university have ISE Eval CDs. I don't see anything unusal that somebody want to download 1gb. The various Linux distribution you can download from plenty of websites. they're over 1gb. NorbertArticle: 64086
I use foundation2.1i to do simulation. My design has passed functional simulation. There's only timing,i can't pass it.i don't know if it is static. one of the input data is synchronized with the clock,the other is a constant. how to synchronize the reset pulse in the testbench?Article: 64087
Hi Pierre, > So, what I was hoping to get is either suggestions about how I might > measure these delays, or, if someone has already measured/received > this information, the actual min:typ:max board delays between memory > and FPGA. I can't answer your question directly, but can offer a set of numbers (parameters and constraints etc) for the EDK-provided DDR controller that work on the v2mb1000 board... perhaps you can extract what you need from these? Regards, JohnArticle: 64088
Hi Paraag, Probably you have selected a FG package in your project and that on the board is a PQ208. Sandeep "paraag" <paraagv@hotmail.com> wrote in message news:39fdcd07.0312151502.2bae0032@posting.google.com... > Hi I was trying to program a digilent board featuring xilinx spartan > 2E XC2S200E Fpga ...the problem lies with the pin naming. According to > the digilaent manuals the pins are numbered from 1 to 208 where as the > constraints editor in ISE 6.1 the PACE software names this same FPGA > as A1,A2....etc to T16.... > > My problems comes as I donot know which pin is which so that i can > perform some in/out operations with an expansion board. > > please help me with thius > Thanks > Paraag > UNC CHARLOTTEArticle: 64089
Hi, Our LVDS Drivers failed when their power supply starts(it has soft start feature). On some boards only positive output or input of differential side failed (probably because of high current sourcing in failure mode). I checked power suppply yesterday and found some negative (-2.7v) but very narrow (200ns) spikes on power supply rail. I think it is one of the problems. LVDS drivers are from TI and spikes below -0.5 damage them. I look for more problem, e.g. grounding and ... here are some shematic of our system: LVDS+/- <-............3meter twisted-pair cable...............-> LVDS+/- GND ----------------------------------------------------------> GND regardsArticle: 64090
> Consider vcom and vsim from the command line, not from Quartus. > > -- Mike Treseler Hi Mike, ok let's consider vcom and vsim from the command line ... what does I learn from it? :o) Thanks. Kind regards Andre V.Article: 64091
"Jacques athow" <jaxlau@yahoo.com> wrote in message news:acc717b2.0312150350.29f7dd9e@posting.google.com... > I wanted to know which particular software from altera give support, > in terms of synthesis, P&R and downloading to this chip. Is the ALTERA > Max + Plus II suitable to program those chip? > > And also, it seems that the 10K50E part is an obsolete part that has > been replaced by the 10K50S. Is there any difference between them, in > terms of implementation and bitstream compatibility? > I've not used these parts for a while but I remember one or two things. Max+Plus II supports all 10K series (A,B,E,S...). For 10K50E I think you need a full version of Max+Plus II (the free web version only supports upto 10K30). For the programming files, you'll need to compile the design again for 10K50S. Best Regards ArashArticle: 64092
>My best option seems to be to free run the transmitter with a clock >correction packet, followed by a byte sync(Comma) followed by a 1024 >byte packet( each byte from an LFSR) with CRC enabled. Each receiver >can then throw away the data and check that it's getting the correct >number of packets/second and that none of the many error flags (in >particular the CRC of course) are getting set. Are you trying to check the connectors and wires on the backplane? The wires and solder joints on the board? Or do you want to burn-in test the whole design? If you are sending LFSR data, you might just as well check it bit-for-bit (byte-for-byte) at the receive end. You can do that on the other side of a recv fifo and such. If you copy/reuse that part of the logic from your real/main design, then you are testing that part of the design as well as that part of the on chip hardware. The catch is getting the LFSR generators in sync. That's easy if you feed the received data (good or bad) into the receive LFSR rather than feeding the LFSR output back to itself. This is often used for scramblers - called self-synchronizing. Works great. (The catch is that you get a multiple bit error for each error on the wire. The error pattern matches the 1s in the polynomial used in the LFSR.) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 64093
>I don't see anything unusal that somebody want to download 1gb. The various >Linux distribution you can download from plenty of websites. they're over >1gb. I'll echo that. Just put the iso images you used to make the CDs up on a web/ftp server. Lots of people have CD burners. 1 GB is ~10 hours on a DSL line. Not great, but many people would find it better than waiting for the postman. Many people, companies, and universities have faster links. Even if your line isn't fast enough, you may be able to horse-trade with somebody else. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 64094
>Hey, I'd really like to hear about your multilayer process! I have the gear >for 2-layer, but often just have them done by commercial shops. But, I >could be real interested in any innnovative laminating and plating processes >you use! > >Jon Hi Jon I recommend you then to join the http://groups.yahoo.com/group/Homebrew_PCBs group. There I posted the steps involved some weeks ago (search the archives). Besides, the group is really a very good place to start. If you have a trhough plating station (that's what I asume you mean with "I have the gear for 2-layer") then you are basically all set. If you don't have a trhough plating station then you definately will need one. MarkusArticle: 64095
Hello Sandor, have You already got the datasheet? I hava a double, paperback - weight 1.1Kg, XILINX - "The Programmable Logic Data Book 1994". Send me Your address via eMail and I send You the double. Donīt hassle about the antic pieces. We used those parts for evaluation on a demo board, at days when those parts were the most recent product. They worked very well, and besides all the advertising and advantages of new product families: The principle of FPGAīs did not change since the xc2064. No news, no big changes in technology - just big improvements in speed, size, on chip memory, usability, software ... But if You want to show the principle, You canīt afford the money for new chips and You want something improved instead of PALīs and standard logic those parts are fine!!! Three problems You should be really aware of: 1.) DO YOU HAVE SOFTWARE ??? 2.) DO YOU HAVE a HARDLOCK (dongle) working with it ??? 3.) DO YOU LIKE TO WORK IN DOS ENVIRONMENT ??? Up to date software does not support those parts, and You will have to work schematic based in DOS environment. Do not underestimate those problems, and if You still want the book - tell me. with best regards, Peter Seng ############################# SENG digitale Systeme GmbH Im Bruckwasen 35 D 73037 Göppingen Germany tel +7161-75245 fax +7161-72965 eMail p.seng@seng.de net http://www.seng.de ############################# "Sandor Jager" <sanyi@villamvadasz.hu> schrieb im Newsbeitrag news:aEQCb.55682$dt3.19182@news.chello.at... > Hi! > I've bought a lot of XC2018 (yes I know, antic pieces), > but they were very-veyr cheap, I've had no heart not to > get them :) > I'm looking for its complete datasheet, but I wasn't > able to find it anywhere on the net... > Has somebody got some point where to get it from, or > maybe has a pdf ?... > > Many thanx > Sandor JagerArticle: 64096
Hello
> B8 00 00 18 80 00 00 00 B0 00 7F FF B8 08 FF FF
> .
>
> when I look at sdram (after downloading) I see the following (unsigned char
> pointer used for reading out):
>
> 00 B8 18 00 00 80 00 00 00 B0 FF 7F 08 B8 FF FF
> .
I had the same problem, you have to swap each byte with the following:
Bytes in bin-File:
b1 b2 b3 b4 b5 b6 b7 b8 b9 b10...
Bytes to store in SDRAM / FLASH ..
b2 b1 b4 b3 b6 b5 b8 b7 b10 b9 ...
Here is a litte C-code fragment which does that:
for (i = 0; i < FRAME_DATA_SIZE/2; i++) {
data_frame.data[2*i+1] = *act_data++;
data_frame.data[2*i] = *act_data++;
}
act_data is a pointer to the bin file
data_frame.data[x] is the data to store in FLASH.
Greetings,
Reiner Abl
--
_____________________________________
www.rockmotion.de
Article: 64097Paraag, The user manual page 7 describes the mapping between the connector pins and the Spartan 2E pins. Will paraagv@hotmail.com (paraag) wrote in message news:<39fdcd07.0312151502.2bae0032@posting.google.com>... > Hi I was trying to program a digilent board featuring xilinx spartan > 2E XC2S200E Fpga ...the problem lies with the pin naming. According to > the digilaent manuals the pins are numbered from 1 to 208 where as the > constraints editor in ISE 6.1 the PACE software names this same FPGA > as A1,A2....etc to T16.... > > My problems comes as I donot know which pin is which so that i can > perform some in/out operations with an expansion board. > > please help me with thius > Thanks > Paraag > UNC CHARLOTTEArticle: 64098
"Reiner Abl" <diax_removethis_@gmx.de> wrote in message
news:oprz9omzsxzrls9e@news.online.de...
> Hello
>
> > B8 00 00 18 80 00 00 00 B0 00 7F FF B8 08 FF FF
> > .
> >
> > when I look at sdram (after downloading) I see the following (unsigned
char
> > pointer used for reading out):
> >
> > 00 B8 18 00 00 80 00 00 00 B0 FF 7F 08 B8 FF FF
> > .
>
> I had the same problem, you have to swap each byte with the following:
>
> Bytes in bin-File:
>
> b1 b2 b3 b4 b5 b6 b7 b8 b9 b10...
>
> Bytes to store in SDRAM / FLASH ..
>
> b2 b1 b4 b3 b6 b5 b8 b7 b10 b9 ...
>
> Here is a litte C-code fragment which does that:
>
> for (i = 0; i < FRAME_DATA_SIZE/2; i++) {
> data_frame.data[2*i+1] = *act_data++;
> data_frame.data[2*i] = *act_data++;
> }
> act_data is a pointer to the bin file
> data_frame.data[x] is the data to store in FLASH.
>
> Greetings,
> Reiner Abl
>
> --
> _____________________________________
> www.rockmotion.de
In meanwhile I can run an application from sdram. There was an error in the
byte selects of my sdram (I got an example which contains this bug). Longs
and words were written okay only bytes were swapped. The binary file I
created with mb-objcopy could be placed directly into sdram.
Anyway, thanks for your help.
Frank
Article: 64099> > The catch is getting the LFSR generators in sync. That's easy if > you feed the received data (good or bad) into the receive LFSR > rather than feeding the LFSR output back to itself. This is often > used for scramblers - called self-synchronizing. Works great. I was going to throw away the data because of the hastle in re-synchronizing but your suggestion makes instant sense. Many thanks.
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