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Hi, Is there any script kind of, which can scan the RTL files and list out the Available Multicyle paths ? It is possible. Isn't it? Regards, MuthuArticle: 63901
Can somebody help me in understanding few USB related queries? What is USB host controller? What is USB device controller? What is USB OTG controller? What are the different siuations which will make USB to generate interrupt? What are 'End points'? What is the meaning of 'OTG tranceiver in bi-directional mode'? What is the meaning of 'Non-OTG tranceiver in uni-directional mode'? What is transeiver? Thanx in advance -dathaArticle: 63902
Datha <dathathreya.bhat@wipro.com> wrote: : Can somebody help me in understanding few USB related queries? : What is USB host controller? : What is USB device controller? : What is USB OTG controller? : What are the different siuations which will make USB to generate interrupt? : What are 'End points'? : What is the meaning of 'OTG tranceiver in bi-directional mode'? : What is the meaning of 'Non-OTG tranceiver in uni-directional mode'? : What is transeiver? www.usb.org -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 63903
Hi, 1. Code size If your program only is in assembler and you don't use any libraries then the size is as you stated. Other stuff only gets added if you reference them. 2. BRAM You can share BRAM with instructions and data but the current BRAM_module will use 4 BRAM blocks in order to support byte-writes. You will have to modified to BRAM_module code to only support 1 BRAM but then you will not be able to handle byte or half-words since they require byte-write capabilities on the memory. Göran Bilski RISC taker wrote: >Hi! How much extra RAM (additional to the pure code size of the user >program) do I usually need for a MicroBlaze system?? > >I am considering MicroBlaze for a Spartan-3 project. Peripherals would >be a UART and my own memory mapped peripheral. Assuming that my >program can be compiled into less than 300 assembly instructions, it >should fit into one single BlockRAM, right? (300 * 32 bits = 9600 bits >< 18 KBits). > >Now what about data memory? My program wouldn't need much. Could I >squeeze that into the second half of the same blockRAM? Or is that >physically not possible? > >And most important: do the binaries get significantly bigger than just >the assembled functions? Is there any other stuff that gets compiled >into the program (UART stuff or whatever) that makes it big? > >Thanks a lot for your answers! > >Article: 63904
Ryan,
I ran the vmap batch file and compxlib per the instructions on
page 5 of the getting started guide. The problem is still there. I
went through the tutorial design (except for the programming into
hardware) and the tutorial design gives me 'Z' output. Any idea why?
Thanks again.
Matt
Ryan Laity <ryan_dot_laity@x-i-l-i-n-x_pleasenospam_dot_com> wrote in message news:<3FD11C4E.1010704@x-i-l-i-n-x_pleasenospam_dot_com>...
> Matt,
>
> It sounds to me like you haven't compiled the EDK behavioral model
> libraries. If that's the case then check out the "Behavioral Model
> Libraries" section on page 5 of the "Getting Started with the EDK"
> document ($EDK/doc/edk_getstarted.pdf) for the instructions.
>
> Best regards,
> Ryan Laity
> Xilinx Applications
>
> Matt wrote:
> > I need help....I installed Xilinx 5.2 SP3, EDK 3.2 SP2 and ModelSim
> > 5.7b. After running through the compxlib and vmap to setup the
> > libraries for Modelsim, I went through the Microblaze tutorial. I
> > completed the tutorial up to downloading the design to hardware. I
> > skip over to the simulation section and recompiled the microblaze with
> > the simulation.c code. When I run the behavioral simulation, the
> > output from the microblaze is Z's. WHat am I doing wrong???
> >
> > Confused,
> > Matt
Article: 63905toby <toby@toby.com> wrote in message news:<iffAb.33264$5s6.9670@newssvr29.news.prodigy.com>... > > `define MAXIMUM3(x,y,z ) ( (`MAXIMUM2(x,y)>z) ? (`MAXIMUM2(x,y)):(z) ) Note that this could be written more compactly as `define MAXIMUM3(x,y,z) `MAXIMUM2(`MAXIMUM2(x,y),z) but this may be even less likely to work, since it involves a macro appearing in a macro argument, not just the expansion text. > This barfs on most of the above... I will check the most recent NC-Verilog and file a bug report if necessary. Incidentally, macros with arguments were added in Verilog-1995, not Verilog-2001. However, a lot of tools probably didn't support them until they started implementing the Verilog-2001 extensions. The standard does not specify whether macros can be nested (i.e. whether the text expansion of a macro is subject to further substitution), but it seems like a reasonable thing to expect.Article: 63906
Pratip Mukherjee <pratipm_nooospam@hotmail.com> wrote in message news:<Xns944AE74DDA1B2pratipmnooospamhotma@216.148.227.77>... > Hi, > I am trying to use AVRCore project from opencores.com on ACEX1K100-3 FPGA. > Timing summary tells me that maximum clock is 11.xxx MHz. Since my external > clock is 40MHz, I inserted a divide by 4 counter before feeding it to the > CPU clock. But Quartus still says that max. clock is 11.xxx MHz. How's > that, shouldn't it be now 44.xxx MHz, assuming the input counter can count > to 44MHz. I am not using the input clock for any other purpose than > dividing by 4. > Another related question. ACEX1K datasheet says that the -3 devices do not > have PLL. But Quartus always reports 0 of 1 PLL used, even when I > specifically select -3 device. Which one is right, datasheet or Quartus? > Thanks in advance. Consider asking this question in the proper forum: comp.arch.fpga. -aArticle: 63907
Petter Gustad <newsmailcomp6@gustad.com> wrote in message news:<87d6b0fsk7.fsf@filestore.home.gustad.com>... > Is it possible to run nios code from flash memory directly (assuming > I'm running at only 10MHz)? Or do I need a small bootstrap in local > rom to jump to the flash address? > > Most existing designs I've seen have use an external ram and bootstrap > by copying code from the flash to the ram prior to branching to the > start address. > > I tried a quick simulation. The only inputs I have to the nios cpu is > clock and reset. I don't see that it's trying to put the flash address > out on the bus. > > Petter Hi Petter, I just tried this with my Nios Stratix (1S10ES) board and was able to boot out of flash using a slightly modified "standard_32" design. The steps I took were to: 1. In SOPC Builder's software settings for my Nios CPU: Modified the boot & program memory to be flash, and the data memory I left in SRAM (obviously, data memory must be volatile and writable by the CPU!). 2 Re-generated the system in SOPC Builder & re-compiled in Quartus. 3. For flash memory contents, I compiled a simple program (hello_world.c) and used the srec2flash utility to get a flash programming file suitable for the GERMS monitor to write into flash. However, I had to modify this file slightly, as srec2flash normally has a flash copier routine to support users who want to boot up, copy their program to SRAM/SDRAM, and then execute from the faster memory. Basically I just removed the first part of the file and left the GERMS erase & relocate commands before the S-record data for my hello_world application. 4. Loaded a design that boots with the GERMS monitor, and loaded the above .flash file to get my code in place. 5. Downloaded the new .sof file that has Nios booting from flash -- success. On your simulation problem: My guess here would be that you don't have a simulation model for flash memory. This is an optional step in SOPC Builder when you add flash to your system -- in the GUI where the flash is instantiated, there is a simulation contents page which you can use to create memory contents for simulation. By default I believe this is left to 'do not create simulation model'. If you would like I'd be happy to email you the design I used in the above steps. Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 63908
"Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message news:<3fd47b9d$0$14041$fa0fcedb@lovejoy.zen.co.uk>... > > I *did* set the reset address to the flash base. The nios supplied > > flash ip has an 8-bit interface only. However, I was hoping to see > > that it would try to do a read at address 0 (the flash base address > > and reset location) to fetch the first instruction. My plan was to try > > to make a new ptf file for a 16-bit flash interface and run a 16-bit > > nios directly from this. > > Petter > > That seems odd, I would have thought that the program counter > would reset to whatever value you set it to, and that this is > the first address it would try to access. > > Let us know what's happening if you suss this out. > > > Nial > > ------------------------------------------------ > Nial Stewart Developments Ltd > FPGA and High Speed Digital Design > Cyclone PCI development/eval board > www.nialstewartdevelopments.co.uk I just finished a NIOS project that had a loader locates at one memory location and application code located at another location. When you define the CPU you set restart and flash locations. THat produces excalubur.h and excalibur.s files which are used in the building process to defince startup locations. I build both examples in the NIOS CPU definitions and then looked at the differences. I now just edit the excalibur.s,h files (with a batch file) for the different start up locations. The loader is executed on power up. Then is no activity takes place in 5-10 seconds the application start location is called. This proceedure violates a lot of C conventions but it works. GoergeArticle: 63909
Pratip Mukherjee <pratipm_nooospam@hotmail.com> wrote in message news:<Xns944AE74DDA1B2pratipmnooospamhotma@216.148.227.77>... > Hi, > I am trying to use AVRCore project from opencores.com on ACEX1K100-3 FPGA. > Timing summary tells me that maximum clock is 11.xxx MHz. Since my external > clock is 40MHz, I inserted a divide by 4 counter before feeding it to the > CPU clock. But Quartus still says that max. clock is 11.xxx MHz. How's > that, shouldn't it be now 44.xxx MHz, assuming the input counter can count > to 44MHz. I am not using the input clock for any other purpose than > dividing by 4. > Another related question. ACEX1K datasheet says that the -3 devices do not > have PLL. But Quartus always reports 0 of 1 PLL used, even when I > specifically select -3 device. Which one is right, datasheet or Quartus? > Thanks in advance. > > Pratip Mukherjee Purely a point of view issue. Quartus is stating that you better not go faster than 11.xxx. If you put the divide by 4 external to the FPGA I'm sure you would be ok. If you can guarantee you seperated the clocks then I'm also sure your OK. One way is to put the 44.xxx into one clock input and divide then that the output and wire it external to the FPGA into the other clock input. GeorgeArticle: 63910
karlIGNORETHISPART@chello.nl (Karl) wrote in message news:<3e83178d.0312050420.6b7201a0@posting.google.com>... > fredrik_he_lang@hotmail.com (Fredrik) wrote in message news:<77a94d51.0312040505.76d6e2cf@posting.google.com>... > > jwing23@hotmail.com (J-Wing) wrote in message news:<d6e7734d.0312020835.42729684@posting.google.com>... > > > The NIOS processor runs on a 33.333MHz clock. How can I increase the > > > speed of the clock and what is the maximum speed which can be > > > achieved? Please advice. > > Hi, > > One way of achiving this would be to remove the Y1 clock source and > > put a faster one on to this.(You need to check the schematics for > > pinning). Second question you can always check in the timing analys > > for fmax of your design, if I rember correctly you should be able to > > get 50-70MHz depending on design. (You need to change target freqency > > in the SOPC builder also). > > Cheers > > Fredrik > > Hi, > > Did some playing around with the Nios V3.1 in the APEX 20K200E and > could get 74 MHz with a small 16 bit core, 2 KByte on-chip memory and > a UART. Any bigger system will have lower performance. > > Karl. If you're doing a one of a kind (not productions) then I would ask Altera the map for speed vs Voltage, temp amd processing. If you raise the voltage you'll go faster, If you lower the temperature you'll go faster. If you select parts for speed you'll go faster. Altera map should show you how much you can gain. GeorgeArticle: 63911
kempaj@yahoo.com (Jesse Kempa) writes: Hi Jessa, thank you for your reply. > I just tried this with my Nios Stratix (1S10ES) board and was able to > boot out of flash using a slightly modified "standard_32" design. The > steps I took were to: My explanation was probably a little unclear: I would like to set the reset vector to point to a flash location and run the code directly from the flash. In order to save some money and board space I wanted to run a flash in 16-bit mode and use a 16-bit NIOS CPU and feed the instruction stream directly from the flash. In other words I don't want to boot out of the flash, I want to execute code from it directly. I just can't see how you can do this on the NIOS Development Kit Stratix Edition since it only has an eight bit datapath to the flash (if we're talking about the same board). Take a look at page 6 of: $NIOS_DIR/documents/nios_stratix_1s10/nios_1s10_board_schematic.pdf Hence you'll have to read the flash contents into either a pipeline register, on-chip ram, the sram or the rdram on the board prior to execution. Some flash memories (not the one on the in the development kit) have an optional pin (xbyte) which selects byte or 16-bit mode. > On your simulation problem: My guess here would be that you don't have > a simulation model for flash memory. This is an optional step in SOPC I do. I downloaded a flash model from AMD. I've also written my own testbench which instantiate the design and the flash (so there's room for errors here). The thing is since the *only* inputs to the design are clk and reset I expected to see that it would at least output the flash address on the bus shortly after reset. The next step would have been to convert the srec file for the flash to commands to write the flash before I release reset to the nios cpu (the flash model does not have readmem to init the flash for simulation). However, I haven't spent very much time debugging this. I posted the message to see if anybody had done this already. Most likely there is a bug in my testbench etc. It could also be that I'll have to write my own ptf file for a 16-bit flash in order to make this work since the flash ip provided is an 8-bit part only. BTW: 1) Is it possible to run the plugs library on a 16-bit nios cpu? 2) Is it possible to use the plugs library without an uart? see news:<m3brtht54l.fsf@scimul.dolphinics.no> Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 63912
When you use the -lw option for your application you link in the system call library for xilkernel. This library provides functions such as process_create, thread_create, send_message, etc. (see docs for exact function names). When you invoke one of these functions, control goes back to the xilkernel executable which does the necessary bookkeeping actions and returns to your app. The xilkernel info in your MSS files causes an executable called xilkernel.elf to be created if you specify the multi-elf-file mode (the default mode). I would expect the bootloader to load this elf - "xilkernel.elf" into memory, and let xilkernel.elf automatically load the "app" by specifying the app's start address in the process table parameter in the MSS. If you build the bootloader as an "executable" and xilkernel.elf using the default mode (xmdstub), the overall memory map looks like this: 0x0: reset vector, interrupt and exception handler jumps -- 6 words -- -- xmdstub code for xilkernel.elf or bootloader code for bootloader-- 0x400: xilkernel.elf code starts here -- approx 10K of xilkernel code depending on selections -- 0xA0000000: Application code starts here So if the bootloader code is smaller than the 0x400 bytes, there should be no problem directly loading the xilkernel code. Otherwise, you could force the xilkernel.elf code to start at a higher address by modifying the linker script or the make file that creates this elf file. Hope this helps, MohanArticle: 63913
Hi, I have an Altera FPGA, which shows hold violation on an input pin. The first FLOP is positive edge triggered and in IOB. To get rid of the roughly 2 ns margin in hold, i put -3ns phase shift in clock output of PLL that clocks the input register. Apparently this was ignored in hold time calculation. Can someone point out why ? A negative shift in clock should have made hold time better in this case. ShardenduArticle: 63914
Fred H wrote: > > Using Xilinx ISE 6.1i, FPGA Editor, it is possible to > edit different aspects of the design implementation > directly in the .ncd-file after finishing P&R. > > Say you have a huge design, that takes forever to run > P&R on, is it then possible to make small changes in > the .ncd-file, using the FPGA Editor, and then either > generate programming files or create a simulation model > of it, without running P&R first? Yes, you can make changes in FPGA Editor, then use that NCD for timing simulation or bitstream generation. Of course, changes will not be back annotated into your source for the next time you compile. > The changes I'm talking about, is moving pin-locations, > moving components between slices and last but not least, > editing PULLUP/PULLDOWN on pins. I know I can do this in > the .ucf og .pcf files, but then I will definately need > to rerun P&R, and I want to avoid that. > > I trid to introduce PULLDOWN on a pin in a test design > just now, and after I did that, I generated a new Post > P&R sim model, and ran Modelsim. But nothing happened. > > Then I noticed that the file I was actually editing when > I had double clicked "View/Edit Routed Design (FPGA Editor)" > under the "Place & Route" node in Xilinx Project Navigator > was the map_<filename>.ncd file, and not the <filename>.ncd. > So I trid to open the <filename>.ncd directly from FPGA Editor, > and did the changes there. When I then generated the new > Post P&R sim model, I got this warning: > > WARNING:Anno:13 - The .ncd is out of sync (not logically equivalent) > with the > .ngm; therefore, an .nga will be created from the .ncd. > > I have tried to find out what this actually means, but I'm new > to this, so I haven't figured it out yet. The NGM is a cross reference file that the mapper creates. It is used when a simulation model is created to make the net names and hierarchy match the input netlist as much as possible (for easier debugging). When you change the NCD in FPGA Editor, the NGM is out of sync, so the tools do not attempt to match the input netlist; they just create a simulation netlist from the new NCD. It sounds to me like you are doing the right thing and your pulldown should work. Steve > Anyway, when I then > started the post P&R simulation with Modelsim, the PULLDOWN > was in effect. > > When I tried to generate programming files, I could do that wihtout > any warnings. But since I havent actually downloaded my code to an > FPGA, and meassured the voltage on the actual pin, I'm not really > sure weather my modification works or not. > > If anyone has had experience with doing this kind of modifications > without rerunning P&R, I'd like to hear about it. But any comments > are welcome :-) > > Sincerely > -FredArticle: 63915
Dear all, I implement a DMA controller in the PLD side of the ALtera's excalibur device(epxa1), and a block ram in the PLD other. DMA controller access data through the PLD-to-STRIP bridge. I config the DMA controller through STRIP-to-PLD bridge. now I need to exchange datas between the sdram(out of chip) and the RAM in PLD. It seemed that some datas not translated successly, there would be eight continual beats failed every since. while other datas sucessful, and there would be eight continual beats as well. The DMA controller was designed refer to ALtera's "AN 287: Using Excalibur DMA Controllers for Video Imaging ". I dont confirmed the AN287 is ok, I thinked it's worked well. In the other hand, If the DMA controller exchange between the SPRAM(single port RAM on chip) and the block ram in the PLD, the DMA controller worked very well. The timing and function simulation is successed as well. I think if there were some bugs in the excliabur device. The above sympton seemd is related with the SDRAM' controller or the AHB BUS. because THE HARDWARE REFERENCE MANUAL's SDRAM section said "Transfers to the memory are made up of eight-beat reads and writes. A request from the system bus that does not map directly to this fixed-beat access(for example, A larger burst size or a wrapping transfer) is handled by performing multiple accesses. Burst termination is utilized to maximize throughput." regards algousArticle: 63916
The PLL report for the ACEX1K -3 is a bug. This device does not have a PLL, and this is a reporting bug which has been fixed in the next version of Quartus. Without seeing your design, the best I can say for the timing problem, is that you need to tell Quartus of the relationship between your 10Mhz derived clock and the 40 MHz external clock. You can do this using the Assignment Settings->Timing Requirements and Options Dialog. The steps are as follows, based on the assumption that your incoming 40 Mhz clock is clock40. 1. Open Assignment Settings->Timing Requirements and Options Dialog 2. In the Clock Settings Group select the Settings for Individual clock signals. 3. Click on the New button to define the new clock. 4. Fill in the entries in the New clock settings dialog. Set the clock settings name to clock40 (for ease of use) and the "Applies to node" should be selected to be the pin from the Node finder. The "Relationship to other clock settings" should be set to "independent of other clock settings". The fmax should be 40Mhz. Hit OK to close the New clock settings dialog box. 5. Next define the 11 MHz clock based on the output of the divide by 4. Click on the New button to define clock10. 6. Set the clock settings name to clock10. The Applies to node should be the output of the register that is the 10MHz signal. The "Relationship to other clock settings" should be set to "Based on" clock40 (defined in step4). Click on the Derived Clock Requirements, and fill in the Divide base clock field.Hit OK, and close all the dialogs. 7. Compile the design. Hope this helps - Subroto Datta Altera Corp. "Pratip Mukherjee" <pratipm_nooospam@hotmail.com> wrote in message news:Xns944AE74DDA1B2pratipmnooospamhotma@216.148.227.77... > Hi, > I am trying to use AVRCore project from opencores.com on ACEX1K100-3 FPGA. > Timing summary tells me that maximum clock is 11.xxx MHz. Since my external > clock is 40MHz, I inserted a divide by 4 counter before feeding it to the > CPU clock. But Quartus still says that max. clock is 11.xxx MHz. How's > that, shouldn't it be now 44.xxx MHz, assuming the input counter can count > to 44MHz. I am not using the input clock for any other purpose than > dividing by 4. > Another related question. ACEX1K datasheet says that the -3 devices do not > have PLL. But Quartus always reports 0 of 1 PLL used, even when I > specifically select -3 device. Which one is right, datasheet or Quartus? > Thanks in advance. > > Pratip MukherjeeArticle: 63917
In this case rename your vhd file which contains the testbench to the .vht extension using the Windows Explorer or DOS prompt. - Subroto "ALuPin" <ALuPin@web.de> wrote in message news:b8a9a7b0.0312072313.3cd8ecc@posting.google.com... > "Subroto Datta" <sdatta@altera.com> wrote in message news:<JYaAb.3672$2C5.2593@newssvr33.news.prodigy.com>... > > http://www.altera.com/support/software/nativelink/quartus2/glossary/def_vht. > > html > > > > - Subroto Datta > > Altera Corp. > > > > > > > > > > A VHDL Test Bench File is the same as a standard VHDL test bench file, saved > > with a .vht extension. > > > > > Hi, > > yes I read about it in the handbook, but HOW can I save a .vhd file as > a .vht file? > > When I write a testbench file I can only save it as .vhd ! ? > > Thank you.Article: 63918
Hi all, I'd like to highlight a problem encountered while using the Xilinx foundation series 4.1i. I am unable to connect all the input ports to the respective output ports due the following comments shown: Too many signals: Checking for sourceless, loadless nets and multiple drivers aborted. I suspect that there is a limit to the number of bus terminal labels that we can give on a schematic. The bus terminal labels are given to the inputs and outputs ports so that they need not to be physically connected with wires. These termianl labels are essential as it is impossible to physically connect the ports together with wires under the constraint of the space given in the schematic. Any idea how to solve the problem ??? Thanks. BuzzArticle: 63919
Well, that's totally different from what I thought it's working. Okay, I saw that the xilkernel executable is created and also an bootloader executable. Besides I have an application executable. If I understand everything, I have to run the bootloader (which is done automatically, because it's beginning at address 0) located in BRAM. With this bootloader I should download the xilkernel executable and put it in memory. Because the process_table parameter in the MSS file is specified, the kernel wants to start a process (which is my application), so I have to download first the application to 0xA0000000 and then the xilkernel to 0x400. Is that correct?! How to start the application if the process_table parameter is not specified? Jump to application and do a process create here?! By the way, my bootloader exceeds the 0x400 bytes, thus I have to put the xilkernel at a higher address by using a linkerscript. Can I put it also in external memory? And how to start up the xilkernel when downloaded into external memory, just jump to the start address of it? Does the xilkernel contain startup code for initializing data, stack etc.? (I guess the answer is yes, because a disassembly of the .elf file shows me there is a _crtinit). My application does also contain startup code for initializing data, stack etc, doesn't it? How is this working? Are there different stacks (one for xilkernel and one for application)? My last question is about getting the xilkernel starting at external memory (if possible): how to easilly change the common makefile (common for bootloader and xilkernel) or linkerscript to let the bootloader start in BRAM and the kernel start at external SDRAM?! Do you have any examples?! A lot of questions again, hopefully you can make it clear for me. TIA, Frank "mohan" <mohan@xilinx.com> wrote in message news:3FD4EE73.F5C7F556@xilinx.com... > When you use the -lw option for your application you link in the system call library for xilkernel. This library provides functions such as process_create, thread_create, send_message, etc. (see docs > for exact function names). When you invoke one of these functions, control goes back to the xilkernel executable which does the necessary bookkeeping actions and returns to your app. > The xilkernel info in your MSS files causes an executable called xilkernel.elf to be created if you specify the multi-elf-file mode (the default mode). > I would expect the bootloader to load this elf - "xilkernel.elf" into memory, and let xilkernel.elf automatically load the "app" by specifying the app's start address in the process table parameter in > the MSS. > If you build the bootloader as an "executable" and xilkernel.elf using the default mode (xmdstub), the overall memory map looks like this: > 0x0: reset vector, interrupt and exception handler jumps > -- 6 words -- > -- xmdstub code for xilkernel.elf or bootloader code for bootloader-- > 0x400: xilkernel.elf code starts here > -- approx 10K of xilkernel code depending on selections -- > > 0xA0000000: Application code starts here > > So if the bootloader code is smaller than the 0x400 bytes, there should be no problem directly loading the xilkernel code. > Otherwise, you could force the xilkernel.elf code to start at a higher address by modifying the linker script or the make file that creates this elf file. > > Hope this helps, > MohanArticle: 63920
Hmm I was thinking about the meaning of "high performance" a bit while walking to my doctor's appointment (dang wife borrowed the car today, and she's always right). An FPGA design doesn't have to be high performance, relative to similar products, in order to require intimate knowledge and use of a specific FPGA architecture. What matters is how much performance you need, relative to the performance that the FPGA can provide without much design effort. Since most commercial projects are price conscious, we're usually picking the cheapest FPGAs that don't cause us too much pain. Instead of paying the recurring cost of a more expensive bill of materials, management prefers spending a little more on design effort which only has a one time cost...well that's not totally true since there are hidden costs in choosing cheaper FPGAs that are harder to work with...but decissions are usually made on the more immidiate and visible costs. So more often than not, we have to sacrifice vendor independence in order to squeeze more performance out of cheaper parts. VinhArticle: 63921
Thanks a lot for your help. Best regards, Arkaitz. Peter Alfke <peter@xilinx.com> wrote in message news:<3FD10E63.5947DE27@xilinx.com>... > There is a nifty trick: > If you need several single-port memories of up to 8Kbit size each, then > you can put two of them into one dual-port RAM, if you make sure that > the two ports never address the same RAM space (Make one port's MSB > High, the other one's MSB Low. > If you think about it, you can of course take any other address bit > position and drive it permanently High for one port, Low for the other. > And you can even divide the RAM in a not-50-50 manner, but that requires > slightly more complex addressing control. > > Peter Alfke > ============ > John_H wrote: > > > > Your tools may combine two single port memories into one dual-port if the > > memory sizes are compatible. By instantiating the dual-port, you no longer > > have the option of the combination. The tool flow you use may not take > > advantage of this packing anyway, so the point might be moot. > > > > Check what your BlockRAM usage is - see if the tools are already > > implementing two single-port memories in a dual-port. As long as the total > > number of BlockRAMs you infer and instatiate fit within the available number > > of BlockRAMs for the device, you're set. > > > > "arkaitz" <arkagaz@yahoo.com> wrote in message > > news:c1408b8c.0312050623.52b9b1fa@posting.google.com... > > > Hi all, > > > > > > I am working with a 1 million gate Virtex II FPGA. I am instantiating > > > large amounts of Block RAMs in my design and even though I am using > > > Single-Port ones, I would like to know if there would be a trouble to > > > instantiate them as Dual-Port ones. I mean, would it need twice the Block > RAMs > > > I am using now, or would it just configure them as Dual-Port? > > > > > > Thanks, > > > > > > Arkaitz.Article: 63922
"Vinh Pham" <a@a.a> writes: <snip> > So more often than not, we have to sacrifice vendor independence in order to > squeeze more performance out of cheaper parts. > Indeed - and no different to a lot of embedded software. Some will be in "vendor-specific" assembly, or even if in C, the low level stuff is not trivially portable! I wonder if the difference is that in FPGA space there is a very limited choice of vendors, so some people may think that it is reasonableo t aim for vendor independance, whereas in the embedded processor space there are many more choices, so its clear you'll never cover them all! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 63923
Thanks Alan for the help. The thing is that I have been looking for it in a manual that mentions that isn't possible to assign different direction buses in one instruction. I've tried and it works, so thanks again. Best regards, Arkaitz. "Alan Fitch" <alan.fitch@doulos.com> wrote in message news:<bqpk9o$p7t$1$8302bc10@news.demon.co.uk>... > > Hi all, > > > > It might be an obvious question but I have a doubt when assigning > two buses > > that are defined with opposite direction. > > > > Here you are an example; > > > > architecture behavioral of buses is > > signal bus_a: std_logic_vector (0 to 7); > > signal bus_b: std_logic_vector (7 downto 0); > > ... > > begin > > > > -- this doesn't work > > bus_b <= bus_a; > > > > > What do you meant "it doesn't work?". It works fine! In > VHDL vectors are assigned left to right, *regardless of how > they are declared*. So that code says > > bus_b(7) <= bus_a(0); > bus_b(6) <= bus_a(1); > bus_b(5) <= bus_a(2); > bus_b(4) <= bus_a(3); > bus_b(3) <= bus_a(4); > bus_b(2) <= bus_a(5); > bus_b(1) <= bus_a(6); > bus_b(0) <= bus_a(7); > > Which looks fine to me. That's how VHDL works... > > > -- but don't know why this doesn't work > > process (bus_a) > > begin > > for i in bus_a'range loop > > bus_b (i) <= bus_a (i) > > end loop; > > Again, what do you mean "it doesn't work"? > > bus_a'range gives you "0 to 7", so the loop results in > > bus_b(0) <= bus_a(0); > bus_b(1) <= bus_a(1); > ... > bus_b(7) <= bus_a(7); > > which again works fine. Of course it does something different > from your first example... > > > > > -- this works > > process (bus_a) > > begin > > for i in bus_a'range loop > > bus_b(i) <= bus_a (bus_a'left - i); > > end loop; > > end process; > > > > This does > bus_b(0) <= bus_a(0-0); > bus_b(1) <= bus_b(0-1); -- error! > > so should not run. It should give a "index out of range error". > You may only see that at run time however, not at compile time. > > > Does anybody have any idea why the second example doesn't work? > > > > I believe your first two examples "work", and the last example doesn't > because of the indexing error. > > What exactly are you trying to achieve? > > kind regards > > Alan > > > > -- > Alan Fitch > Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project > Services > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 > 1AW, UK > Tel: +44 (0)1425 471223 mail: > alan.fitch@doulos.com > Fax: +44 (0)1425 471573 Web: > http://www.doulos.com > > The contents of this message may contain personal views which are not > the > views of Doulos Ltd., unless specifically stated.Article: 63924
Hi ! In the spartan datasheet I can read that: "Horizontal routing resources are provided for on-chip 3-state busses. Four partitionable bus lines are provided per CLB row" What does partitionable mean in this case ? Does this mean the horizontal lines can be divided ? If so, where (how many) the division points are there ? Is FPGA Editor removed from ISE6.1i ? I've recently used 6.1i at my university, and couldn't find it :(
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