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Hi all, I'm currently trying to use ChipScope (5.2i) to verify the functionality of my OPB slave on a Virtex2 running Microblaze. Either I'm not very good at understanding how to use ChipScope, or the program itself is behaving fishy. However, the following scenario occurs: Currently I'm just using the lmb bus address strobe signal as trigger and it seem to work fine on its own, but as soon as I add the lmb addr bus a data bus in ChipScope the waveforms for the strobe signal won't show at all, even though it still triggers on it. Note that I use these signals just to learn how to use the program on a system that I know works, i.e. without my own core added so far. Does anybody have a solution to this problem, or any other tips and trix regarding ChipScope in general? /JohanArticle: 62326
John Larkin wrote: >Well, we've probed it with a 1 pF, 1 GHz fet probe into a TDS3052 (500 >MHz) scope, and CCLK still looks beautiful. Maybe I should try the 3 >GHz sampling probe next! The 68332 port edge is pokey enough that we >wouldn't expect much ringing on a short trace, and we've done much >longer and nastier multiple-FPGA configs without problems. > > What about setup time between Din and CCLK? Loading down CCLK also will delay it a nS or so, and that may be enough. Maybe previous version of this had some other loads on CCLK that slowed it down, so you never saw this problem before. JonArticle: 62327
You run the state machine of you controller on negedge of clk and SDRAMs sample data of posedge of clock. Sumit george_mercury@hotmail.com (George) wrote in message news:<6d167a0a.0310260419.50c5076d@posting.google.com>... > Hi! > I am a bit new to FPGAs, so far I have only worked with CPLDs ( Xilinx > 9500 family ). Now I would like to use a Spartan 2E ( with WebPack 5.2 > and VHDL ) to make a SDRAM controller. > > I have searched this archive but I haven't found any topic related to > my question. Here's the deal. When data needs to be transfered to the > SDRAM the controller sends out data prior to generating the rising > edge of the SDRAM's clock. So the way I see it, the fpga must generate > two clocks, one for the controller and one for the SDRAM. The SDRAM > clock must be by 90° out of phase of the controller clock ( the SDRAM > clock must be delayed for 1/4 of the cycle of the controller clock ), > in order for data to appear on DQ lines before the rising edge of > SDRAM's clk. I am right so far, or am I way off? And If I am right, > how do you generate the SDRAM clock ( do you use a DLL to phase-shift > the input clock ? ). > > Best regards > George MercuryArticle: 62328
Hello, I have a large design implemented in Verilog. In the design there are several thousand SRL16 type shift registers that are inferred from the Verilog by XST. What is the best way to initialize each shift register with different a unique value? Preferably this initialization could be specified outside of the verilog so that thousands or different module definitions are not needed. I also am using all 96 block rams on the XC3S4000 and need to initialize those as well. Currently I am initializing the block rams in the module where they are instantiated but for the final design I need this to be seperated from the Verilog module definition because I don't want to have 96 different module definitions. Thanks, Matt HardyArticle: 62329
Pressing headers does not help. I know that i need sometimes to reset (clear all messages) and redownload headers in OE. That is why I've considered missing messages as another bug. Actually, the problem is bad newserver as mikhail mentioned.Article: 62330
george_mercury@hotmail.com (George) writes: > Hi! > I am a bit new to FPGAs, so far I have only worked with CPLDs ( Xilinx > 9500 family ). Now I would like to use a Spartan 2E ( with WebPack 5.2 > and VHDL ) to make a SDRAM controller. > > I have searched this archive but I haven't found any topic related to > my question. Here's the deal. When data needs to be transfered to the > SDRAM the controller sends out data prior to generating the rising > edge of the SDRAM's clock. So the way I see it, the fpga must generate > two clocks, one for the controller and one for the SDRAM. The SDRAM > clock must be by 90° out of phase of the controller clock ( the SDRAM > clock must be delayed for 1/4 of the cycle of the controller clock ), > in order for data to appear on DQ lines before the rising edge of > SDRAM's clk. I am right so far, or am I way off? And If I am right, > how do you generate the SDRAM clock ( do you use a DLL to phase-shift > the input clock ? ). > Xilinx have an appnote on this. And Altera also. As for me, assuming you're talking about single data-rate: I just ran my state machine off the same clock as the SDRAMs. If you drive the data on the rising edge, it won't appear on the outputs until some time later (about 6/7 ns IIRC for my chip), so the SDRAM will then latch it in on the *next* clock cycle. No need to faff about generating mutplile clock domains, using negative edges or any of the other nasties. Just make sure the latency in whatever is provding the data is right. Micron provided good VHDL models to get the simulation right - much easier than wiring up a logic analyser! If you're doing DDR, ignore me :-) HTH, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 62331
I'm using an Altera ACEX1K and can't find the condition of the IO-Pins during configuration and initialisation of the FPGA ??? Can there be an input on the IO-Pins during configuration and initialisation ??? Especially can there be a clock on GCLK0-Pin during configuration and initialisation ??? Thanks, ManfredArticle: 62332
"Manfred Balik" <e8825130@stud4.tuwien.ac.at> writes: > I'm using an Altera ACEX1K and can't find the condition of the IO-Pins > during configuration and initialisation of the FPGA ??? > Can there be an input on the IO-Pins during configuration and initialisation > ??? > Especially can there be a clock on GCLK0-Pin during configuration and > initialisation ??? > Thanks, Manfred > I've had running clocks on a 10KE during configuration without hassle. The ACEX is very similar as I understand it. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 62333
Hi all, I am trying to implement an LCD driver in FPGA which will drive a 320x240 color LCD (digital 18bit parallel input). Could you please read below and comment if my way if thinking is correct or not. For two virtual screens to be stored in memory I need 2x320x240x18 bits = 150k x 18 bits of memory. And this seems impossible with Spartans' block ram. So I need an external memory. At first I tought that I need a dual port SRAM since a host will write to the video memory and the driver will continuously read from that memory and feed the LCD. But these RAMs seem to be overpriced (Arrow says hundered something dollars for 4mbit memory) Then I realised that at 60 Hz driving frequency I only need ~8 Mhz clock. Is it possible to use a faster main clock (like 50-60 Mhz maybe) and still feed the LCD at 8 Mhz and in the remaining time fulfill the memory read/write commands given by the host asynchronously? If that is true I need a memory capable of achieving around 60Mhz. I found the NoBL (or ZBT)SRAMs from Cypress and IDT which can go up to 166 Mhz and gives me full bw utilization. (no wait cycles b/w read and write). And the good thing is that they also come in x18 organisation which is just what I need! Digikey says ~$9 for 256kx18 100 MHz ZBT SRAM. Is that memory suitable for my needs or would you recommend any other memory? Thanks in advance AntonisArticle: 62334
Hello all, I'm learning to use JBits and I want to verify the bitstream I produce. I have seen that an application called BoardScope can do that, but I'm unable to find this app. Can you help me ? I precise that BoardScope is not yet given with JBits package. Thank you and sorry for my english Barthélémy von HallerArticle: 62335
I did an electronic dice game ( 3 die ) program in VHDL. Basically , the program has 216 different dice values combinations which was simply assigned by me. The dice has 3 segment displays . I defined the 3 displays as output " seg " . However , I can't figured out any idea to write this electronic dice ( 3 die )program using the function " Random Number Generator " where the dice can get random combinations randomly which means I don't have to assign the 216 dice combintions . Anyone have any idea how to write the program ? Perhaps write the beginning part of the program so that I could roughly have an idea to continue from there. I appreciate your help. Thanks a lot . Below is my program: >>>>>> boring code removed by archive manager, see his other postingArticle: 62336
In the distribution I have it is at - Jbits/con/xilinx/Boardscope.. Steve PS there are a lot of great engineers who speak German, French, Spanish, Japanese, Chinese, Korean, Polish and many other languages. If you are unsure of your English try posting in both English and your native language. "Barthélémy von Haller" <bartoche@bluewin.ch> wrote in message news:969317f.0310270555.228001@posting.google.com... > Hello all, > > I'm learning to use JBits and I want to verify the bitstream I > produce. I have seen that an application called BoardScope can do > that, but I'm unable to find this app. Can you help me ? > I precise that BoardScope is not yet given with JBits package. > > Thank you and sorry for my english > > Barthélémy von HallerArticle: 62337
"Amstel" <lange360@hotmail.com> wrote in message
news:56f7756d.0310270805.76c619d6@posting.google.com...
> I did an electronic dice game ( 3 die ) program in VHDL. Basically ,
> the program has 216 different dice values combinations which was
> simply assigned by me. The dice has 3 segment displays . I defined the
> 3 displays as output " seg " .
> However , I can't figured out any idea to write this electronic dice (
> 3 die )program using the function " Random Number Generator " where
> the dice can get random combinations randomly which means I don't have
> to assign the 216 dice combintions .
> Anyone have any idea how to write the program ?
You're nearly done.
You don't need any kind of random number generator. Just
make the clock run very fast (100 MHz ???) and add one more
input, an "Enable". Inside the state machine, wrap your
case statement in an "if" block:
if enable = '1' then
case sm
......... lots of stuff
end case;
end if;
Now connect "Enable" to a pushbutton. While this button
is down, the dice will roll - far too fast for the eye
to follow. When the button is released, the dice will
stop at a point which is essentially random, controlled
only by the exact moment of release of the button.
OK, that's the homework done. For a bit more credit, you
need to do two things:
(1) make your design and coding a lot more stylish; at the
moment, it's about as ugly as a sea cucumber's backside.
(2) think very, very carefully about why the "enable button"
scheme doesn't work well, and needs a lot of fixing.
The thread that you stimulated a couple of weeks ago, but
never contributed to again, would be a useful starting point.
> Below is my program:
Small children, nursing mothers and others of nervous
disposition should avert their gaze at this point.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 62338>(2) think very, very carefully about why the "enable button" > scheme doesn't work well, and needs a lot of fixing. I was going some comment about metastability, but maybe it's more fun to try to demonstrate setup/hold glitches. It would be like real life when one of the die leans against another one. How would you build a system to maximize the chances of screwing up? I think you want a state machine with lots of illegal states and maybe lots of transitions with many bits changing. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 62339
Hi all, I've got a little question about post Place&Route simulation in ISE WebPack 5.2 + ModelSim. How can I do a post-PAR simulation of a VHDL submodule (i.e. a part of a bigger design that is not connected to I/O buffers)??? I tryed to uncheck the "Add I/O buffer" (synthesis), to use the SAVE constraints and/or to uncheck the "Trim unconnected signals" (mapping), but I've always got mapping or simulation errors... Thanks in advance, Antonio Di StefanoArticle: 62340
I have a DSP chip with address/data bus and control pins interfaced to a Spartan IIE. The DSP is driving these lines, but I do not ever need to use some of them in my FPGA design. What should be done with these input pins? At the moment they are completely unassigned (using Webpack). Some are strobing or clocking, and others just fixed value. Also, I have assigned two pins which connect to ground on the DSP board as GROUND_OUT <= '0'; Is this adequate for grounding? I guess there is no such thing as a ground 'input' on an FPGA as you cannot assign an input to '0'. The DSP bus is driven out through a TI CMOS transceiver/buffer chip (on TI C6711 DSK board) and I have connected this bus directly to inputs on the FPGA, configured as LVTTL as logic 1 is 3.3V. Is this OK? Do I need to use pullup or pulldown "virtual" resistors on the FPGA inputs? Many thanks for your help TomArticle: 62341
Thanks, I will consider using both propositions! One more thing, what exactly is a state-machine? I have read this expression about a milion times in datasheets and application notes, but I stil don't know what it is. GeorgeArticle: 62342
george_mercury@hotmail.com (George) wrote in message news:<6d167a0a.0310260419.50c5076d@posting.google.com>... > Hi! > I am a bit new to FPGAs, so far I have only worked with CPLDs ( Xilinx > 9500 family ). Now I would like to use a Spartan 2E ( with WebPack 5.2 > and VHDL ) to make a SDRAM controller. > > I have searched this archive but I haven't found any topic related to > my question. Here's the deal. When data needs to be transfered to the > SDRAM the controller sends out data prior to generating the rising > edge of the SDRAM's clock. So the way I see it, the fpga must generate > two clocks, one for the controller and one for the SDRAM. The SDRAM > clock must be by 90° out of phase of the controller clock ( the SDRAM > clock must be delayed for 1/4 of the cycle of the controller clock ), > in order for data to appear on DQ lines before the rising edge of > SDRAM's clk. I am right so far, or am I way off? And If I am right, > how do you generate the SDRAM clock ( do you use a DLL to phase-shift > the input clock ? ). Assumption: Single-data-rate SDRAM. You're making the whole thing WAAAAY too complicated. Your SDRAM controller should obviously be a synchronous state machine. Clock the SDRAM and the controller with the same clock -- it's common to use special clock-buffer chips to do this. You have a synchronous controller, and you should register the data outputs, too: this way, the SDRAM command and data lines all have the same clock to out. Say you're running your SDRAM and controller at 100 MHz (to keep the math simple). Say your FPGA (or whatever) has clock-to-out on the pads spec'd at 5 ns. Say the SDRAM has 2 ns setup and 1 ns hold times. Say you've laid out your board such that the flight time of the traces between the controller and the SDRAM is 1 ns. This all means that command and data asserted on clock edge 1 will be stable by edge 1 + 5 ns. Therefore, that command and data are valid on the SDRAM pins on clock edge 1 + 6 ns. They meet SDRAM setup with a 2 ns margin, and will be registered in the SDRAM on clock edge 2. In other words, it's Synchronous Design 101, and nothing special is required in order for you to meet the SDRAM's timing specs. -aArticle: 62343
DLLs ain't misbehavin' !
The DLL in Spartan-2 does not have all the functionality of the
Virtex-II and Spartan-3 DCMs, but all these circuits, even the DLL,
offer extremely low ("zero") skew between their output drivers. So I
disagree with Jeff's statement.
Peter Alfke, Xilinx Applications
=================
Jeff Cunningham wrote:
>
> Peter Alfke wrote:
> > If you use the Digital Clock Manager in Virtex-II or Spartan3, you have
> > four outputs with practically zero skew (<100ps?)between them, and they
> > can be fractions or multiples of the incoming clock. When you distribute
> > these signals on global clocks, there will not be any hold-time caused
> > problems. The skew is definitely less than any clock-to-Q.
>
> Just to make sure I understand, this is NOT the case with the Spartan-2
> DLL is it, i.e. the skew is not so well behaved in the DLL.
>
> Jeff
Article: 62344Manfred Balik wrote: > I'm using an Altera ACEX1K and can't find the condition of the IO-Pins > during configuration and initialisation of the FPGA ??? > Can there be an input on the IO-Pins during configuration and > initialisation ? You shouldn't count on them being pulled up or pulled low. > Especially can there be a clock on GCLK0-Pin during configuration and > initialisation ??? Sure. You could have an smd clock oscillator on board and wouldn't want to unsolder it just for configuration. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 62345
I googled on "802.11" phy core and got several hits. Here's one that has been targeted to an FPGA. http://www.ittiam.com/pages/products/wlan-aphy.htm Robert "David" <dbeberman@earthlink.net> wrote in message news:366a0905.0310250649.7e4883f@posting.google.com... > Hi, > > I've been reading the archives of this list, and the FAQ. I haven't > seen much about 802.11a and g phy implementations. Does anybody know > where I might find 802.11a/g VHDL, Verilog or other implementations. > This does not need to be open source, however, I am looking for > something that I will be able to add my own modifications to. > > Thanks, > > DavidArticle: 62346
One option is to modify the "add wave" section of the tb_<filename>.tcl script created by dspbuilder. from : add wave -radix dec /tb_test/oSines to : add wave -radix dec -format Analog-Step /tb_test/oSines hope this helps, Charles Anshu <experteyes2002@yahoo.co.in> wrote in message news:<eec61de.-1@WebX.raydaftYaTP>... > Hello all, > > > Well DSPBuilder is the altera tool that works on the Simulink > platform. > Well it do have an automated flow to the simulation tool called as > ModelSim -Altera. > > > Well I take the tb_<filename>.tcl to ModelSim and do the > Execute macro . Now it automatically opens the waveform editor. > > > I can view the signals only in the digital domain . I want to > visualize in the analog domain . > > > How i gonna view the signals in the analog domain in the ModelSim - > Altera ? > > > Any Suggestions ... > > > Regards > AnshuArticle: 62347
I have checked in Jbits/com/xilinx/Boardscope but I did'nt find it. Maybe it is because it's version 3.0. Do you have an URL where I can find it ? Thank you PS : next time i'll post in both french and english ! ;) Steve Casselman <sc_nospam@vcc.com> wrote: > In the distribution I have it is at - Jbits/con/xilinx/Boardscope.. > > Steve > PS there are a lot of great engineers who speak German, French, Spanish, > Japanese, Chinese, Korean, Polish and many other languages. If you are > unsure of your English try posting in both English and your native language. > > "Barthélémy von Haller" <bartoche@bluewin.ch> wrote in message > news:969317f.0310270555.228001@posting.google.com... > > Hello all, > > > > I'm learning to use JBits and I want to verify the bitstream I > > produce. I have seen that an application called BoardScope can do > > that, but I'm unable to find this app. Can you help me ? > > I precise that BoardScope is not yet given with JBits package. > > > > Thank you and sorry for my english > > > > Barthélémy von HallerArticle: 62348
Hi to all interested in, Xilinx support respondet, that in the future it will be possible to redirect the jtag signals to custom registers. The developer agreed that it is a very useful feature. Not only for us... today, there is no way to make reuse of the parallel III / IV driver ... thomas "Antti Lukats" <antti@case2000.com> schrieb im Newsbeitrag news:80a3aea5.0309252121.48107d27@posting.google.com... > "T. Irmen" <tirmen@gmx.net> wrote in message news:<bkvkuq$9im$1@online.de>... > > Hi Antti, > > > > > 5 intercept dll, it exposes xilinx DLL entry points and call xilinx > > > dll > > > (that you have renamed) part of the calls are re routed to your dll > > > that then talks to your hardware > > > > that sounds good to me. > > > > I never thought of that way. Isn´t it possible to stack a filter onto xilinx > > kernel driver? > > stupid, me, yes it would. its just that I havent written such drivers > > > Do you know which Xilinx DLL I have to deal with? :-) > > not hard to find, check out whitch one talks the xpc4drvr.sys > > anttiArticle: 62349
George wrote: > Thanks, I will consider using both propositions! One more thing, what > exactly is a state-machine? I have read this expression about a milion > times in datasheets and application notes, but I stil don't know what > it is. > > George A state machine is like a little hardwired program inside of your design. It's called a state machine because it works on a so-called state register and a number of inputs to generate outputs, and a new value of the state register. This state register can be implemented in umpteen ways, and how the state machine decides to jump from one state to the next can be implemented in even more ways. I'd say just look up "Moore Mealy FSM" on Google to get the hang of the idea. Best regards, -- Ben
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