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Peter -
I don't want to put words in Ray Andraka's mouth, but I distinctly
remember him posting about the dangers of using the supposedly
low-skew outputs from the DLLs of Virtex parts. As I recall, the
problem he experienced was that jitter on the clock coming into the
part resulted in jitter on the DCM output clocks, in a way that didn't
track from clock to clock. (Such jitter could be caused by the clock
generator itself, or by SSO noise from nearby FPGA outputs.) So while
the spec for output-to-output skew is indeed low, the effects of input
clock jitter could increase these numbers. (If this is wrong, Ray,
please jump in and correct me.)
For that reason, I've always treated transfers between f and Nf
domains carefully, and I assume that rising-edge-to-rising edge
transfers won't work reliably in all cases.
So, my questions:
1) To what extent does jitter on the input clock affect DLL/DCM
output-to-output skew?
2) Is there some amount of input clock jitter below which the skew
published in the data sheets dominates? For example, for a Virtex II
part, how much jitter can I tolerate on the DCM clock input before the
DCM output-to-output phase offset exceeds the +/-140ps number in the
data sheet? (The Virtex II data sheet says that the input clock
period jitter can be as high as +/-1ns; is this just the amount of
jitter we can tolerate before losing lock, or do I get the +/-140ps
clock-to-clock output skew with this much jitter?)
Thanks,
Bob Perlman
Cambrian Design Works
On Mon, 27 Oct 2003 11:53:55 -0700, Peter Alfke <peter@xilinx.com>
wrote:
>DLLs ain't misbehavin' !
>
>The DLL in Spartan-2 does not have all the functionality of the
>Virtex-II and Spartan-3 DCMs, but all these circuits, even the DLL,
>offer extremely low ("zero") skew between their output drivers. So I
>disagree with Jeff's statement.
>
>Peter Alfke, Xilinx Applications
>=================
>Jeff Cunningham wrote:
>>
>> Peter Alfke wrote:
>> > If you use the Digital Clock Manager in Virtex-II or Spartan3, you have
>> > four outputs with practically zero skew (<100ps?)between them, and they
>> > can be fractions or multiples of the incoming clock. When you distribute
>> > these signals on global clocks, there will not be any hold-time caused
>> > problems. The skew is definitely less than any clock-to-Q.
>>
>> Just to make sure I understand, this is NOT the case with the Spartan-2
>> DLL is it, i.e. the skew is not so well behaved in the DLL.
>>
>> Jeff
Article: 62351Hello: I am not so surprised: this thread, has triggered lots of answers. To me, this underline the need, for a given Linux application to be able to run on most "current" distributions. Or stated otherwise to be distribution independent. If Altera (or any other vendors) do not want to do this, it is after all their choice to loose customers to vendors who will address waht seems to be a very common request. But I believe their concern is to have to test, and support their software on only one distribution, to make things possible. Instead of having the (irrational in my view) position: "We support only this Linux" which inevitably will result in supporting the local Linux vendor (SUSE=Germany, REDHAT=US, MAndrake-France, etc...), I would suggest to rather support a "level" of Linux Kernel+Libraries. A collateral advantage, would be for libraries and kernel developpers to evaluate if they did not break backward compatibility, by trying a few large applications. In my view it is fine for vendor to test their distribution, only on one current version of Linux. (Current to me is latest and one before latest). I would advocate to use Debian, which is based on stability, rather than "bleeding edge", and is really open source. Unless I am mistaking it also uses unmodified Linux Kernels. (Commercial distributions tend to modify the kernel). This will have the advantage to have Linux deliver what most of US want: freedom of choice, unlike proprietary operating systems. To achieve this, could be either a fancy script, but I have to admit that I do not favor this: 1) portablility is not great, 2) Debugging can be hairy. I am wondering if the best solution would not be, just a simple open source module written in C, which could do the necessary initialization (checking authorizations, setting of environment variables, openning of configuration files), and having this open source module, calling "Proprietary code" in object form. This would allows user to develop and post on the net fancy installation files, specifics to a given distribution. Does this make sense? Thanks for your attention. ---- Jan De Ceuster <jandc@elis.ugent.be> wrote in message news:<bn59aj$tqj$1@gaudi2.UGent.be>... > >>And now it works... Maybe Altera should write a cleaner script that > >>first checks if it's a Red Hat distribution... > > > > > > Yes. But it would have been even better if they checked for the > > *features* they need rather than checking the distribution. > > Indeed and I even had to manualy add some directories to the librarypath to get > everything up and running. It just doesn't look profecional to me. 2 days work > (at most) for a decent engineer and the scripts would have been perfect. I'm a > bit dissapointed... > > kind regards, > JanArticle: 62352
Hello George, > One more thing, what exactly is a state-machine? I have a presentation that discusses finite state machines -- with a simple example in Verilog, at: http://www.engr.sjsu.edu/crabill/vlogfsm.pdf If you are looking for a ready-made SDRAM controller, you can find one on the Xilinx website, as XAPP134. I've used it in a project and it works properly. Good luck, EricArticle: 62353
Bob, The DCM ICDES expert will weigh in here. See below, Austin Bob Perlman wrote: > Peter - > > I don't want to put words in Ray Andraka's mouth, but I distinctly > remember him posting about the dangers of using the supposedly > low-skew outputs from the DLLs of Virtex parts. As I recall, the > problem he experienced was that jitter on the clock coming into the > part resulted in jitter on the DCM output clocks, in a way that didn't > track from clock to clock. (Such jitter could be caused by the clock > generator itself, or by SSO noise from nearby FPGA outputs.) So while > the spec for output-to-output skew is indeed low, the effects of input > clock jitter could increase these numbers. (If this is wrong, Ray, > please jump in and correct me.) ?? Yes there is added jitter, but it is added to all outputs at the same time. > > > For that reason, I've always treated transfers between f and Nf > domains carefully, and I assume that rising-edge-to-rising edge > transfers won't work reliably in all cases. > > So, my questions: > > 1) To what extent does jitter on the input clock affect DLL/DCM > output-to-output skew? Not at all. All outputs are generated by matched devices in the clock generator output block state machine that has the delay line (taps) as its inputs. > > 2) Is there some amount of input clock jitter below which the skew > published in the data sheets dominates? For example, for a Virtex II > part, how much jitter can I tolerate on the DCM clock input before the > DCM output-to-output phase offset exceeds the +/-140ps number in the > data sheet? (The Virtex II data sheet says that the input clock > period jitter can be as high as +/-1ns; is this just the amount of > jitter we can tolerate before losing lock, or do I get the +/-140ps > clock-to-clock output skew with this much jitter?) The latter. You get the +/- 140 offset on top of the 1 ns noise. One can think of the offset, or skew as DC, and the jitter as AC. On any signal, you have the AC component which varies, and the DC component which is fixed and does not vary for any given part. That is why the timing budget has to treat offsets different from jitter. They are both measures of time, but one is peak to peak white AC noise (jitter), and the other is + or - DC offset (output skew). Adding offsets is linear (1+1=2) while adding jitter is quadratic (1+1=1.414 or sqr(2)). Adding RMS jitter would add arithmetically (1+1=2), but the peak to peak to RMS ratio of designs is so hard to evaluate, that the RMS to P-P conversion factor could be guessed to be from 3 to 14 (and still not be right). Easier to keep everything in P-P, and do the calculations that way.Article: 62354
Hello Does anybody know how to import quartusII simulation waveform (.vwf) and block design file(.bdf) to the Word file( .doc)? Thanks. SarahArticle: 62355
On 26 Oct 2003 23:23:14 -0800, google@matthardy.us (Matt Hardy) wrote: >Hello, > >I have a large design implemented in Verilog. In the design there are >several thousand SRL16 type shift registers that are inferred from the >Verilog by XST. What is the best way to initialize each shift >register with different a unique value? Preferably this >initialization could be specified outside of the verilog so that >thousands or different module definitions are not needed. I also am >using all 96 block rams on the XC3S4000 and need to initialize those >as well. > >Currently I am initializing the block rams in the module where they >are instantiated but for the final design I need this to be seperated >from the Verilog module definition because I don't want to have 96 >different module definitions. Can you figure out a way to specify the initial value using a parameter? That way, you only need one module definition. This is simple to do in VHDL, and ought to be possible in Verilog. Regards, Allan.Article: 62356
Hi, Is there a good book on FPGA CPU design which starts with a simple cpu, like Xilinx PicoBlaze, and takes the user through different aspect of cpu design like instruction set design, pipelining, etc., etc, at the same time keeping the focus on actual implementaion in a FPGA and not on theoritical discussions? Am I asking for too much? Thanks. Pratip Mukherjee.Article: 62357
"Pratip Mukherjee" <pratipm@hotmail.com> wrote in message news:Xns9421CF58A715Fpratipmhotmailcom@204.127.199.17... > Hi, > Is there a good book on FPGA CPU design which starts with a simple cpu, > like Xilinx PicoBlaze, and takes the user through different aspect of cpu > design like instruction set design, pipelining, etc., etc, at the same time > keeping the focus on actual implementaion in a FPGA and not on theoritical > discussions? Am I asking for too much? > Thanks. > > Pratip Mukherjee. I like http://www.amazon.com/exec/obidos/tg/detail/-/1558606742/qid=1067305763/sr=8-1/ref=sr_8_1/103-1584317-6219838?v=glance&n=507846 He develops a CPU as an illustration of various VHDL coding techniques.Article: 62358
Somehow , I'm required to write this electronic dice game program using the function " Random Number Generator " . It's part of a project assignment and I have no choice . I really need help on how to write the program using the " Random Number Generator " . Please . Anyone have any solutions ? Thanks a lot .Article: 62359
Manfred Balik wrote: > I'm using an Altera ACEX1K and can't find the condition of the IO-Pins > during configuration and initialisation of the FPGA ??? > Can there be an input on the IO-Pins during configuration and initialisation > ??? Yes, there can be inputs. The ACEX pins are weakly pulled high before and during initialization. > Especially can there be a clock on GCLK0-Pin during configuration and > initialisation ??? Yes, no problem.Article: 62360
Copy and Paste using the clipboard. - Subroto Datta Altera Corp. "sarah" <sarahshen2003@yahoo.ca> wrote in message news:d51c0c2.0310271643.532e37d4@posting.google.com... > Hello > > Does anybody know how to import quartusII simulation waveform (.vwf) > and block design file(.bdf) to the Word file( .doc)? > > Thanks. > > SarahArticle: 62361
Hi, Sorry to bother you all, but has anyone here ever used the trenz-electronics XC2S spartan board? I bought it about a year ago and just recently started working on it. I tried earlier to program the flash rom from which the spartan will then load automatically. Whenever I start the webpack4.1 impact programmer, I keep getting an error telling me to set the JTAG clock setting. I've done it, but I can't get the stupid thing to properly initialize and program itself. Well, I've gotten this thing to work before. What gives? Thanks, LTArticle: 62362
Just to provide some clarification on one of Rick's comments below, an HDL simulation package *is* included with one of our Quartus II subscriptions at no additional cost. Specifically, we provide Model Technology™ ModelSim®-Altera for VHDL or Verilog HDL simulation. Have a look at http://www.altera.com/products/software/order/ord-subscription.html for more details. Hope this helps. Chris Balough Director, Software and Tools Marketing Altera Corp. cbalough@altera.com rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F967A05.37B0A649@yahoo.com>... > Andreas Holz wrote: > > > > Hello all, > > > > I'm thinking about a project to reimplement old processor designs > > (Symbolics Lisp-machines or a Control-Data cyber 17x, 18x in a chip) > > using modern programmable hardware, e.g. FPGA's. > > > > The complete hardware documentation for these platform is available. > > > > My knowledge in this task in not up-to-date, as I've not been working > > on hardware design for almost ten years (onyl software!). > > > > I would like to get some suggestions about a FPGA Development > > environment and programming system to use for this task. Any other > > suggestions or links to similar projects are very welcome. > > > > If there are other people interested in such kind of project, please > > contact me directly. > > > > This is not a commercial project! > > > > Andreas > > This would be an interesting project and might even make a good project > for an advanced class in processor design. If I am not mistaken, there > is a web site or sites where others are working on similar projects. I > have seen projects on PDP-xx machines as well as others. Certainly this > is not a difficult task. > > I would recommend that you find a board using a Xilinx FPGA since they > provide more complete design tools for free. The current Altera tools > do not include an HDL simulator. I am assumming of course that you > intend to use an HDL, and I also recommend it. > > Here is a list of some FPGA board vendors... > > http://www.fpga-faq.com/FPGA_Boards.shtml > > Do a Google search on this and find some of the individuals doing > similar projects. I am sure they can give you some good advice. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 62363
"T. Irmen" <tirmen@gmx.net> wrote in message news:<bnk4qb$nii$1@online.de>... > Hi to all interested in, > > Xilinx support respondet, that in the future it will be possible to redirect > the jtag signals to > custom registers. The developer agreed that it is a very useful feature. Not > only for us... well the jtag signals can be used with custom registers today, no problems with that!! > today, there is no way to make reuse of the parallel III / IV driver ... you can reuse Cable III, no problems with that, just write your own logic analyzer core, write the custom registers, connect them to BSCAN primitive, and then use JAM player to talk to your custome logic analyzer and custom registers. this cant be used with Cable IV, because the API and documentation about Cable IV are kept as secret. anttiArticle: 62364
Hi, I am trying to understand the technique of eliminating static 1 and 0 Hazards with the K-map method. I understand how to eliminate static 1 hazard with the K-map method, but how do I know wether eliminating static 1 hazard will also eliminate static 0 hazard? Thanks! HendraArticle: 62365
Hi Tom You should find that any pins declared as inputs but unused in your design will be optimised out by the Xilinx tools during synthesis and mapping. Once you've placed and routed your design, right click on the "Generate Programming File" process and choose "Properties", select the "Configuration Options" tab and choose "Float" for unused IOB pins. This will ensure that all unused pins are tristated. That way even if the DSP does drive them, no contention can occur. I'm not quite sure what you mean by "adequate grounding". You can assign IO pins as outputs and tie them to GND to improve the chip's grounding. However, as long as all the dedicated GND pins are connected, this shouldn't really be necessary. I'm not sure what levels the CMOS transceiver works at. As long as it is 3V3 TTL compatible you should be fine with your setup as is. Hope this helps Sam "Tom Derham" <tderham@NOSPAM.ee.ucl.ac.uk> wrote in message news:bnjn2a$oo4$1@uns-a.ucl.ac.uk... > I have a DSP chip with address/data bus and control pins interfaced to a > Spartan IIE. > The DSP is driving these lines, but I do not ever need to use some of them > in my FPGA design. > What should be done with these input pins? At the moment they are > completely unassigned (using Webpack). Some are strobing or clocking, and > others just fixed value. > > Also, I have assigned two pins which connect to ground on the DSP board as > GROUND_OUT <= '0'; > Is this adequate for grounding? I guess there is no such thing as a ground > 'input' on an FPGA as you cannot assign an input to '0'. > > The DSP bus is driven out through a TI CMOS transceiver/buffer chip (on TI > C6711 DSK board) and I have connected this bus directly to inputs on the > FPGA, configured as LVTTL as logic 1 is 3.3V. Is this OK? Do I need to use > pullup or pulldown "virtual" resistors on the FPGA inputs? > > Many thanks for your help > > Tom > >Article: 62366
I have spent three-four days on several XPLA3 CPLD boards that I've designed (same boards) to determine why the JTAG is not working properly. I cannot initialize the chain to "read" what devices are on the boundary scan chain, nor will TDO change states. I can set "levels" on TDI, TMS, and TCK using the "Start Debug Chain" portion of the Xilinx IMPACT software. I am using the Parallel IV cable and have read a few places it could be cable length issues? Does ANYONE have any type of experience with this? I've been wracking my brains out trying to figure out what's wrong. I am using a "home-made" cable because my PCB is used in embedded application with limited space. Even went to a BLANK PCB and stuffed only CPLD, linear regulator, and caps. Any help is MUCH MUCH appreciated... Thanks!Article: 62367
Sorry for the late response...
"John Williams" <jwilliams@itee.uq.edu.au> wrote in message
news:bn9j1j$c24$1@bunyip.cc.uq.edu.au...
> Hi Frank,
>
> Frank wrote:
> > I've succesfully build a microblaze system with external interrupt and
my
> > own IP core (using the opb slave template in the EDK). The interrupt is
> > connected to a dip-switch. In the ISR I'm writing some data to my own IP
> > core (which is an OPB slave). My OPB slave is reading some other
> > dip-switches and put the result to some LEDs (yes I'm using an
evaluation
> > board ;). So far everything is ok. Now comes the problem: the expected
> > behaviour is dependent of the code in the ISR. If I've the following
ISR:
> >
> > void dip_isr(void)
> > {
> > *(opb_mycore_base) = 0x12345678;
> >
> > // Write the value of j to the LED
> > // XGpio_DiscreteWrite(&gp_out, 0);
> >
> > #ifdef USE_INTC
> > XIntc_mAckIntr(XPAR_MY_INTC_BASEADDR, XPAR_SYSTEM_MY_INT_MASK);
> > #endif
> > }
> >
> > it's not working.
>
> Can you define what you mean by "not working"?
Well in my own user IP core, I'm reacting if there is a write access to the
base address of my IP core. The reaction is reading some dip switches and
writing a value to some leds. I can not see this behaviour when it's "not
working".
>
> > But if I enable the XGpio write, it is working.
>
> And similarly, what do you mean by "working"?
If it's working, the value of the dip switches are shown correctly at the
leds.
>
> > And at
> > last, if I do the XGpio write first and than the write to the OPB slave
> > (opb_mycore) it's again not working anymore.
>
> > In all three situations, the
> > code is coming in the ISR (I see that, because there is no output at the
> > uart anymore, which is done in the main program).
>
> I would hesitate to use that fact as proof that the code is entering the
> ISR...
I'm 100% sure that it's entering the ISR, because I also tested it with
toggling leds in the ISR.
>
> Anyway it almost suggests like you have some issues with the OPB address
> decoding in your slave. Either that, or some kind of bus timeout issue
> maybe. Have you tried simulating your core?
No, I haven't. At this moment, I don't know how to do that.
>
> Also, are you using the IPIF example that comes with edk3.2? Someone
> here in our lab very recently had problems with that, the IPIF address
> decoding wasn't doing anything like what he expected. When he dropped
> IPIF and did the OPB interface manually, it got a lot better.
Yes, I'm using the IPIF example from the EDK3.2 (I used the
opb_core_ssp0_v1_00_b). I will try it without the IPIF, but I'm still
inquisitive about the fact why it isn't working...
Article: 62368"Amstel" <lange360@hotmail.com> wrote in message news:56f7756d.0310271927.4ab2cdd7@posting.google.com... Hi, > Somehow , I'm required to write this electronic dice game program > using the function " Random Number Generator " . If you look back over the previous thread on this subject, when you asked for help about two weeks ago, you will see lots of very interesting discussion about how to use a random number generator for this problem, and why it's somewhat difficult. You will also find some very frivolous posts from me and others! > It's part of a project assignment and I have no choice. > I really need help on how to write the program using the " Random > Number Generator " . What kind of random number generator? I have already offered a suggestion for one way to make a random number generator, based on human-driven sampling of a very fast counter. It works well - I made an electronic die like this back in 1976 using four LSTTL chips, and seven LEDs. It even had a touch-pad that you could press to roll the die - I think I used a FET-input op amp for that. > Please . Anyone have any solutions ? OK, here goes. 1) Make a nice big linear-feedback shift register to create a pseudo-random stream of bits. 2) To roll the 3 dice, clock the shift register 8 times to get 8 random bits. (You can pick these bits from the top 8 flip-flops of the shift register; there's no need for separate storage.) 3) If the numeric value of the 8 random bits is greater than 215, go back to step 2 and keep trying until you get <=215. 4) Now you've got a numeric value in the range 0..215, decode it onto the dice display using something similar to the huge and disgusting selected assignment at the end of the code you showed in your last post. Steps (2) and (3) need a state machine. The same state machine can also manage interaction with the user push-button or whatever mechanism you use to demand a dice roll. For the linear feedback shift register, how about a 20-bit shift register with taps 20 and 17 XOR'd together and fed back to the input?Article: 62369
Thanks a lot for your effort. I found my KCPSM source cannot pass the IDE asemble, but it had passed the KCPSM.EXE of Xilinx and generated VHDL code for synthesis. In my source, the "input sX, (sY)" instruction were reported as "?Closing". Some labels ahead instructions were reported as "?Phasing", but some were OK. Why? Besides, what's the difference between "open file" and "import file"? "Henk van Kampen" <henk@mediatronix.com> :23ecd97d.0310240736.7b08c8dd@posting.google.com... : Recently I have updated my Picoblaze (tm Xilinx) development tool : pBlazIDE and added some documentation. Additionally I have published : some example code and demonstration files. Please feel free to check : this out. Its all freeware. Check under 'Tools'. : : Regards, : Henk van Kampen : www.mediatronix.comArticle: 62370
Jonathan Bromley wrote: > What kind of random number generator? I have already offered > a suggestion for one way to make a random number generator, > based on human-driven sampling of a very fast counter. Jonathan - do you happen to know how fasible it is to generate a random stream by sampling white noise with an A->D converter. By feasible I mean a reasonable cost level and a reasonable component count, though I guess qualifying the resulting circuit is really the expensive part of the job. Somewhere in "The Art of Computer Programming" Knuth points out that you cannot generate random numbers by randomly choosing an algorithm ;-)Article: 62371
cbalough@altera.com (Chris Balough) writes: > Just to provide some clarification on one of Rick's comments below, an > HDL simulation package *is* included with one of our Quartus II > subscriptions at no additional cost. Specifically, we provide Model > Technologyž¹ ModelSim®-Altera for VHDL or Verilog HDL simulation. Have > a look at http://www.altera.com/products/software/order/ord-subscription.html > for more details. > To further calrify (:-) - I think Rick's point was that of the "free" tools, Webpack offers Modelsim-XE whereas Quartus offers the built-in simulator only. Unless that's changed since I last looked? Martin. -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 62372
antonis_konstantinos@hotmail.com (Antonis Konstantinos) writes: > Hi all, > > I am trying to implement an LCD driver in FPGA which will drive a > 320x240 color LCD (digital 18bit parallel input). > > Could you please read below and comment if my way if thinking is > correct or not. > > For two virtual screens to be stored in memory I need 2x320x240x18 > bits = 150k x 18 bits of memory. And this seems impossible with > Spartans' block ram. So I need an external memory. > Sounds good so far... > At first I tought that I need a dual port SRAM since a host will write > to the video memory and the driver will continuously read from that > memory and feed the LCD. But these RAMs seem to be overpriced (Arrow > says hundered something dollars for 4mbit memory) > :-) DPRAM is not cheap > Then I realised that at 60 Hz driving frequency I only need ~8 Mhz > clock. Is it possible to use a faster main clock (like 50-60 Mhz > maybe) and still feed the LCD at 8 Mhz and in the remaining time > fulfill the memory read/write commands given by the host > asynchronously? > > If that is true I need a memory capable of achieving around 60Mhz. > > I found the NoBL (or ZBT)SRAMs from Cypress and IDT which can go up to > 166 Mhz and gives me full bw utilization. (no wait cycles b/w read and > write). And the good thing is that they also come in x18 organisation > which is just what I need! > Digikey says ~$9 for 256kx18 100 MHz ZBT SRAM. > > Is that memory suitable for my needs or would you recommend any other > memory? > How about SDRAM? The controller is not that complicated, or you can use the Xilinx or Altera reference designs. I've done 800x600x60Hz with memory to spare for framebuffers coming out of your ears (I think we had 15+ of them) simply because you can;t buy SDRAMs small enough :-) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 62373
Ronald Chung wrote: > I have spent three-four days on several XPLA3 CPLD boards that I've > designed (same boards) to determine why the JTAG is not working > properly. I cannot initialize the chain to "read" what devices are on > the boundary scan chain, nor will TDO change states. I can set > "levels" on TDI, TMS, and TCK using the "Start Debug Chain" portion of > the Xilinx IMPACT software. > > I am using the Parallel IV cable and have read a few places it could > be cable length issues? Does ANYONE have any type of experience with > this? I've been wracking my brains out trying to figure out what's > wrong. > > I am using a "home-made" cable because my PCB is used in embedded > application with limited space. > > Even went to a BLANK PCB and stuffed only CPLD, linear regulator, and > caps. > > Any help is MUCH MUCH appreciated... > > Thanks! Try to add an 1K pull-up on TDO and let me know if that's better. Laurent www.amontec.comArticle: 62374
Loi Tran wrote: > Hi, > > Sorry to bother you all, but has anyone here ever used the trenz-electronics > XC2S spartan board? I bought it about a year ago and just recently started > working on it. I tried earlier to program the flash rom from which the > spartan will then load automatically. Whenever I start the webpack4.1 impact > programmer, I keep getting an error telling me to set the JTAG clock > setting. I've done it, but I can't get the stupid thing to properly > initialize and program itself. Well, I've gotten this thing to work before. > What gives? > > Thanks, > > LT I think this is a trouble with the board. I don't know trenz-electronics boards and schematics. Could you let me know how the CE# of the FLASH is connected. Normally, we have to add electronic or just a jumper, to allow 1) a connection between the done signal to the CE# in normal use (FPGA in master serial or parallel) 2) a disconnection of the done signal and the CE# in JTAG mode and auto-configuration using CF pin of FLASH to generate a pulse on FPGA program pin Laurent www.amontec.com
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