Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Yana, The .ll file should provide the absolute bit offset as well as Frame address and offset. You no longer need the equations to calculate the DFF or BRAM bit location. Regards, Wei Yana wrote: > Hi: > > I'm working on partial reconfiguration of VII devices, and until now I > haven't found information about the internal configuration addressing > of VII and the respective formulas to calculate MJA and MNA. I guess > they are similar to the ones for VirtexE (as both have BRAMs > interspersed between CLBs). > > Its urgent!!!! PLS > > P.S I have already read app 151, app290, VII user guide, etc > > YanaArticle: 62228
Hye, It exists Xilinx Applications notes ( XAP169 ) concerning a MP3 player. Visit www.support.xilinx.com and make a search with MP3. Regards. "SneakerNet" <nospam@nospam.org> a écrit dans le message de news: PMEib.177545$JA5.4451689@news.xtra.co.nz... > Hi All > > Has anyone done/come across a mp3 personal project which is done using FPGA > with added circuitry. Please let me know. I'm looking at making one myself > and would like some added help. > > Right now i'm doing research on it, so any info pls pass it on. > > Kind Regards > > > >Article: 62229
"David Brown" <david@no.westcontrol.spam.com> wrote in message news:<bn0j25$91g$1@news.netpower.no>... > I'm using the downloadable version of ispLever for a verilog project on a > Lattice Mach 4 CPLD chip. The software has both Synplify and Leonardo > Spectrum available for synthesis. I can build the code (so far, anyway) > with either tool. Is there any reason why I should choose one over the > other? Well, the full-up version of Leonardo lets you set Verilog parameters from the GUI or from a TCL script, whereas Synplify does not. This makes parameterized designs impossible in Synplify, so that tool's disqualified until that very important feature is added. (Ummmm, haven't parameters been a part of the language since the beginning???) Leonardo does not (and will never) support Verilog 2001 whereas Synplify does. If this matters to you, then your choice is obvious. Mentor Graphics is replacing Leonardo with their new Precision Synthesis tool, which does have V-2001 support, but it's not clear if a "lite" version will be offered via the FPGA vendors. -aArticle: 62230
"Panic" <panic74@hotmail.com> wrote in message news:<cUglb.518$mf2.4092@news4.e.nsc.no>... > After searching for the source of an error for quite a long time, I've > decided that I need some help, and once again you guys drew the shortest > straw ;-) > > I have a 8 bit DFF with output q[7..0]. This feeds the net > dff_inst23_out[7..0]. (The reason this net is given this name, was to see if > the error actually was located where I thought it was, since the original > error pointed to some temp net.) Both the DFF output and the net is 8 bits > wide, and still I get this error message: > > Error: Net dff_inst23_out[6] cannot be assigned more than one value > Error: Net is fed by std_8bit_dff0:inst8|lpm_ff:lpm_ff_component|dffs[6] > Error: Net is fed by std_8bit_dff0:inst9|lpm_ff:lpm_ff_component|dffs[6] > Error: Net is fed by std_8bit_dff0:inst23|lpm_ff:lpm_ff_component|dffs[6] > > This is repeated for each bit of dff_inst23_out. > > Ok, so I have two other registers that feed this net, but they are not > connected! I understand that this is happening because the output of these > other registers are the same as the inst23 one, but hey, I've got more > registers like that, all over the place! So why is this happening to this > particular net? > > I've taken a screenshot of the design in question, and my troublesome net is > the blue stub: > http://www.battlefield.no/bilder/inst23.gif > > Any suggestions would be appreaciated! > Sincerely > -"Panic" Panic, There is a connection error in the schematic that you provided me which is not evident from the bitmap posted on the web. The qar file with the schematics shows this problem. Two bitmaps have been posted to you, one circling the problem connection and the other one with the fix. - Subroto Datta Altera Corp.Article: 62231
Thanks a lot. That one had escaped me!Article: 62232
rickman wrote: > "Steven K. Knapp" wrote: > > > > The Spartan-3 pinout tables have now been updated to correct this mistake. > > The mistake in the data sheet is strictly the bank indication in the pinout > > table. The pin name and pin number in the data sheet is correct as is the > > PQ208 footprint diagram. > > > > The correct information for the PQ208 footprint table is available via > > either of the following two links. > > > > Spartan-3 1.2V FPGA Pinout Descriptions (pinout tables only) > > http://direct.xilinx.com/bvdocs/publications/ds099-4.pdf > > > > Spartan-3 Complete Data Sheet (All four modules) > > http://direct.xilinx.com/bvdocs/publications/ds099.pdf > > > > The electronic ASCII-text footprint tables were not affected by this > > mistake. > > http://direct.xilinx.com/bvdocs/publications/s3_pin.zip > > Steven, > > I am looking at partial/modular reconfiguration in Spartan 3 and I > realize that there are some issues with IO that I am not sure how to > resolve. To get an understanding of how to approach the problem I need > to know what IO pads and pins are mapped to what CLB columns. I am > looking at using the XC3S400 in the 456 pin BGA package. Where can I > get info on how the IOs are mapped to the CLB columns? The relative location of pins to CLBs can be seen graphically in PACE or put into a text file using "partgen -v xc3s400fg456" > > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX -- Marc Baker Xilinx Applications (408) 879-5375Article: 62233
Luddite Me, who's forgotten most of the Verilog he once knew, needs to start doing serious HDL-based design. No more schematic-orphans for me. Are there good reference books for Verilog or VHDL? Ideally, something akin to Java in a Nutshell (Java), the Post Script Red (language reference) and Blue (tutorial and cookbook) series, or K&R? Thanks. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 62234
1.5i was released in late 1998 (see http://www.xilinx.com/prs_rls/1_5i.htm) and supported Spartan-XL. 4.2i was released in early 2002 (see http://www.xilinx.com/prs_rls/software/0226_Em_perf.html) rickman wrote: > I rummaged around and found the old distribution of Foundation 1.5i that > I had used to design with a 4000XL back in 1998 using VHDL. Will this > package support the SpartanXL? I see that the version currently > provided by Xilinx is ISE 4.2i. When was this package orginally > released? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX -- Marc Baker Xilinx Applications (408) 879-5375Article: 62235
"Kasper Pedersen" <ngfilter@kasperkp.dk> wrote in message news:3f9570cb$0$45335$edfadb0f@dread11.news.tele.dk... > > "Carl" <jiz_king@hotmail.com> wrote in message > news:8aec9d92.0310210623.443ba2d5@posting.google.com... > > I have never used PLD's before, but have used PIC's (asm) and was > > wondering if it is realistic for me to grasp enough of PLD design (not > > necessarily VHDL) to implement some simple logic functions within a > > month or so? > > > > Or is this likely to take far longer? > > Assuming you're not learning logic from scratch: > When I first started with CPLD's I was using a rather early Xilinx > Foundation, > covertly provided to me, and it went something like this: > Day 0: Be friendly towards the FAE when he's on-site anyway. Get a hint. > Day 1: Get the tool installed. Why the hell won't my schematic of a > simple buffer translate? > Day 2: Discovered that I needed I/O buffers. Place a single counter into > the design, figure out how to put the pins where I want them. It > translates and fits! Build a small board with an oscillator, an XC9536, > and a LED. Borrow a Parallel-III cable. > Day 3: Programming works, LED is blinking (very quickly). Conclude that > this is feasible. > Day 6: Call the friendly FAE. "This is a tool bug. Do this instead." Get > a few tricks and nasty jokes. > Day 10: Create a better Parallel-III cable, give back the original. I bought a Parallel-III cable years ago, never used it though, but am "close" to using it now. What were your problems with the cable? Cheers KlausArticle: 62236
Also, search this newsgroup using "beginner" to find threads with ideas on how to get started. There was a recent one where sort of listed a suggested set of steps to get going. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "Andreas Holz" <asholz@topinform.com> wrote in message news:1795018.0310220045.189e6970@posting.google.com... > Hello all, > > I'm thinking about a project to reimplement old processor designs > (Symbolics Lisp-machines or a Control-Data cyber 17x, 18x in a chip) > using modern programmable hardware, e.g. FPGA's. > > The complete hardware documentation for these platform is available. > > My knowledge in this task in not up-to-date, as I've not been working > on hardware design for almost ten years (onyl software!). > > I would like to get some suggestions about a FPGA Development > environment and programming system to use for this task. Any other > suggestions or links to similar projects are very welcome. > > If there are other people interested in such kind of project, please > contact me directly. > > This is not a commercial project! > > AndreasArticle: 62237
Marc Baker wrote: > > rickman wrote: > > > "Steven K. Knapp" wrote: > > > > > > The Spartan-3 pinout tables have now been updated to correct this mistake. > > > The mistake in the data sheet is strictly the bank indication in the pinout > > > table. The pin name and pin number in the data sheet is correct as is the > > > PQ208 footprint diagram. > > > > > > The correct information for the PQ208 footprint table is available via > > > either of the following two links. > > > > > > Spartan-3 1.2V FPGA Pinout Descriptions (pinout tables only) > > > http://direct.xilinx.com/bvdocs/publications/ds099-4.pdf > > > > > > Spartan-3 Complete Data Sheet (All four modules) > > > http://direct.xilinx.com/bvdocs/publications/ds099.pdf > > > > > > The electronic ASCII-text footprint tables were not affected by this > > > mistake. > > > http://direct.xilinx.com/bvdocs/publications/s3_pin.zip > > > > Steven, > > > > I am looking at partial/modular reconfiguration in Spartan 3 and I > > realize that there are some issues with IO that I am not sure how to > > resolve. To get an understanding of how to approach the problem I need > > to know what IO pads and pins are mapped to what CLB columns. I am > > looking at using the XC3S400 in the 456 pin BGA package. Where can I > > get info on how the IOs are mapped to the CLB columns? > > The relative location of pins to CLBs can be seen graphically in PACE or put into > a text file using "partgen -v xc3s400fg456" I think you have a leg up on me. I am not familiar with a program called PACE. I am guessing that is the chip editor? If so, I do not currently have the full ISE tools and so do not have the chip editor. How else can I get this file? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 62238
Anybody having trouble with 6.1i (service pack 2)? Over 5.2i that is. I think I'm having trouble meeting all timing constraints when I was meeting them all in 5.2i (2 different designs). (I switched to highest effort BTW). And on one design after a minor change I believe the DLL would not lock anymore. I added test points, recompiled, and it still didn't work but test points indicated the DLL maybe. So I added different / more test points, recompiled, and this time it worked great. DanArticle: 62239
There was a thread on this issue on October 17th... /Mikhail "Dan Kuechle" <danielgk@voomtech.com> wrote in message news:3f96fe63$0$75900$a1866201@newsreader.visi.com... > Anybody having trouble with 6.1i (service pack 2)? Over 5.2i that is. > > I think I'm having trouble meeting all timing constraints when I was meeting > them all in 5.2i (2 different designs). (I switched to highest effort BTW). > > And on one design after a minor change I believe the DLL would not lock > anymore. I added test points, recompiled, and it still didn't work but test > points indicated the DLL maybe. So I added different / more test points, > recompiled, and this time it worked great. > > Dan > >Article: 62240
"Nial Stewart" <nial@spamno.nialstewart.co.uk> writes: > One guy would automatically run the emacs beautifier on any > source code as soon as he'd checked it out, work on it > then check it back in. (Only 1/3 of the team used emacs). In the places I've worked, this would have been sufficient grounds for the guy to be drawn and quartered. It is NEVER acceptable to reformat an entire source file when making minor modifications, and usually not even when making major mods.Article: 62241
I see a new post started about this elsewhere in this group. My one comment is that the FAEs who post here recommend that you call the hotline and open a case on this. The sooner they learn of your problem the sooner they can address it and keep it from being *my* problem... 8^O Nagaraj wrote: > > Hi, > I am facing the same problem. I have a design in XC2S400E which is > working well in ISE 5.1 sp3 and met all timing requirements. When I > moved to 5.2 it failed to give required timing. I did not worry b'coz > I knew that they are coming up with 6.1. Now when I > synthesized/implemented my design in 6.1 (latest sp), it is giving the > same result as in 5.2 (i.e. it is unable to meet the performance of > 5.1). > Now I am sticking with 5.1i since I have already used it for many > months, and also given my product to some customers (I need to support > them!!!). > My gut feeling is that when they changed from 5.1 to 5.2 something > has gone wrong in the tool software, and when they upgraded to 6.1 > since they used 5.2 (i assume! ) as base version, the problem > continued to exist even in 6.1. This is a clue to Xilinx people > (anybody here?) so that they can findout the cause of this problem. > Could anybody give assurance that atleast next versions will be > free from critical problems like these? > > Regards, > Nagaraj CS > > "jakab tanko" <jtanko@ics-ltd.com> wrote in message news:<bmp871$22k$1@news.storm.ca>... > > Hi all, > > > > I have updated my Xilinx software to 6.1 a few days ago and it > > looks like I am in for a ride; the design that worked well under > > the previous version (5.2 with all service packs) wouldn't even > > go through PAR anymore!! I managed to work around this > > by setting thr effort level to maximum for the place&route but > > when I program the FPGA (XC2V4000-5) with this new bitstream > > my board doesn't work anymore!!? > > Anybody having similar problems? > > I guess I shoild have known better: the service pack for this latest > > software creation arrived before the CD with the software did! > > In my humble oppinion the best software from Xilinx was 4.2, > > it's all downhill from there; it seems that a nice GUI is valued more than > > a decent and consistent PAR algorithm these days. > > --- > > jakab -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 62242
On 22 Oct 2003 10:24:06 -0700, Bassman59a@yahoo.com (Andy Peters) wrote: >"David Brown" <david@no.westcontrol.spam.com> wrote in message news:<bn0j25$91g$1@news.netpower.no>... >> I'm using the downloadable version of ispLever for a verilog project on a >> Lattice Mach 4 CPLD chip. The software has both Synplify and Leonardo >> Spectrum available for synthesis. I can build the code (so far, anyway) >> with either tool. Is there any reason why I should choose one over the >> other? > >Well, the full-up version of Leonardo lets you set Verilog parameters >from the GUI or from a TCL script, whereas Synplify does not. This >makes parameterized designs impossible in Synplify, so that tool's >disqualified until that very important feature is added. (Ummmm, >haven't parameters been a part of the language since the beginning???) Yes, and you have been able to set them (along with VHDL generics) in Synplify since version 7.3. Regards, Allan.Article: 62243
Sounds like you need a copy of the verilog standard. You can buy it on ieee's site, its about $100. Ljubisa Bajic ATI Technologies --- My opinions do not represent those of my employer. --- nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) wrote in message news:<bn6gq8$15i5$1@agate.berkeley.edu>... > Luddite Me, who's forgotten most of the Verilog he once knew, needs to > start doing serious HDL-based design. No more schematic-orphans for > me. > > Are there good reference books for Verilog or VHDL? Ideally, > something akin to Java in a Nutshell (Java), the Post Script Red > (language reference) and Blue (tutorial and cookbook) series, or K&R? > > Thanks.Article: 62244
There is a book that has side by side examples of code, one written in VHDL the other in Verilog. Forgot the title but I'll send it tommorow. "Nicholas C. Weaver" <nweaver@ribbit.CS.Berkeley.EDU> wrote in message news:bn6gq8$15i5$1@agate.berkeley.edu... > Luddite Me, who's forgotten most of the Verilog he once knew, needs to > start doing serious HDL-based design. No more schematic-orphans for > me. > > Are there good reference books for Verilog or VHDL? Ideally, > something akin to Java in a Nutshell (Java), the Post Script Red > (language reference) and Blue (tutorial and cookbook) series, or K&R? > > Thanks. > -- > Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 62245
I need info on how to generate a NTSC signal using VHDL (or verilog) and a fpga. I have been frantically looking all over the Internet but can't find a single example. I am familiar with VHDL but not with NTSC at all. Are there any good internet resources out there on NTSC or good books you can recommend that don't require a PhD? Any cores or examples in VHDL (or verilog) floating around out there? Any tips at all? Thanks so much!Article: 62246
On 22 Oct 2003 19:21:24 -0700, info@irvinehosting.net (Shanon Fernald) wrote: >I need info on how to generate a NTSC signal using VHDL (or verilog) >and a fpga. > >I have been frantically looking all over the Internet but can't find a >single example. I am familiar with VHDL but not with NTSC at all. > >Are there any good internet resources out there on NTSC or good books >you can recommend that don't require a PhD? > >Any cores or examples in VHDL (or verilog) floating around out there? > >Any tips at all? > >Thanks so much! Recommendation ITU-R BT.470-6, Conventional Television Systems http://www.itu.int/rec/recommendation.asp?type=folders&lang=e&parent=R-REC-BT.470 (You can download this for free once you've registered.) You'll probably need a 14.31818 MHz clock (4 x the subcarrier frequency). You'll also need a DAC, but this may be as simple as a few resistors if you don't need a good picture quality. Regards, Allan.Article: 62247
I wish to connect a LED to the CONF_DONE pin of a cyclone FPGA to indicate when configuration has been completed. The CONF_DONE pin is an open collector pin that is pulled high via a 10K resistor when configuration is completed. Do I connect my circuit board indicator to ground (through another resistor) or should I connect it to the power rail? Thanks BenArticle: 62248
Hi all,
I have an unusual timing problem that I hope someone can help with.
I've constrained the delay between flip flops within one of my VHDL
macros (called COLFILT) to bo 20ns. This constraint is violated which
in itself is not strange. The odd thing is that the paths violating the
constraint all seem pass through another VHDL macro (called ROBAVG -
variable SReg) which is in the same data path as COLFILT but the two
have no direct connections.
(Note: INT_ColumnFilter is a TNM that defines all flipflops in the
COLFILT VHDL macro)
Can anyone clear this up for me? What is a reference to ROBAVG doing in
a timing path that should only include elements from COLFILT? I've
attached an example from the timing analyser and associated code for
your reference.
Thanks in advance.
================================================================================
Timing constraint: TSColFilt = MAXDELAY FROM TIMEGRP "INT_ColumnFilter"
TO TIMEGRP "INT_ColumnFilter" 20 nS ;
40105 items analyzed, 14 timing errors detected.
Maximum delay is 25.241ns.
--------------------------------------------------------------------------------
Slack: -5.241ns path COLFILT/FiltS<8> to COLFILT/FiltS<5> relative to
20.000ns delay constraint
Path COLFILT/Filt<8> to COLFILT/FiltS<5> contains 11 levels of logic:
Path starting from Comp: CLB_R26C47.S1.CLK (from CLK180)
To Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- --------
CLB_R26C47.S1.XQ Tcko 1.372R COLFILT/FiltS<8>
COLFILT/FiltS_reg<8>
CLB_R19C31.S1.F3 net (fanout=13) 3.545R COLFILT/FiltS<8>
CLB_R19C31.S1.X Tilo 0.738R ROBAVG/Sreg0<5>
COLFILT/C1593
CLB_R22C46.S0.G2 net (fanout=1) 2.903R COLFILT/syn7069
CLB_R22C46.S0.Y Tilo 0.738R COLFILT/N3216
COLFILT/C1585
CLB_R25C47.S0.G3 net (fanout=10) 2.337R COLFILT/C912
CLB_R25C47.S0.Y Tilo 0.738R COLFILT/C839/N27
COLFILT/C1564
CLB_R24C46.S1.F1 net (fanout=1) 1.341R COLFILT/C839/N63
CLB_R24C46.S1.COUT Topcyf 1.445R COLFILT/HPO<4>
COLFILT/C824/C6/C2
COLFILT/C824/C6/C1
COLFILT/C824/C7/C1
CLB_R23C46.S1.CIN net (fanout=1) 0.000R COLFILT/C824/C7/C1/O
CLB_R23C46.S1.COUT Tbyp 0.109R COLFILT/N2915
COLFILT/C824/C8/C1
COLFILT/C824/C9/C1
CLB_R22C46.S1.CIN net (fanout=1) 0.000R COLFILT/C824/C9/C1/O
CLB_R22C46.S1.Y Tciny 0.590R COLFILT/N2917
COLFILT/C824/C10/C1
COLFILT/C824/C11/C0
CLB_R24C47.S0.F4 net (fanout=1) 1.474R COLFILT/N2918
CLB_R24C47.S0.X Tilo 0.738R COLFILT/syn7390
COLFILT/C1414
CLB_R27C47.S1.F2 net (fanout=1) 1.444R COLFILT/syn7390
CLB_R27C47.S1.X Tilo 0.738R COLFILT/syn1816
COLFILT/C1411
CLB_R27C47.S0.F1 net (fanout=1) 0.404R COLFILT/syn1816
CLB_R27C47.S0.X Tilo 0.738R COLFILT/C56/N51
COLFILT/C1407
CLB_R35C56.S0.CE net (fanout=7) 2.901R COLFILT/C56/N51
CLB_R35C56.S0.CLK Tceck 0.948R COLFILT/FiltS<5>
COLFILT/FiltS_reg<4>
-------------------------------------------------
Total (8.892ns logic, 16.349ns route) 25.241ns (to CLK180)
(35.2% logic, 64.8% route)
--
-- IXAcc/ITAcc are outputs to an external accumulator
-- IXSum/ITSum are input from the external accumulators
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library SYNOPSYS;
use SYNOPSYS.attributes.all;
entity colfilt is
port (clk: in STD_LOGIC;
DataBa: in INTEGER range -32768 to 32767;
DataBb: in INTEGER range -32768 to 32767;
DataInReady: in STD_LOGIC;
Height: in INTEGER range 0 to 31;
It: in INTEGER range -256 to 255;
ITSum: in INTEGER range -32768 to 32767;
Ix: in INTEGER range -256 to 255;
IXSum: in INTEGER range -32768 to 32767;
localDiff: in INTEGER range -256 to 255;
reset: in STD_LOGIC;
Width: in INTEGER range 0 to 511;
AccEn: out STD_LOGIC;
AddrA: out INTEGER range 0 to 255;
AddrB: out INTEGER range 0 to 255;
DataAa: out INTEGER range -32768 to 32767;
DataAb: out INTEGER range -32768 to 32767;
DataOutReady: out STD_LOGIC;
ENA: out STD_LOGIC;
ENB: out STD_LOGIC;
ITAcc: out INTEGER range -32768 to 32767;
ItS: out INTEGER range -2048 to 2047;
IXAcc: out INTEGER range -32768 to 32767;
IxS: out INTEGER range -2048 to 2047;
LoadAcc: out STD_LOGIC;
stopData: out STD_LOGIC);
end;
architecture colfilt_arch of colfilt is
--diagram signal declarations
signal BufRead: INTEGER range 0 to 255;
signal BufWrite: INTEGER range 0 to 255;
-- SYMBOLIC ENCODED state machine: FiltSide
type FiltSide_type is (FS1, FS2, FS3, FS4, FS5, FS6, FS7, FS8, FS9, Init2);
signal FiltSide: FiltSide_type;
-- SYMBOLIC ENCODED state machine: InputSide
type InputSide_type is (Init1, IS1, IS2);
signal InputSide: InputSide_type;
begin
--concurrent signal assignments
FiltSide_machine: process (clk)
--machine variables declarations
variable col: INTEGER range 0 to 511;
variable HPO: INTEGER range 1 to 32;
variable row: INTEGER range 0 to 31;
begin
if clk'event and clk = '1' then
if reset='1' then
FiltSide <= Init2;
HPO:=Height+1;
AddrB<=0;
ENB<='0';
BufRead<=0;
DataOutReady<='0';
row:=0;
col:=0;
AccEn<='0';
LoadAcc<='1';
else
case FiltSide is
when FS1 =>
LoadAcc<='0';
if (localDiff>=2*HPO) or (col=Width) or (col=Width-1) then
FiltSide <= FS2;
end if;
when FS2 =>
AddrB<=BufRead;
ENB<='1';
FiltSide <= FS3;
when FS3 =>
IXAcc<=4*DataBa;
ITAcc<=4*DataBb;
AccEn<='1';
AddrB<=BufRead+1;
FiltSide <= FS4;
when FS4 =>
IXAcc<=DataBa;
ITAcc<=DataBb;
AddrB<=BufRead-1;
FiltSide <= FS5;
when FS5 =>
IXAcc<=DataBa;
ITAcc<=DataBb;
AddrB<=BufRead+HPO;
FiltSide <= FS6;
when FS6 =>
IXAcc<=DataBa;
ITAcc<=DataBb;
AddrB<=BufRead-HPO;
FiltSide <= FS7;
when FS7 =>
IXAcc<=DataBa;
ITAcc<=DataBb;
ENB<='0';
FiltSide <= FS8;
when FS8 =>
IxS<=IXSum;
ItS<=ITSum;
AccEN<='0';
DataOutReady<='1';
BufRead<=BufRead+1;
FiltSide <= FS9;
when FS9 =>
DataOutReady<='0';
LoadAcc<='1';
if row=Height and col=Width then
FiltSide <= FS1;
row:=0;
col:=0;
elsif row/=Height then
FiltSide <= FS1;
row:=row+1;
elsif row=Height then
FiltSide <= FS1;
row:=0;
col:=col+1;
end if;
when Init2 =>
FiltSide <= FS1;
when others =>
null;
end case;
end if;
end if;
end process;
InputSide_machine: process (clk)
--machine variables declarations
variable CBW: INTEGER range 0 to 255;
begin
if clk'event and clk = '1' then
if reset='1' then
InputSide <= Init1;
DataAa<=0;
DataAb<=0;
AddrA<=0;
ENA<='0';
BufWrite<=0;
CBW:=1;
stopData<='0';
else
case InputSide is
when Init1 =>
InputSide <= IS1;
when IS1 =>
if CBW=BufRead then
InputSide <= IS1;
stopData<='1';
elsif DataInReady='1' and CBW/=BufRead then
InputSide <= IS2;
DataAa<=Ix;
DataAb<=It;
AddrA<=BufWrite;
ENA<='1';
stopData<='0';
end if;
when IS2 =>
ENA<='0';
if DataInReady='0' then
InputSide <= IS1;
BufWrite<=BufWrite+1;
CBW:=CBW+1;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
end colfilt_arch;
Article: 62249On Thu, 23 Oct 2003 14:37:24 +1000, Kload <aperson@somewhere.com> wrote: >Hi all, > >I have an unusual timing problem that I hope someone can help with. >I've constrained the delay between flip flops within one of my VHDL >macros (called COLFILT) to bo 20ns. This constraint is violated which >in itself is not strange. The odd thing is that the paths violating the >constraint all seem pass through another VHDL macro (called ROBAVG - >variable SReg) which is in the same data path as COLFILT but the two >have no direct connections. > >(Note: INT_ColumnFilter is a TNM that defines all flipflops in the >COLFILT VHDL macro) > >Can anyone clear this up for me? What is a reference to ROBAVG doing in > a timing path that should only include elements from COLFILT? I've >attached an example from the timing analyser and associated code for >your reference. Each CLB contains eight flip flops and LUTs. A given CLB may contain logic from separate parts of your design (e.g ROBAVG and COLFILT). The CLB "name" is taken from one of the flip flops or LUTs it contains. Thus your "COLFILT" timing paths may seem to be passing through "ROBAVG", even though there is no actual relationship between them (except that they are sharing a CLB). BTW, use fpga_editor in future. Regards, Allan.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z