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There's an announcement on the Xilinx web site that the XC3S50, XC3S200, XC3S400, and XC3S1000 are now shipping. Is that the "real" XC3S50, or the XC3S50J? For my application, I need the BlockRAMs and 3.3V tolerant I/O, so the XC3S50J won't do. It seems to me to be very misleading that the announcement claims that they are shipping now, and gives prices, but only in the footnote is it revealed that those are the prices for the end of 2004. Are today's prices so high that marketing is afraid to publicize them? I notice that Altera states OEM prices for mid-2004, which is somewhat more useful but still not ideal. I hope this doesn't turn into another one-upmanship game: "We'll state prices for a year from now." "Oh yeah? We'll state prices for TWO years from now! Nyah, nyah!"Article: 62026
My experience with Altera's mySupport is pretty bad. Out of 5 questions I asked them none was replied to my satisfication. When I followed up, they asked for my design files, when it was completely unnecessary. I wasn't really asking for any design problems, but rather capabilities and features of the Cyclone.Article: 62027
It was for a bar game, although there are several board games that use more than 2 dice. Yahtzee, for example uses 5 as I recall.
Jim Granville wrote:
> Ray Andraka wrote:
> >
> > I did a similar 3 die design way back when (ca 1976) using TTL parts. > It could easily be done in a small CPLD and a short time with
> > current tools.
>
> With some care (challenge for todays students ?) I believe one
> can pack 2 dice into a 16V8 - smallest/cheapest programmable logic
> device made.
>
> Ideal for backgammon etc....
>
> What games need 3 dice ?
>
> -jg
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 62028"Eric Smith" <eric-no-spam-for-me@brouhaha.com> wrote in message news:qhismoiy83.fsf@ruckus.brouhaha.com... > There's an announcement on the Xilinx web site that the XC3S50, XC3S200, > XC3S400, and XC3S1000 are now shipping. Is that the "real" XC3S50, > or the XC3S50J? For my application, I need the BlockRAMs and 3.3V tolerant > I/O, so the XC3S50J won't do. The XC3S50J FPGAs are available today. Samples of the XC3S50 (no 'J' suffix) with 3.3V-tolerant I/O, block RAM, multipliers, and Digital Clock Managers (DCMs) are available at the end of the year. Until then, you might consider prototyping with the XC3S200 that has block RAM and 3.3V I/O. The XC3S200 has the same package footprints as the XC3S50. > It seems to me to be very misleading that the announcement claims that > they are shipping now, and gives prices, but only in the footnote is it > revealed that those are the prices for the end of 2004. Are today's prices > so high that marketing is afraid to publicize them? I notice that Altera > states OEM prices for mid-2004, which is somewhat more useful but still > not ideal. I hope this doesn't turn into another one-upmanship game: > "We'll state prices for a year from now." "Oh yeah? We'll state prices > for TWO years from now! Nyah, nyah!" Not to defend Marketing folks, but quoting forward pricing is valuable information when you are considering FPGAs in a high-volume product. Today's small volume prices are indeed higher just as you might expect with any semiconductor product early in its life cycle. Buying a few parts for prototyping today can be many times more expensive than buying a large volume when then product goes into production a year from now. We generally try to quote projected volume OEM pricing for a least a year in the future just so that designers know what is possible in higher production volumes. FPGAs have the steep pricing decreases associated with other high-volume standard products like memories and processors. At product launch, we announced that the XC3S1000 at 250K unit levels would be less than $20 in 2004. http://www.xilinx.com/prs_rls/silicon_spart/0333spartan3.htm The latest release, based on current manufacturing experience with the product, further clarifies that the XC3S1000 at 250K unit levels will be less than $12 in late 2004. Again, this was meant only to provide a volume-pricing data point for products that would go into production about one year from now. http://www.xilinx.com/prs_rls/silicon_spart/03142s3_pricing.htm --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASICArticle: 62029
I agree that their pricing is somewhat misleading. In addition, their
'advertised' pricing ("million gate FPGA for under $xx) is for
unbelievably high quantities. At least some other companies provide
reasonable budgetary pricing. Fairchild is closer to 1000 for their
web page pricing, Analog Devices is 10,000, etc.
A quick email to a distributor, fortunately, provides realistic
quantity pricing.
Jake
Article: 62030"Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> writes: > The XC3S50J FPGAs are available today. Samples of the XC3S50 (no 'J' > suffix) with 3.3V-tolerant I/O, block RAM, multipliers, and Digital Clock > Managers (DCMs) are available at the end of the year. Until then, you might > consider prototyping with the XC3S200 that has block RAM and 3.3V I/O. The > XC3S200 has the same package footprints as the XC3S50. Using the XC3S200 or even the XC3S400 for my prototype would be reasonable, but Arrow, Avnet, and Insight have no stock of either part. Avnet and Insight do apparently have the XC3S50J, though.Article: 62031
In article <d6ad3144.0310161719.3535a05a@posting.google.com>,
Jake Janovetz <jakespambox@yahoo.com> wrote:
>I agree that their pricing is somewhat misleading. In addition, their
>'advertised' pricing ("million gate FPGA for under $xx) is for
>unbelievably high quantities. At least some other companies provide
>reasonable budgetary pricing. Fairchild is closer to 1000 for their
>web page pricing, Analog Devices is 10,000, etc.
Also, it depends on the part family as well. The press release "By
the boatload" prices for the V2Pro are based on 10k unit boatloads
rather than 250k unit boatloads.
--
Nicholas C. Weaver nweaver@cs.berkeley.edu
Article: 62032Has anybody made a table of "corrected" prices to include a ROM or such to load the FPGA? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 62033
Hal Murray wrote: > > Has anybody made a table of "corrected" prices to include a ROM or such > to load the FPGA? What ? - you mean that's not free ?! :) - jgArticle: 62034
Eric Smith wrote: > > "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> writes: > > The XC3S50J FPGAs are available today. Samples of the XC3S50 (no 'J' > > suffix) with 3.3V-tolerant I/O, block RAM, multipliers, and Digital Clock > > Managers (DCMs) are available at the end of the year. Until then, you might > > consider prototyping with the XC3S200 that has block RAM and 3.3V I/O. The > > XC3S200 has the same package footprints as the XC3S50. > > Using the XC3S200 or even the XC3S400 for my prototype would be > reasonable, but Arrow, Avnet, and Insight have no stock of either part. > Avnet and Insight do apparently have the XC3S50J, though. I am planning to use the XC3S400 (unless I find some more surprises) and I am being told the part will be shipping in production by the end of the year. I specifically asked for samples (not ES parts) by the end of November and was told they expect that would work. Until I said end of November though, they were hemming and hawing. So I would not expect to get any before then. Don't expect them to show up on the disti's web sites. You need to talk to them to get in line. Remember, your disti is your friend! As to pricing, I belive you can take the marketing number for gazilions and multiply that by 2 for qty 250 and by 1.5 for qty > 1000. When I pushed them on price, they eventually came back with a decent number. This is all 1Q04 pricing of course. Don't take a high number for a final answer, let them know that the Cyclone parts fit your sockets too. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 62035
Hi all, I am currently working on a project in which i want to drive a dot matrix VFD using a CPLD - if anyone has any previous experience of this and has got any tips i would be most gratefull. Thanks, MattArticle: 62036
soar2morrow@yahoo.com (Tom Seim) wrote in message news:<6c71b322.0310032134.4b3135a7@posting.google.com>...
> Marc Guardiani <marc@guardiani.com> wrote in message news:<5T2fb.20355$541.16572@nwrdny02.gnilink.net>...
> > What OS are you using? Xilinx dropped NT support with version 5.1i (even
> > though it worked). Now with 6.1i I can't get Impact or Core Generator to
> > run.
> >
>
> XP Home. I have since been advised to turn off virus scanning (McAfee
> in my case) during installation. I have done this, resulting in mixed
> success. Now the project nav starts ok, but if I try to launch coregen
> it fails. I have gone thru NUMEROUS uninstalls/installs with 2
> different computers running 2000 and XP Home without success. I did an
> install on a virgin laptop running XP PRO w/o problems. I am in touch
> with tech support and will advise on the outcome.
>
> Tom
I had a problem with ISE6.1 not opening on Windows XP Home. I
read your posting and turned off the Auto-Protect mode of the Norton
Anti-virus. That solved the problem. ISE6.1 opens and works OK with
the Anti-virus Auto-Protect mode OFF. ISE6.1 works correctly on
Windows XP PRO with the Auto-Protect mode ON.
Thanks for your help,
Bill Hanna
Article: 62037Hi all, I can't execute any program from external SRAM memory. The program is copied from FLASH to SRAM and the executed. This is done with a bootloader. Here you are the details of the steps I do: 1-. I create a C program 2-. I compile in EXECUTABLE mode with _TEXT_START_ADDRESS = SRAM base address. 3-. I create the binary file of the "executable.elf" from the XMD with the next GCC command: "mb-objcopy -O binary executable.elf executable.bin" Now I have 2 options: -- FIRST 4-. I compile the FLASH charger in EXECUTABLE mode with _TEXT_START_ADDRESS = 0, in order to be stored in the internal BlockRAMs. 5-. I program the FPGA with the resulting "download.bit" bitstream. 6-. I burn the "executable.bin" file to the FLASH memory using a FLASH writer I have done that communicates the PC with the MicroBlaze's flash charger via serial port. --SECOND 7-. I burn the "executable.elf" file with a tcl file that some people have sent me. This tcl uses the XMD tcl command "xdownload". ---- 8-. I compile the bootloader in XMDSTUB mode. This program copies the contents of the flash memory into the sram memory and then branches to the SRAM base address. 9-. I download it to the FPGAs BlockRAMs through the debugger. OK. Now firstly I compare if the FLASH contents are the same as the "executable.bin" file. Always they are. Then I copy it to the SRAM and I check it. Always has the same content as the FLASH. Finally, the next instruction of the bootloader is a branch to the SRAM base address. Once I execute MICROBLAZE becomes blocked and doesn't do anything. Does anybody know why? Am I doing something wrong? I hope the details I've done can be easily understood. Thanks for all the help you can give me. Arkaitz.Article: 62038
If I create a two-FF chain (with common clock), XST will likely pull those two FFs into a SRL16. Is it permissible to use two bits of a SRL16 as a synchroniser in this way? (It surely must be the shortest-possible path between two FFs). Peter Alfke <peter@xilinx.com> wrote: :You should always be concerned about metastability, whenever :asynchronous signals are being synchronized. Let me add some numbers to :Phil Freidin's excellent comments: : :Metastability creates unpredictable additional settling delays (even :oscillations can be considered delays to valid out). The probability of :a specific max delay depends on the clock rate, the data rate, and the :IC technology. : [snip]Article: 62039
Hi,guys!
I have maybe a silly question,but it confused me all the day,the
question is:
I have a function with 5-inputs and one output,and thus XST maps to
2 LUTs in the Xilinx FPGA,but I think its a bit too wasteful--there is
about 5000 such functions in my design.So I want to use a 4-input LUT
and a D-LATCH with async clear instead(one of the 5-inputs is used to
clear the output).But,the question is,I do use the LUT and latch in
the same slice,but the other LUT in the same slice can not be used by
other logic!
Why my method could not work?Is there any resource conflict?
Appreciate for your help!Thanks!
ps.
My verilog code is like this:
always @ (zero_flag or a or b )
if (zero_flag)
o_tmp_data <= 14'h0 ;
else if (b[1:0] == 2'b00)
o_tmp_data <= a[13:0] ;
else if (b[1:0] == 2'b01)
o_tmp_data <= {a[12:0],1'b0} ;
else if (b[1:0] == 2'b11)
o_tmp_data <= ~a[13:0] ;
else
o_tmp_data <= {~a[12:0],1'b1} ;
or I use two blocks and the other block is exactly like what Xilinx
suggests in its template,but the XST could not recognize it as a LUT
and a latch,and still 2 LUTs.I wonder if I miss something?
Article: 62040Hi Sorry to bother the group with something I really should have been able to figure out myself, but I'm sort of pressed for time, so I hope you bear with me. I have some (limited) knowledge of the (modern) Xilinx Virtex 'Slice', and how it is constructed, so to speak. But how similar is the Altera FPGAs' building blocks, and what are they called? Oh, and how, if at all, similar are the two?Article: 62041
Dear Sir or Madame,
when I try to compile a testbench including the following process
I get the following error message:
"Error: VHDL Wait Statement error at tb_reservoir_positions.vhd(55):
Wait Statement must contain condition clause with UNTIL keyword."
process
begin
t_reset <= '1', '0' after 100 ns;
wait;
end process;
I thought that is was a legal wait-statement when writing a testbench for functional
simulation.
So what could be the reason for that error message?
(p.s. I am using the Quartus II WebEdition 3.0)
Kind regards
Andrés Vázquez
G&D System Development
Article: 62042I'm planning to use Microblaze in my project without using DMA devices. It seems than Microblaze don't have any instruction like "read and auto- increment register" so if I have to transfer data from a location to another I have to implicitaly increment pointer. Anyone knows if there is some solution that allows to transfer data with the lowest number of cycles?Article: 62043
Hi,
Since MicroBlaze branches on register values you can first load a
register with the length.
MicroBlaze also have an address mode which is address = regA + regB.
I would also move from the end to the beginning like this
addi r5,r0,#Src_Addr
addi r6,r0,#Dest_Addr
addi r7,r0,#(4*(Nr_of_Words-1)
.loop
lw r8,r5,r7
sw r8,r6,r7
bneid r7,loop
addi r7,r7,-4
This will create a loop with 1 load, 1 load, 1 branch and 1 decrement.
The number of clock cycles depends on the latency to the memory but it
will be 2 memory access + 3 clock cycles if the code is executed from
the LMB memory.
Göran Bilski
C.Amendola wrote:
>
> I'm planning to use Microblaze in my project without using DMA
> devices. It seems than Microblaze don't have any instruction like
> "read and auto- increment register" so if I have to transfer data from
> a location to another I have to implicitaly increment pointer. Anyone
> knows if there is some solution that allows to transfer data with the
> lowest number of cycles?
Article: 62044Matt North wrote: > Hi all, > > I am currently working on a project in which i want to drive a dot matrix > VFD using a CPLD - if anyone has any previous experience of this > and has got any tips i would be most gratefull. > > Thanks, > Matt > > Hi Matt, Using dot matrix, you have to multiplex the Row and give a command on the columns. It 'is itself very easy, but you have to make sure about the current specification of your dot led matrix. The most important thing is the compromize between the current of each led on one Row and the rom multiplexage. In normal use, you drive LED with static 10mA or 20mA, but in the dot matrix case you need to drive something between 50mA and 100mA dynamic PWM current by led. So, your CPLD CMOS specification will not be able to drive so much PWM current. You have to use line driver or MOS-FET N and P after your CPLD. If you will play on 3.3V, you have to work with a transistor having a small Rds (Drain Source Resistor), not more 1.5 Ohm. We are doing a dot matrix module for our SPARTAN-3 rapid prototyping platform. I will receive the PCB in two weeks, I can send you a sample of our dot matrix board if you want. Let me know Laurent www.amontec.comArticle: 62045
"Matt North" <m.r.w.north@rl.ac.uk> wrote in message news:bmo5e6$16o2@newton.cc.rl.ac.uk... > I am currently working on a project in which I want to drive a dot matrix > VFD using a CPLD - if anyone has any previous experience of this > and has got any tips I would be most grateful. I looked at using various VFDs for use in audiophile radio several years ago. They are quite a significant cost, and quickly rises with number of pixels. I liked the idea of graphic VFDs, and the ones with driver chip-in-glass looked nice but these are essentially HV shift registers and the pixel to bit position mapping is rather inconvenient. The sales rep stretched the truth by saying they can be driven by an AVR. I worked out that it would have to be spending c. 85% of its time shifting in the pixels. A colleague managed to drive such a display with c. 5% of CPU time, by using DMA to transfer the bits. However, that was with an H8. This was not economical in the radio. Your project certainly sounds feasible. VFDs want supply rails applied in particular order, and can be destroyed if scanning stops (just as TV tubes don't like the electron beam to stop. So I feel hardware is better than software-driven refresh since the latter could crash. Logic gates can handle the bit-to-pixel mapping far better than software. Will you be using this CPLD with a micro, and if so what type? How would you like the micro to access the pixels? Memory mapped? How fast will the display be expected to change? Will you be wanting animations, smooth scrolling, etc?Article: 62046
I need to program an obsolete Lattice component, the MACH211-15JC. I would like to do this with the software tool ispLEVER v3.0 Problem is that I cannot select that device out of the list with the available devices. In ispLEVER I can choose for the MACH211SP, but (in my case) I can't use it. The MACH211SP is ISP and there are pin 13 and 35 (and another few) reserved for JTAG configuration. I need absolutely to program the MACH211-15JC because I have to reprogram the device which is used in an older hardware application. And of course, I need pin 13 and 35 as input ports. So question is, which device do I have to select, or are there some files which I have to install to make the device available in the list. So if anyone can help me, I would appreciate it very well. BartArticle: 62047
ric wrote:
>
> Hi,guys!
> I have maybe a silly question,but it confused me all the day,the
> question is:
> I have a function with 5-inputs and one output,and thus XST maps to
> 2 LUTs in the Xilinx FPGA,but I think its a bit too wasteful--there is
> about 5000 such functions in my design.So I want to use a 4-input LUT
> and a D-LATCH with async clear instead(one of the 5-inputs is used to
> clear the output).But,the question is,I do use the LUT and latch in
> the same slice,but the other LUT in the same slice can not be used by
> other logic!
> Why my method could not work?Is there any resource conflict?
> Appreciate for your help!Thanks!
>
> ps.
> My verilog code is like this:
> always @ (zero_flag or a or b )
> if (zero_flag)
> o_tmp_data <= 14'h0 ;
> else if (b[1:0] == 2'b00)
> o_tmp_data <= a[13:0] ;
> else if (b[1:0] == 2'b01)
> o_tmp_data <= {a[12:0],1'b0} ;
> else if (b[1:0] == 2'b11)
> o_tmp_data <= ~a[13:0] ;
> else
> o_tmp_data <= {~a[12:0],1'b1} ;
> or I use two blocks and the other block is exactly like what Xilinx
> suggests in its template,but the XST could not recognize it as a LUT
> and a latch,and still 2 LUTs.I wonder if I miss something?
You didn't say which Xilinx part you are using and I am not intimate
with all of them. But generally you can't use two different signals for
the async control of the FFs in a slice. The async control is shared
between the two FFs.
Perahps you can find common signals to your 5 input functions and
combine them in a LUT. This signal can be run to a group of 4 input
functions which will then each fit in a single LUT.
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Article: 62048Panic wrote: > > Hi > > Sorry to bother the group with something I really should have been able to > figure out myself, but I'm sort of pressed for time, so I hope you bear with > me. > > I have some (limited) knowledge of the (modern) Xilinx Virtex 'Slice', and > how it is constructed, so to speak. But how similar is the Altera FPGAs' > building blocks, and what are they called? > > Oh, and how, if at all, similar are the two? I find it a bit difficult to learn all the ins and outs of each companies differnt products, so I don't blame you for asking here. But check with the data sheets to really understand it all. The Xilinx slice is composed of a pair of LUTs, a pair of FFs, carry chain and some other misc logic to optimize 5 input functions and other similar operations. There are different numbers of slices to a CLB depending on the family, 1, 2 or 4 slices. Altera calls a LUT plus FF an LE. LEs are grouped into Logic Array Blocks (LABs) of 8 or 10 LEs depending on the family. There are two chains within a LAB, a fast carry like the Xilinx also a "Cascade" chain for doing large functions. This is similar to the way Xilinx can combine LUTs within a CLB, but runs the length of the LAB and implements a very fast, two input AND gate at each LUT output. You can analyze the differences on paper all day, and you still won't know how your design will do in either family of parts. The best thing to do is to write your HDL to be generic and see how it fits. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 62049
"rickman" <spamgoeshere4@yahoo.com> wrote [......] Thanks a lot! > You can analyze the differences on paper all day, and you still won't > know how your design will do in either family of parts. The best thing > to do is to write your HDL to be generic and see how it fits. Sure, and normally I would. But I've studied a paper written by François-Xavier Standaert, where he and some other reasearchers optimizes a implementation of the Rijndael algorithm to better match the Xilinx slice. And the results are impressive! So I wanted to try and figure out how I could transfer such a design strategy to the Altera-FPGA I am working on (EPXA1F484C1). But in order to do that, I need to understand how I can make the different stages fit in Alteras slice-equivalent :p I will try and grab a detailed data sheet from Alteras website, allthough I have downloaded all the documentation marked for EPXA1, and haven't seen anything like it in there. But I suppose that if I search for LC or LAB layout or something similar, I will eventually find it :-) -"Panic"
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