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Hi, For those of you who might be interested in such prototyping boards, and have the time to fab it yourself, I have designed such a board and you can get the gerber photoplots for it at: http://www.engr.sjsu.edu/crabill/projects/ Have fun, I sure did... I've tested this board out and it works as intended. You can use it with the Xilinx v3.0 PCI32 LogiCORE. Eric mikegw wrote: > > > I would happily buy one. > > > > Ralph > > > I would too. But as long as it is not shipped by UPS. > I would cost more than that to ship to Australia. > Documentation would be important as in this > case I am a bit thick. > > MikeArticle: 62726
The Big Bear wrote: > Leon Heller wrote: > >>The Big Bear wrote: >> >> >>>I've got a design for a $40 assembled and tested fpga dev board that is >>>on a pci card for use in a standard PC (probably running linux). It would >>>have ethernet and some other ports for experimentation, but basically the >>>fpga would become a configurable pci device. Possible applications could >>>be mpeg encoding/decoding, encryption/decryption, or just plain >>>experimentation with fpga technology. I'm debating whether to do a >>>production run of these things, but if they won't sell I don't want to >>>bother. Would anyone consider buying such a thing? >> >>What FPGA? > > > XC2S100E 100K gates 2,700 logic cells. It's a Xilinx part Put me down for one, then. LeonArticle: 62727
"Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message news:<bobfb4$2gq$1$8300dec7@news.demon.co.uk>... > "john jakson" <johnjakson@yahoo.com> wrote in message > news:adb3971c.0311042304.43735b02@posting.google.com... > > [snip much] > > > I am curious to know what folks think of combining HDL,CSP,C rather > > than keeping HW & SW miles apart as in conventional engineering. > > See Celoxica's products. > > And observe how they've backed away from a reasonably pure CSP > approach like yours, and put more emphasis on the pure-C thing. > > Software people have an irrational and passionate distaste for > fine-grained parallelism. I don't think you have much chance > of changing their collective mind. > Just as HW people generally view plain C as a likely HDL with great discomfort as has been seen by the no of deceased C HDL companies. But Celoxica is aiming at a different crowd, not hardcore HW Asic guys. I am familiar with HandelC to some degree, I see them a couple of times a year at different shows. Every time I see them I get better insight but the question remains, why use plain C with CSP semantics (Occam is underneath it right) when HDLs are far better at describing HW. Every conversation with Celoxica people tells me that you still have to describe the parallelism directly which is why it can be synthesized. It would surprise me if its possible to use HandelC in a meaningfull way and not use any of the inherited Occam keywords. Then again HDLs are not too good for describing purely seq processes or SW so bridging the 2 worlds is difficult with either HDL or general seq SW languages. So I am addresing the audience that is comfortable on both sides and wants to move processes between HW & SW. This is not quite the same thing as SystemvVerilog as that is clearly only aimed at big $ ASIC engineers. VHDL perhaps already is a bridge language but I have never been partial to it. If Celoxica included a Transputer IP core with their tool, I imagine HandelC could also be a bridge since code could either run as synthed HW or run as plain Occam style code. Regards John johnjaksonATusaDOTcomArticle: 62728
"Michelle" <sleepymish@hotmail.com> wrote in message news:2b3db7ca.0311050941.3dc9ee2c@posting.google.com... > Hi, > > I'm a newbie to FPGA and Linux world. I have a general question > concerning both. > > I have a workstation with Linux installed. A Virtex II Pro FPGA Module > is plugged in the backplane of the workstation. I'm wondering if I > need to write a device driver for the FPGA module in order for the > Linux box to recognize the card? > > I want a software program running on the Linux machine to be able to > poll a few registers on the FPGA module, bascially through memory map. > Is this possible without a device driver? Was the board designed to work with Linux? Some years ago I worked with a variety of boards on Sun workstations. Sun provided device drivers that would map memory as an I/O device so that any device could be accessed that way. A little less convenient than a dedicated device driver, but it did work. I don't know that Linux provides that, though. -- glenArticle: 62729
sleepymish@hotmail.com (Michelle) wrote in message news:<2b3db7ca.0311050941.3dc9ee2c@posting.google.com>... > I have a workstation with Linux installed. A Virtex II Pro FPGA Module > is plugged in the backplane of the workstation. I'm wondering if I > need to write a device driver for the FPGA module in order for the > Linux box to recognize the card? No. By backplane do you mean PCI? > I want a software program running on the Linux machine to be able to > poll a few registers on the FPGA module, bascially through memory map. > Is this possible without a device driver? You might want to try: http://www.linuxjournal.com/article.php?sid=5442 "User Mode Drivers" Which talks about writing directly to PCI memory space. This is not a particularly nice/good/proper thing to do, but it is quick and dirty and good for starters. Alan Nishioka alann@accom.comArticle: 62730
The concept of "fair" really has no meaning. In a free market, fairness is regulated by the ability to quit and go elsewhere if you don't want to work free overtime, or, to look at it another way, lower your hourly wage. Perhaps you mean "legal". But employers of salaried people have quite a bit of leeway in this area. Normally the laywers who file a class action lawsuit get a lot of people to sign up and then make a settlement with the company that involves paying a large sum to the lawyers and giving the members of the class a gift certificate to Hardee's. The question of whether the overtime is legal or not is probably beside the point, since the company would rather settle by paying off the class action lawyers. The settlement actually hurts employees, because some of the money that would have been available for salaries goes to pay the lawyers. So I must guess that you represent the lawyers. -Kevin "Kent Ross" <kentr0ss@yahoo.com> wrote in message news:9218691.0311051125.7c0ebb6@posting.google.com... > Is it fair for programmers to work long hours of overtime and not get > paid for the work? If you are a programmer who has been working for a > while you probably > know there can be some issues with not getting paid for overtime. > Companies can take advantage of programmers with the long hours needed > to complete projects. If you feel you are having difficulty getting > paid for what you have > done, you are not alone. There are people out there who are willing to > lend a hand. Check out this site: > http://www.bigclassaction.com/class_action/computer.html > You can send them a complaint for free and they pass them along to > lawyers for evaluation. This one seems to be specifically for > programmers who have worked for Computer Sciences Corporation. There > is, however, lots of other info on the site that might be more to what > you need, but this is a currently hot subject. I hope this might help > somebody out. > > kr0Article: 62731
We are trying to implement a decoder design on a Spartan II(2s200), and when I run the Synthesize process, the message window shows that all verilog modules are being compiled, however the process seems to take forever when it is trying the compile the unisim_comp.v file which is provided by ISE. Can anybody guess what the problem could be and/or the possible solution. Thanks in advanceArticle: 62732
Mike Treseler wrote: > Jeff Cunningham wrote: > >> I am somewhat dissapointed that I have never seen any viable 3rd party >> FPGA IP for the firewire link function. Does anyone know of any such >> IP available now or on the horizon? > > > Maybe one of these? > http://www.google.com/search?q=firewire+link+layer+synthesizable+core+2003 > > -- Mike Treseler > I think those links all refer to IP that I would call "asic" flavored, by which I mean it has been synthesized using synopsis design compiler and any targeting of fpgas is a non-optimized prototyping port. I have not done exhaustive checking, but I get the idea these are very expensive. The open cores one is only in the early planning stage. What I would like to see is a 1394 link function available in something like the xilinx alliance core program - where I can assume the heavy lifting of optimizing the design for fpga implementation and proving it out has been done, i.e. where the risk would be similar to using the alliance core pci interface for example. And where the cost would be in a similar ball park. JeffArticle: 62733
Hi, I have been following this thread with great interest. If you need a processor with links to/from the processor register file then MicroBlaze could be the answer. MicroBlaze has 18 direct links (in the current version, the ISA allows up to 2048) and 8 new instructions for sending or receiving data to/from the register file. The connection is called LocalLink (or FSL) and has this features - Unshared non-arbitrated communication - Control and Data support - Uni-directional point-to-point - FIFO based - 600 MHz standalone operation Göran john jakson wrote: >"Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message news:<bobfb4$2gq$1$8300dec7@news.demon.co.uk>... > > >>"john jakson" <johnjakson@yahoo.com> wrote in message >>news:adb3971c.0311042304.43735b02@posting.google.com... >> >>[snip much] >> >> >> >>>I am curious to know what folks think of combining HDL,CSP,C rather >>>than keeping HW & SW miles apart as in conventional engineering. >>> >>> >>See Celoxica's products. >> >>And observe how they've backed away from a reasonably pure CSP >>approach like yours, and put more emphasis on the pure-C thing. >> >>Software people have an irrational and passionate distaste for >>fine-grained parallelism. I don't think you have much chance >>of changing their collective mind. >> >> >> > >Just as HW people generally view plain C as a likely HDL with great >discomfort as has been seen by the no of deceased C HDL companies. But >Celoxica is aiming at a different crowd, not hardcore HW Asic guys. I >am familiar with HandelC to some degree, I see them a couple of times >a year at different shows. Every time I see them I get better insight >but the question remains, why use plain C with CSP semantics (Occam is >underneath it right) when HDLs are far better at describing HW. Every >conversation with Celoxica people tells me that you still have to >describe the parallelism directly which is why it can be synthesized. >It would surprise me if its possible to use HandelC in a meaningfull >way and not use any of the inherited Occam keywords. > >Then again HDLs are not too good for describing purely seq processes >or SW so bridging the 2 worlds is difficult with either HDL or general >seq SW languages. So I am addresing the audience that is comfortable >on both sides and wants to move processes between HW & SW. This is not >quite the same thing as SystemvVerilog as that is clearly only aimed >at big $ ASIC engineers. VHDL perhaps already is a bridge language but >I have never been partial to it. If Celoxica included a Transputer IP >core with their tool, I imagine HandelC could also be a bridge since >code could either run as synthed HW or run as plain Occam style code. > >Regards >John > >johnjaksonATusaDOTcom > >Article: 62734
sleepymish@hotmail.com (Michelle) wrote in message news:<2b3db7ca.0311050941.3dc9ee2c@posting.google.com>... > Hi, > > I'm a newbie to FPGA and Linux world. I have a general question > concerning both. > > I have a workstation with Linux installed. A Virtex II Pro FPGA Module > is plugged in the backplane of the workstation. I'm wondering if I > need to write a device driver for the FPGA module in order for the > Linux box to recognize the card? > > I want a software program running on the Linux machine to be able to > poll a few registers on the FPGA module, bascially through memory map. > Is this possible without a device driver? > > Thanks in advance for all the help. > > Michelle The better FPGA board makers should include a ready to go PCI device driver. For Windows this would have been something like Numega IIRC, but for Linux I am less sure, most of my old links are long gone (thanks to MS ...). Who is the board vendor?, check their site for driver support. John johnjaksonATusaDOTcomArticle: 62735
I want to implement a smart card reader on a FPGA Cyclone Altera with NIOS processor inside. Do you know any device driver (free or not) ISO 7816 compatible? Thanks for your help Giaccaglini Giorgio Aethra ItalyArticle: 62736
Here comes the end.. The problem IS brought by the macro's reference comp(or something like that , I am not sure),because the placed macros(one slice each) are at the same position in the CLBs,and this reduces much routing agility . But in the design of the macro , I can not modify the attribute to let it not remember the position in the CLB . What I do is after the "map" process of the whole design , read in the ncd file in FPGA Editor and select all the macros and unbind them,then the tool will take all of them as ordinary components,and the PAR would not fail.Also , the area is saved by the use of these macros . In my design , the slice usage drops from 89% to 78%(XC2VP40). That's all,hope it helps , though seems just like talking to myself...Well, glad to be here and thank you for all the help , have a nice day!Article: 62737
"Andras Tantos" <andras_tantos@tantos.yahoo.com> wrote in message news:<3fa942a5@news.microsoft.com>... > > I will write a open source arm vhdl model from > > this month on. I hope to have it ready in > > approximately 2 months using LeonSoc as a framework > > and implementing a arm1 integerunit. Anyone that wants > > to participate is wellcome. > > Konrad Eisele > > Many tried, all got kicked in the back by ARM. If you can create something > useful, get ready for a contact from one of their lawyers, > > Andras Tantos why write it from scratch? the nnARM source codes can be found with google with no problems. the synthesis result is unfortunatly quite big fits barely into XC2S600E would be nice to have smaller core though ;) antti PS the ARMlayers tried to take nnARM off from public internet, but its still downloadable, so the layers are not doing very good job.Article: 62738
Hi, I have successeuse config the virtex2Pro with a elf file and bit stream file independently. But how to make the powerpc and the fpga logics work together? Can I use the BRAM as an interface between the FPGA and powerpc? It means that I read data from the internal BRAM by the powerpc after the FPGA logics stored value in BRAM.What's the function in the C library is relating to the internal BRAM data retrieval? For the FPGA design, I am using System Generator, can i specify the interface or BUS (PLB) within the syste mgenerator environment, which is the communication channel between the powerpc and FPGA? or there are other approach to have SW/HW codesign by using system generator? Many thanks!! TerrenceArticle: 62739
Hello all
I am trying to implement the following logic in a xilinx XCS05xl
FPGA.
I have a 15 bit binary counter. I need to store its count value
on the occurrence of an event. Some time later I need to shift the stored
counter value out of the FPGA in a serial fashion under the control
of a clock.
What I currently have is:
-----------------------------------------------------------------------
input clear;
reg clear;
input ACB_Decade_Count_Enable;
input ACB_Read_Trigger_Address_Clk;
output ACB_Trigger_Address_Output;
reg ACB_Trigger_Address_Output;
reg [14:0] Store_Trigger_Acquisition_Count; // Storage for counter count.
// Store the count value when ACB_Decade_Count_Enable is high.
always @ (ACB_Decade_Count_Enable)
begin
if(ACB_Decade_Count_Enable) // event happened input is high.
Store_Trigger_Acquisition_Count <= OUT_Acquisition_Count;
end
// Now shift out the stored count serially.
always @ (posedge clear or posedge ACB_Read_Trigger_Address_Clk)
begin
if(clear)
begin
ACB_Trigger_Address_Output <=0;
end
else
begin
ACB_Trigger_Address_Output <=Store_Trigger_Acquisition_Count[14];
Store_Trigger_Acquisition_Count <= Store_Trigger_Acquisition_Count << 1;
end
end
-----------------------------------------------------------------------
With this code my synthesis step gives the following errors.
Warning - Latch inferred in design "My block" read with
'hdlin_check_no_latch'(HDL - 307)
Error - The net /../my block/Store_Trigger_Acquisition_Count<13> has more
than one driver(FPGA-CHECK-5)
The last error is repeated for all bits in Store_Trigger_Acquisition_Count.
The logic above seems correct in my head but Im not an FPGA expert.
Obviously I need a different implementation. Any suggestions.
Many thanks for all suggestions in advance.
Denis
Article: 62740"Kolja Sulimma" <news@sulimma.de> wrote in message news:b890a7a.0311040449.77eabb34@posting.google.com... > > Thanks > > > > Just so I understand you, if I want to "realise" my c code in a FPGA > > array, I can upload the code, data and the processing array. Run it and > > download the data? > Yes. But you are likely to spend a lot of effort designing the > processing array. > I guess that if you post the equation (maybe a simplified version), > the precision you need and the number of elements in a typical data > set you will get a pretty good estimate from this group about how well > this can be solved in FPGAs. > > Kolja Sulimma I will post the equations if I am able. This particular project is not mine and as such I do not know if I am able to post their work. I will know in the next week. But in the meantime the basic premise of the calculations is as follows.... From time zero until time x, for each time step, calculate for n particles (Typically hundreds to thousands) their position in the next time step. Factors affecting the new position are 1)interaction between each particle 2)particle velocity and mass 3)media that the particle is in. Currently the system is simplified by locating the particles into neighbourhoods so that effects from distant particles is ignored. Again thanks all for your help MikeArticle: 62741
Kevin Neilson wrote: > > The concept of "fair" really has no meaning. In a free market, fairness is > regulated by the ability to quit and go elsewhere if you don't want to work > free overtime, or, to look at it another way, lower your hourly wage. A free market would include slavery and assorted other evils that we have made political decisions to ban, and remember that "fair" has no meaning in a completely unregulated market. "Fair" is a political concept. We have a regulated market, that means that there are rules determing the relationships between employers and employees. If you are "salaried", you don't get overtime. > Perhaps you mean "legal". But employers of salaried people have quite a bit > of leeway in this area. The current law makes salaried people not get paid overtime. If you don't think that is fair, you need to convince voters to elect people that will change the laws. Now, back to FPGAs... -- Phil HaysArticle: 62742
Hi,
I have the following problem:
library ieee;
use ieee.std_logic_1164.all;
entity test is
port(ep_to_send : in std_logic_vector(3 downto 0);
addr_to_send : in std_logic_vector(6 downto 0);
data_valid_to_send : in std_logic;
direction_to_send : in std_logic
);
end test;
architecture rtl of test is
signal test_vector: std_logic_vector(9 downto 0);
begin
test_vector <= (addr_to_send(4 downto 0) & ep_to_send &
data_valid_to_send);
end rtl;
Is this legal in VHDL? Will the new vector be composed correctly?
Thanks
Andres Vazquez
Article: 62743dgleeson-2@utvinternet.com (Denis Gleeson) wrote in message news:<184c35f9.0311060253.19553d1f@posting.google.com>... Hi, You do have multiple drivers to Store_Trigger_Acquisition_Count. One source is Out_acquisition_count and the other is the bit from Store_Trigger_Acquisition_Count you are trying to shift. You need a mux for each bit of register. I hope it helps. > Hello all > > I am trying to implement the following logic in a xilinx XCS05xl > FPGA. > > I have a 15 bit binary counter. I need to store its count value > on the occurrence of an event. Some time later I need to shift the stored > counter value out of the FPGA in a serial fashion under the control > of a clock. > > What I currently have is: > ----------------------------------------------------------------------- > input clear; > reg clear; > > input ACB_Decade_Count_Enable; > > input ACB_Read_Trigger_Address_Clk; > > output ACB_Trigger_Address_Output; > reg ACB_Trigger_Address_Output; > > reg [14:0] Store_Trigger_Acquisition_Count; // Storage for counter count. > > > // Store the count value when ACB_Decade_Count_Enable is high. > always @ (ACB_Decade_Count_Enable) > begin > if(ACB_Decade_Count_Enable) // event happened input is high. > Store_Trigger_Acquisition_Count <= OUT_Acquisition_Count; > end > > // Now shift out the stored count serially. > always @ (posedge clear or posedge ACB_Read_Trigger_Address_Clk) > begin > if(clear) > begin > ACB_Trigger_Address_Output <=0; > end > else > begin > ACB_Trigger_Address_Output <=Store_Trigger_Acquisition_Count[14]; > Store_Trigger_Acquisition_Count <= Store_Trigger_Acquisition_Count << 1; > end > end > > ----------------------------------------------------------------------- > > With this code my synthesis step gives the following errors. > > Warning - Latch inferred in design "My block" read with > 'hdlin_check_no_latch'(HDL - 307) > > Error - The net /../my block/Store_Trigger_Acquisition_Count<13> has more > than one driver(FPGA-CHECK-5) > > The last error is repeated for all bits in Store_Trigger_Acquisition_Count. > > > The logic above seems correct in my head but Im not an FPGA expert. > Obviously I need a different implementation. Any suggestions. > > > Many thanks for all suggestions in advance. > > DenisArticle: 62744
> Hi, > > I have the following problem: > > > > library ieee; > use ieee.std_logic_1164.all; > > entity test is > port(ep_to_send : in std_logic_vector(3 downto 0); > addr_to_send : in std_logic_vector(6 downto 0); > data_valid_to_send : in std_logic; > direction_to_send : in std_logic > ); > end test; > > architecture rtl of test is > signal test_vector: std_logic_vector(9 downto 0); > > begin > test_vector <= (addr_to_send(4 downto 0) & ep_to_send & > data_valid_to_send); > > end rtl; > > Is this legal in VHDL? Will the new vector be composed correctly? > > Thanks > > Andres Vazquez Yep, perfectly legal code. Just be sure that the size on the left and right are equal. And you don't need the parenthesisses. I just prefer to use those things as less as possible. Your code will do the following: test_vector(9) <= addr_to_send(4); test_vector(8) <= addr_to_send(3); test_vector(7) <= addr_to_send(2); test_vector(6) <= addr_to_send(1); test_vector(5) <= addr_to_send(0); test_vector(4) <= ep_to_send(3); test_vector(3) <= ep_to_send(2); test_vector(2) <= ep_to_send(1); test_vector(1) <= ep_to_send(0); test_vector(0) <= data_valid_to_send; If you would revers the range of test_vector you will do this: test_vector(0) <= addr_to_send(4); test_vector(1) <= addr_to_send(3); test_vector(2) <= addr_to_send(2); .... kind regards, JanArticle: 62745
I'm doing some stunts using DLL's in a VirtexE to make different clockspeeds. I create a clock mux using BUFT's and different clocksources wich is then fed into a last DLL and then into a global clock buffer. (This is meant to be a separate clock domain with a few exceptions, and I dont care about phase relations between the domains) I also specify a FROM:TO between the domains at a very large number (50us), cause the few signals going between the domains are not time critical, and resynced to the correct domain. (this is done properly by asynchronous set and synchronous clear and edge detector in the new domain) The FROM:TO statement specifies a kind of "timing ignore" between all the domains used by the mux. I have problems getting the timing analyzer to analyze this correctly. I specify a new PERIOD on the signal out of the BUFG after the mux, but the analyzer ignores this and uses the large number (supposedly the FROM:TO has priority over the PERIOD attribute) even if both source and destination of the FF is in the same domain! I have also tried the MAXDELAY and TIG attribute in between where the PERIOD attribute may cross the domains, but it still doesnt analyse this clock domain from the correct PERIOD constraint but uses the FROM:TO. Somehow it seems difficult to really CUT the timing in a path. The TIG attribute does not work as expected. Any ideas? ThanksArticle: 62746
Morten, With the FROM:TO constraints I have always found them applying to things that I did not want them to. To really get the constraint "correct" (so that it didn't want to apply it to something else), I had to use FROM:THROUGH:TO (specify the path in question). After mucking about with this for a long time, and failing to get a reasonable result, I just pulled the constraints, and used the period constraint all alone. The multicycle through paths now did not meet timing (failed), but at least I could go and manually check each one, and "sign off" that these paths were OK none the less. The area was also massively affected by the FROM:THOUGH:TO constraints, with very poor timing results (worse than the period constraint alone) resulting on the paths that I really cared about and larger area..... I suppose that if I had a single clock things would have worked better, but with multiple clock domains, resynchonization circuits, and the rest of the stuff, the FROM:TO constraints just seemed to be causing me nothing but headaches (as the synthesizer just seemed to want to apply relaxed constraints to too many paths). Austin Morten Leikvoll wrote: > I'm doing some stunts using DLL's in a VirtexE to make different > clockspeeds. I create a clock mux using BUFT's and different > clocksources wich is then fed into a last DLL and then into a > global clock buffer. (This is meant to be a separate clock domain > with a few exceptions, and I dont care about phase relations > between the domains) > > I also specify a FROM:TO between the domains at a very large number > (50us), cause the few signals going between the domains are not time > critical, and resynced to the correct domain. (this is done properly by > asynchronous set and synchronous clear and edge detector in the new > domain) The FROM:TO statement specifies a kind of "timing ignore" > between all the domains used by the mux. > > I have problems getting the timing analyzer to analyze this correctly. I > specify a new PERIOD on the signal out of the BUFG after the mux, but the > analyzer ignores this and uses the large number (supposedly the > FROM:TO has priority over the PERIOD attribute) even if both source > and destination of the FF is in the same domain! > > I have also tried the MAXDELAY and TIG attribute in between where the > PERIOD attribute may cross the domains, but it still doesnt analyse this > clock domain from the correct PERIOD constraint but uses the FROM:TO. > > Somehow it seems difficult to really CUT the timing in a path. The TIG > attribute does not work as expected. > > Any ideas? > ThanksArticle: 62747
Hi You consider there SRAM-based FPGAs (Xilnx, Altera..) which need external components to be programmed. There are others technologies like anti-fuse or Flash-based FPGA. These FPGAs don't need any others components and so one can't read your bitstream. Actel is a manufacturor of flash-based FPGA, if you really need security, have a look at their FPGAs. Arnaud. "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu> a écrit dans le message de news:7cXnb.58247$Tr4.129994@attbi_s03... > > "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message > news:J8Vnb.151$t45.14067905@newssvr21.news.prodigy.com... > > "Markus Zingg" wrote: > > > > While reading diverse articles about fpga's I got the impression that > > > they have to be programmed out of a prom or through a microprocessor > > > etc. However, this means that it would be very easy to "catch" this > > > code in a finished design and abuse it to clone/copy such a design. > > > One take on this is the actual value of a bitstream and how someone > > would/could use it in a commercial application and potential reproduction > of > > your project. I've put a lot of thought into this and decided that, at > > least for the type of work I'm doing, it's not an issue. Why? Because, > by > > the nature of the designs, if someone were to copy the bitstream with > intent > > to clone the design (presumably for commercial gain) they'd also have to > > design their board exactly as mine. There isn't a court in the world that > > wouldn't favor the original designer when shown that evidence. > > My belief is that for most devices, in most markets, with reasonable markups > this is true. > > Consider the toy/video game market. (I don't know if any use FPGA, but they > could.) The markup is generally very low, using the razor model and making > most of the money off selling the games (software). In that case, someone > will have a hard time pricing it low enough (assuming one uses cheap foreign > labor, as the cloners would). Also, the profitable lifetime is short. > > Consider the high end scientific/engineering equipment market. The number > of devices built will be low, and they might be sold with a high markup (to > cover design cost, for example). Usually, though, support is an important > part of the purchase, and buyers of clone devices wouldn't get any support. > There is also the embarassment of being caught with an illegal device, > especially in a public company. > > If your market is primarily in places that have strong copyright laws, that > is a big part of your protection. If a large part of the market is in > places with weak copyright laws, then you have to consider other > alternatives. > > -- glen > >Article: 62748
The problem is that you have assigned signal Store_Trigger_Acquisition_Count
in two processes.
One possible solution is the following ;
always @ (ACB_Decade_Count_Enable or OUT_Acquisition_Count)
begin
if(ACB_Decade_Count_Enable) // event happened input is high.
Store_Trigger_Acquisition_Count <= OUT_Acquisition_Count;
end
always @ (posedge clear or posedge ACB_Read_Trigger_Address_Clk )
begin
if(clear)
out_count <= 4'b1110;
else
out_count <= out_count - 1;
end
assign ACB_Trigger_Address_Output =
Store_Trigger_Acquisition_Count[out_count];
This solution creates a latch for Store_Trigger_Acquisition_Count and then
uses an internal down counter to mux the Output under control of the clock.
"Denis Gleeson" <dgleeson-2@utvinternet.com> wrote in message
news:184c35f9.0311060253.19553d1f@posting.google.com...
> Hello all
>
> I am trying to implement the following logic in a xilinx XCS05xl
> FPGA.
>
> I have a 15 bit binary counter. I need to store its count value
> on the occurrence of an event. Some time later I need to shift the stored
> counter value out of the FPGA in a serial fashion under the control
> of a clock.
>
> What I currently have is:
> -----------------------------------------------------------------------
> input clear;
> reg clear;
>
> input ACB_Decade_Count_Enable;
>
> input ACB_Read_Trigger_Address_Clk;
>
> output ACB_Trigger_Address_Output;
> reg ACB_Trigger_Address_Output;
>
> reg [14:0] Store_Trigger_Acquisition_Count; // Storage for counter count.
>
>
> // Store the count value when ACB_Decade_Count_Enable is high.
> always @ (ACB_Decade_Count_Enable)
> begin
> if(ACB_Decade_Count_Enable) // event happened input is high.
> Store_Trigger_Acquisition_Count <= OUT_Acquisition_Count;
> end
>
> // Now shift out the stored count serially.
> always @ (posedge clear or posedge ACB_Read_Trigger_Address_Clk)
> begin
> if(clear)
> begin
> ACB_Trigger_Address_Output <=0;
> end
> else
> begin
> ACB_Trigger_Address_Output <=Store_Trigger_Acquisition_Count[14];
> Store_Trigger_Acquisition_Count <= Store_Trigger_Acquisition_Count << 1;
> end
> end
>
> -----------------------------------------------------------------------
>
> With this code my synthesis step gives the following errors.
>
> Warning - Latch inferred in design "My block" read with
> 'hdlin_check_no_latch'(HDL - 307)
>
> Error - The net /../my block/Store_Trigger_Acquisition_Count<13> has
more
> than one driver(FPGA-CHECK-5)
>
> The last error is repeated for all bits in
Store_Trigger_Acquisition_Count.
>
>
> The logic above seems correct in my head but Im not an FPGA expert.
> Obviously I need a different implementation. Any suggestions.
>
>
> Many thanks for all suggestions in advance.
>
> Denis
Article: 62749Austin Lesea wrote: > After mucking about with this for a long time, and failing to get a > reasonable result, I just pulled the constraints, and used the period > constraint all alone. The multicycle through paths now did not meet timing > (failed), but at least I could go and manually check each one, and "sign off" > that these paths were OK none the less. I also like a single period constraint for staic timing. Some static timers are smart about synchronization and some aren't. Sometimes you have to check paths or break the design in two for timing and assume the synchronizer will just work. -- Mike Treseler
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