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Neil Glenn Jacobson wrote: > > iMPACT (all versions, full or WebPACK install) has > supported and does support download via Parallel > Cable III (in fact, I have one on my desk > and it works just fine) as well as configuration > of legacy devices. Err, not the version embedded in Project Navigator. It scans all the ports (USB, LPT1:n, COM1:n) looking for a compatible cable. This takes quite a while. Then it stops and asks the user to define the cable. Click "Parallel" and "lpt1" and it says there's nothing there. We think we're not unique in having this problem: <http://groups.google.com/groups?selm=%25Qjv7.59250%24y7.681072%40dbsch1.home.nl>. We did try the various fixes suggested by <http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=15742> - so far without success. What we've gone with for the time being is Webpack iMPACT running stand-alone. -- Tim Forcer tmf@ecs.soton.ac.uk The University of Southampton, UK The University is not responsible for my opinionsArticle: 63426
Tim Forcer wrote: > Neil Glenn Jacobson wrote: >> >> iMPACT (all versions, full or WebPACK install) has >> supported and does support download via Parallel >> Cable III (in fact, I have one on my desk >> and it works just fine) as well as configuration >> of legacy devices. > > Err, not the version embedded in Project Navigator. It scans > all the ports (USB, LPT1:n, COM1:n) looking for a compatible > cable. This takes quite a while. Then it stops and asks the > user to define the cable. Click "Parallel" and "lpt1" and it > says there's nothing there. > > We think we're not unique in having this problem: > <http://groups.google.com/groups?selm=%25Qjv7.59250%24y7.681072%40dbsch1.hom e.nl>. > > We did try the various fixes suggested by > <http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID =1&getPagePath=15742> > - so far without success. What we've gone with for the time > being is Webpack iMPACT running stand-alone. In my experience, Parallel Cable III only works with the port in SPP (old fashioned unidirectional) mode, not EPP or ECP mode. Karl OlsenArticle: 63427
Sergey Yemets wrote: > Hi. > I have found "CAPTURE SITE" viewing Virtex die in FPGA editor. > (down-left corner of die). > The site has two inputs only (clk,cap). > I think that the "CAPTURE" belongs to JTAG functionality, but I am not > sure. > I can't find any record of the unit (at Xilinx site). > Does somebody know the goal of this unit? > (I've find explanation about similar units "RPCILOGIC,LPCILOGIC" in > the group only). Have a look at this: http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0081_65.html#wp1000931 -- Sean Durkin Fraunhofer Institute for Integrated Circuits (IIS) Am Wolfsmantel 33, 91058 Erlangen, Germany mailto:23@iis.42.de ([23 , 42] <=> [durkinsn , fraunhofer])Article: 63428
Tim Forcer wrote: > Peter Alfke top-posted: >> >> Tim, you have to get over the idea of still >> getting something from your old chip investment. >> Xilinx FPGAs have become 100 times (!) cheaper, >> have added functionality and better software >> support since the days when you bought the >> XC4013s. > > It's not the chip investment that's the *big* hangup, but the > equipment investment. The chips were chosen deliberately in > pin-grid-array package so we could replace as and when we wanted > - including when/if they got blown up by misuse. Throw-away ICs > we can live with - even at the price of PGA 4013s. Throw-away > experimental units is another ball game. I suspect your best compromise may be to select the latest and greatest - in Xilinx' case, this is currently Spartan-3 - and have a tiny daughter board built with FPGA, regulator and protection/interface chips. Of course you would still have to address the issue of updating all the course material, as Jonathan discussed a month or so ago. And you would have to repeat the exercise every five years or so.Article: 63429
>> BTW: Why do you restrict FIFO depths to powers of two? That would allow >> trading memory usage versus implementation speed (like with altsyncram). > Probably because FIFO storage is based on a ram, > and ram comes in increments of one address bit. True as long as the size of the memory/FIFO is smaller than the memory blocks available in the device. A Cyclone for example uses M4K memory blocks with 4096bit each (as the name suggests). So for RAM/FIFOs <4096bit you will always pay with a full M4K (as long as tey are implemented in memory blocks), but for RAM/FIFOs >4096bits the M4K-block is the smallest building unit, allowing you to implement a RAM/FIFO using 3*4096=12288bits from 3 M4K-blocks (depending on the FIFO width). Because address decoding is easier when aligning by depth an to improve speed, it can make sense to use more (four in our example) M4K-blocks wasting some memory, but it is by no ways a necessity. This is a limitation which does not apply to RAM but only to FIFOs and will be introduced in Quartus 4.0 as Subroto said. However RAM and FIFOs are both implemented in the very same memory blocks so it's up to the Wizard/Module Designer to allow or restrict the depth. It is a choice to restrict FIFO depths to powers of two but as long as there is no special FIFO-RAM block no must. My question was why this limitation which restricts potential savings on memory bit consumption will be introduced. Regards, ManfredArticle: 63430
hi rick, i am sorry for asking these type of trivial questions, let me be the first person to answer. Difference between verification and validation Validation and verification refer to the process of satisfying the requirement, but the difference lies in the level of testing. Verification refer to lower level of test, like testing of module, interface etc. Verification tests are conducted by the developer. Whereas validation occurs at the final stage prior to the acceptance of a product for release. Validation tests are normally conducted by a party that is independent of the developer (Quality Assurance or the test group) Emulation The process by which a device is built to work like another. For example, a chip can be designed to emulate another model. The emulator can be hardware, software or both with regards pradeep.g rickman <spamgoeshere4@yahoo.com> wrote in message news:<3FBDA0A6.BF7DDCA3@yahoo.com>... > pradeep wrote: > > > > Hi, > > > > can any one give the difference between verification and validation ? > > > Will I get credit for doing your assignments? > > > what is system level validation ? > > > What is homework? > > > what is emulation ? > > Why can't you read your text book? > > > I don't normally answer posts that appear to be students asking for help > with homework (or more correctly asking others to do the work for > them). But this is just too obvious. > > How about you read your book and write a couple of paragraphs on each of > the above questions for us to critique? Wouldn't that be more useful to > you? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 63431
I have a problem I hope someone here can give an answer to: I'm working on my first project for a Xilinx Virtex II Pro FPGA, and I'm having some problems with simulation results I get when simulating on the "post place and route" VHDL model. Actually the strange behavioir (which I suppose isn't strange at all, if I only knew how things worked) appears in all simulations other then when I simulate on the behavioural model. The "strange behaviour" I'm refering to, is that no matter what I do, I cannot get anything (other than 0) on my output untill a sertain time has passed by. To simulate, I start Modelsim from Xilinx Project navigator. Now I have made a test-project, only containing a 8 bit register between the input and output pins, and I'm still experiencing this behaviour. I've made a ASCII-drawing of the sim-result that can be found at the bottom of my post. My question is: Is there a certain time that the FPGA need to complete internal resets and such, that is actually reflected in the simulation for all other simulations than on the behavioural model? If so, where in the spec is this specified? What is it called, etc. Sincerely -Fred, Norway. ASCII-figure: Remember to view it in a monospace font: +-----------------------------------------+ | Post PAR simulation | +-----------------------------------------+ | Problem: Nothing but 0 on my outputs | | until the 6th clk period. | +-----------------------------------------+ | | |0 ns 100 ns | || 20 ns |110 ns | || | | | | | _ _ _ _ _ _ _ _ _ _ | |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| | | | __ __ __ __ | |_____________________/A \/B \/C \/D \____| | \__/\__/\__/\__/ | | __ __ __ __ | |______________________/A \/B \/C \/D \___| | \__/\__/\__/\__/ | | | | __ __ __ __ | |_________________/A \/B \/C \/D \________| | \__/\__/\__/\__/ | | __ __ __ | |______________________/B \/C \/D \_______| | \__/\__/\__/ | | | | __ __ __ __ | |_____________/A \/B \/C \/D \____________| | \__/\__/\__/\__/ | | __ __ | |______________________/C \/D \___________| | \__/\__/ | | | | __ __ __ __ | |_________/A \/B \/C \/D \________________| | \__/\__/\__/\__/ | | __ | |______________________/D \_______________| | \__/ | | | +-----------------------------------------+ | FPGA: Virtex II Pro (xc2vp30-5fg676) | | Sim: Modelsim XE II 5.7c | +-----------------------------------------+Article: 63432
Hi Peter, Yes. I too clear with this. I have one question regarding clock skew. As you said, In FPGA we can't control over the clock skew since it is being routed via dedicated lines. When i am looking in to the timing reports, Some times i am getting the Clock Skew value as 0.102ns.. ie., in Positive And some times, -0.123 ie., in Negative. Actually, what it means.??? How the timing report tells the clock skew? How it is being measured? Regards, Muthu Peter Alfke <peter@xilinx.com> wrote in message news:<3FBCF4AD.6D4EE682@xilinx.com>... > Well, Praveen, that's why I used this as an interview question... :-) > Think of a shift register. Min clock period is the sum of clock-to-Q + > routing + set-up time. > Now assume that the downstream flip-flop is clocked earlier than the > upstream one. You have lost that time from your clock period. That's > lower performance! > > Take pencil and paper and draw the timing diagram... > Peter Alfke > ============================ > praveen wrote: > > > > Hi peter, > > > > first of all thanks for your reply . But in your reply one of the > > sentences was not clear here it goes. > > > > "Running the clock against the data flow sacrifices performance by > > increasing the set-up time". > > > > what was not clear to me was you say that it sacrifices perfomance. > > Could you please elaborate on what parameters it is based. > > > > rgds, > > praveen > > > > > > Peter Alfke <peter@xilinx.com> wrote in message news:<3FBBA6A5.D509B341@xilinx.com>... > > > praveen wrote: > > > > > > > i have no of D flip flops cascaded now there are two ways clock can be routed. > > > > > > > > 1) in the direction of the data flow. > > > > 2) opposite to the direction of the data flow. > > > > > > > > which of the above is good?? > > > > > > Good question, Praveen. Since 1988, every young engineer that I > > > interviewed for employment here at Xilinx ( i.e. a couple of hundred) > > > had to come up with an answer to that question. > > > > > > If you have a choice ( in an FPGA you should use global clocks, so you > > > have no measurable delay difference anyhow) there is a trade-off: > > > > > > Running the clock against the data flow sacrifices performance by > > > increasing the set-up time, but it is the safeest method, and therefore recommended. > > > > > > Running the clock in the direction of the data flow reduces set-up time > > > and thus alllows a higher clock rate, but changes the input requirements > > > in the direction of a positive (or more positive) hold time. If > > > overdone, this can create a race condition, and "failure at any clock > > > speed". > > > Therefore not recommended. > > > > > > Peter Alfke, Xilinx ApplicationsArticle: 63433
I forgot to name my signals, so here is a new ASCII-figure: +-----------------------------------------+ | Post PAR simulation | +-----------------------------------------+ | Problem: Nothing but 0 on my outputs | | until the 6th clk period. | +-----------------------------------------+ | | |0 ns 100 ns | || 20 ns |110 ns | || | | | | | _ _ _ _ _ _ _ _ _ _ | |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| | | |IN_1 __ __ __ __ | |_____________________/A \/B \/C \/D \____| | \__/\__/\__/\__/ | |OUT_1 __ __ __ __ | |______________________/A \/B \/C \/D \___| | \__/\__/\__/\__/ | | | |IN_2 __ __ __ __ | |_________________/A \/B \/C \/D \________| | \__/\__/\__/\__/ | |OUT_2 __ __ __ | |______________________/B \/C \/D \_______| | \__/\__/\__/ | | | |IN_3 __ __ __ __ | |_____________/A \/B \/C \/D \____________| | \__/\__/\__/\__/ | |Out_3 __ __ | |______________________/C \/D \___________| | \__/\__/ | | | |IN_4 __ __ __ __ | |_________/A \/B \/C \/D \________________| | \__/\__/\__/\__/ | |OUT_4 __ | |______________________/D \_______________| | \__/ | | | +-----------------------------------------+ | FPGA: Virtex II Pro (xc2vp30-5fg676) | | Sim: Modelsim XE II 5.7c | +-----------------------------------------+Article: 63434
Crap. This was supposed to be a follow up on my other thread. Sorry for the inconvenience... -Fred P.S. If anyone has a good news-client to recommend, please do :pArticle: 63435
pradeep wrote:
> hi rick,
>
> i am sorry for asking these type of trivial questions,
>
> let me be the first person to answer.
>
> Difference between verification and validation
>
> Validation and verification refer to the process of satisfying the
> requirement, but the difference lies in the level of testing.
>
> Verification refer to lower level of test, like testing of module,
> interface etc. Verification tests are conducted by the developer.
>
> Whereas validation occurs at the final stage prior to the acceptance
> of a product for release. Validation tests are normally conducted by a
> party that is independent of the developer (Quality Assurance or the
> test group)
Looking at the definition of those two words, you could just as easily
reverse the wording of the last two paragraphs and you would be equally
correct.
The company I work for has a group called DVT (design verification and
test). They are the high level testers... the final stage prior to
product release. I'll bet others in the group have similar "final test"
groups that use the word validation rather than verification.
In my opinion, the words have close enough meanings that confusion would
result if an organization tried to use them, by themselves, to mean two
different things.
Have fun,
Marc
Article: 63436"Tim" <tim@rockylogic.com.nooospam.com> wrote in message news:bpl8qr$mai$1$8300dec7@news.demon.co.uk... > I suspect your best compromise may be to select the latest > and greatest - in Xilinx' case, this is currently Spartan-3 > - and have a tiny daughter board built with FPGA, regulator > and protection/interface chips. I reckon this is a seriously good idea. It also allows you (for future projects, of course!) to build a base-board with all the human-scale I/O on it - big lights, switches and connectors - using very low-tech, cheap PCB technology, while still tapping in to as exotic an FPGA technology as you wish, at modest cost. Finally, if you are careful about how you partition the programming/download stuff between base-board and FPGA carrier, you could make the base-board compatible with many different types of FPGA/CPLD. This could be pretty powerful stuff for teaching/project tools. > Of course you would still have to address the issue of > updating all the course material, as Jonathan discussed > a month or so ago. Yes, but you could keep *lots* of commonality this way. > And you would have to repeat the exercise every five years > or so. I guess so. But you could hide quite a lot of the change from your "customers" (students, users) by carefully "parameterising" the course materials so that specific devices don't get mentioned too often! -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 63437
hi,
is there some known bug around using generics in FPGA Compiler II ?
I tried this simple code (package, component and its instance see
bellow),
FPGA Compiler II v3.7 gives this error message:
> HDL-353:
> Error: Can't find type information (.typ file) for type
> ANALOGMASTER.PKG_ANAOGMASTER.WORD_A_I
What does this mean ?
thanks,
Marek
Proposed code:
---------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
PACKAGE pkg_pokus IS
-- ADDRESS WORD length
constant ADDR_WORD_LENGTH : natural range 1 to 16 := 10;
-- type of the ADDRESS WORD
subtype ADDR_WORD is std_logic_vector(ADDR_WORD_LENGTH-1 downto 0);
-- type of the ADDR_integer
subtype WORD_A_i is natural range 0 to 2**ADDR_WORD_LENGTH;
-- Some constant
constant PROG_REG_ADDR : WORD_A_i :=
to_integer(to_unsigned(16#3ff#,ADDR_WORD_LENGTH));
END pkg_pokus;
------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY AnalogMaster;
USE AnalogMaster.Pkg_pokus.all;
ENTITY ADDR_DEC IS
GENERIC(
reg_addr : WORD_A_i := 0
);
PORT(
addr : IN ADDR_WORD;
cs_n : OUT std_logic
);
END ADDR_DEC ;
ARCHITECTURE addr_dec OF ADDR_DEC IS
BEGIN
process(ADDR)
begin
if ADDR =
std_logic_vector(to_unsigned(REG_ADDR,ADDR_WORD_LENGTH)) then
CS_N <= '0';
else
CS_N <= '1';
end if;
end process;
END addr_dec;
-------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY AnalogMaster;
USE AnalogMaster.Pkg_pokus.all;
ENTITY pokus IS
PORT(
addr : IN ADDR_WORD;
cs_n : OUT std_logic
);
END pokus ;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY AnalogMaster;
USE AnalogMaster.Pkg_pokus.all;
ARCHITECTURE struct OF pokus IS
COMPONENT ADDR_DEC
GENERIC (reg_addr : WORD_A_i := 0);
PORT (
addr : IN ADDR_WORD ;
cs_n : OUT std_logic
);
END COMPONENT;
BEGIN
-- Instance port mappings.
I0 : ADDR_DEC
GENERIC MAP (
reg_addr => 22
)
PORT MAP (
addr => addr,
cs_n => cs_n
);
END struct;
--
Dipl.-Ing. Marek Ponca
Institut of Circuit Technology and Electronics
Faculty of Electrical Engineering and Information Technology
Ilmenau Technical University
P.O. BOX 10 05 65
98684 Ilmenau, Germany
Tel: +49 3677 69 1167 fax:(1163)
http://www.inf-technik.tu-ilmenau.de/~marek/
marek.ponca@tu-ilmenau.de
Article: 63438Ulf Samuelsson wrote: > > If you want to get some real speed, then maybe something like the Atmel > TS8308500 (500 Mspl/s), TS8388B (1 Gspl/s) or TS83102G0B (Gspl/s) could be > of interest. > Going up to Giga Samples per second, would make your problem worse though > :-) > > http://www.atmel.com/dyn/products/datasheets.asp?family_id=611 > When did Atmel start making flash ADCs? Can someone actually buy these now? How much do they cost? see: http://dustbunny.physics.indiana.edu/~paul/hallDrd for our "merely" 250 Msps particle physics project. Paul Smith Indiana University PhysicsArticle: 63439
Ken wrote:
> the Synplify logfile indicates no replication/pruning has taken place
> but I still see Synplify reporting a broken chain in the worst path report.
Can you post the offending fragment of code showing the adder and
input operands, and the broken chain report message that results?
some other suggestions:
- drop your synthesis target clock to 1 MHz and see if the
broken chain problem goes away
- put the offending adder in its' own module with the
leave-my-module-hierarchy-alone attribute set
( you can then stick an area constraint on that module to force
it to stay in one column, but if the chain's already broken
that won't help too much )
- do the HDL-Analyst RTL/primitive views of the offending adder
show something odd splitting it apart near that bit?
Brian
Article: 63440"Paul Smith" <ptsmith@no_spam.indiana.edu> wrote in message news:bpleh0$fdm$1@hood.uits.indiana.edu... > Ulf Samuelsson wrote: > > > > > If you want to get some real speed, then maybe something like the Atmel > > TS8308500 (500 Mspl/s), TS8388B (1 Gspl/s) or TS83102G0B (2 Gspl/s) could be > > of interest. > > Going up to Giga Samples per second, would make your problem worse though > > :-) > > > > http://www.atmel.com/dyn/products/datasheets.asp?family_id=611 > > > > When did Atmel start making flash ADCs? Can someone actually buy these > now? How much do they cost? Yep, have been around for quite some time. > see: > > http://dustbunny.physics.indiana.edu/~paul/hallDrd > > for our "merely" 250 Msps particle physics project. My guess is maybe $500 for the 1 G sample 8 bit devices. 2-3 x the price for the 2 G sample 10 bit device. This is for commercial spec, mil spec devices are more expensive. How many do you need? -- Best Regards Ulf at atmel dot com These comments are intended to be my own opinion and they may, or may not be shared by my employer, Atmel Sweden. > > Paul Smith > Indiana University Physics >Article: 63441
Khim, What area (Country/State) are you located in? Dan "Khim Bittle" <khimbittle@cliftonREMOVEsystems.com> wrote in message news:3fbbacbb.13085309@news.compuserve.com... > > If your schedule is such that you won't go into production for 6 > months you may want to contact Altera about MAX 2 , the next > generation of product that will be available mid 2004. This just > provides the option of staying with the same toolset for a much lower > power device ... but they aren't 5V tolerant. I also have a power > issue with the current MAX parts but since the other logic parts on my > boards are Altera I really prefer to keep one development tool for the > board and thus will wait for MAX 2 for the power reduction. > > Lattice also makes some great parts with good power characteristics > .. I used to be a loyal Lattice guy until my local FAE quit and > support stopped ... but no more. > > > On Wed, 19 Nov 2003 16:55:49 GMT, Al Clark <dsp@danvillesignal.com> > wrote: > > >We have been using Max EPM3032 and EPM3064 devices for several of our > >designs. > > > >The features I like with these devices is as follows: > > > >1. Very Cheap - $1.30 for 3032 devices in small quantities > >2. Easy tools with 74 style schematic capture entry. > >3. 3.3V operation with 5V tolerant I/O > > > >The MAX 3000 is also a power hog which is the main reason I am searching > >for alternatives. > > > >I looked at the Xilinx CoolRunner and CoolRunner 2 parts. Here were my > >impressions based from their web site. I would appreciate comments. > > > >CoolRunner: > > > >1. Although they have these parts on their web site, they seem to be > >deemphasised. This suggested to me that maybe this line is on the way > >out. > > > >2. I like the 3.3V supply with the 5V tolerance. > > > >3. Power is lower than Altera, prices are higher. > > > >CoolRunner 2: > > > >1. Xilinx wants to sell these parts. > >2. They use 1.8V supplies which is just about the only supply I don't > >already need in my design. > >3. They are not 5V tolerant which may or may not be important (but often > >is) > >4. They cost more than Altera Max 3000 or CoolRunner. > > > >Are the tools as easy as Altera? What's a good In-Circuit-Programmer? > >Are there gotchas? > > > >What other players or parts should I consider? > > > >1. I want schematic entry, reasonably small size in QFP, low power and > >low cost. > > > > > >-- > >Al Clark > >Danville Signal Processing, Inc. > >-------------------------------------------------------------------- > >Purveyors of Fine DSP Hardware and other Cool Stuff > >Available at http://www.danvillesignal.com >Article: 63442
Hi there, Is there any way I can implement submodules, each with their own constraint files (detailing pin locations etc) in to a top level module? Ideally I don't want to connect through all the signals through the top level module. Why do I want to do this? - Because I am trying to make use of some modules already written for a particular Xilinx development board (Microblaze and multimedia XC2V2000). For example, there is a Clock generator module (CLOCKGEN.V and CLOCKGEN.UCF). The constraint file contains the pin locations of input clocks etc. In my top level module, I want to ignore these connections, and just use the output of "CLOCKGEN.V". Does anyone know how I might do this? Should I use a black-box instantiation? (and if so... how? without having to specify the inputs to "CLOCKGEN.V" that I want to know nothing about in the top-level module?) (I am using Verilog). With best regards PETER MASHArticle: 63443
www.acqiris.comArticle: 63444
Have you considered other vendors? Lattice makes several devices that will go beyond 512 Macrocells. Also, their 5kve and XPLD family have 68-inputs into the macrocell blocks which should make fitting easier. Dan "Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:bpkjqf$7ug$1@news.tu-darmstadt.de... > Klaus Falser <kfalser@ihatespamdurst.it> wrote: > : Hello, > > : I have a rather large design for a XC95288XL which consumes 276 macrocells > : of 288 possible. > : Since Xilinx seems to prefer Coolrunner devices to the good old XC9500's > : I tried to stuff the design into a Coolrunner II chip to look how it > : would behave. > > Did you play with the fitter options? > > : However, I was not able to make it fit even in a 512 macrocell device. > : Timing should not be so tight, it has to run at 8 MHz clock, but the > : timing analyzer gives me 17-18 MHz on the slowest 10 ns device. > > The Macrocell of the XC2 is not as wide as the cell of the XC95X(V), so some > logic may need expansion on two cells. > > : Can anybody which know's the XCR2 better than me give me a hit where > : to pay attention? > : How can I see from the report where the fitter has a problem? > > Did you look look at the *.rpt files? > > Bye > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > ======================================================= > > Free software means: Contribute nothing, expect nothing > > =======================================================Article: 63445
I think that you should check out the QL5030 from QuickLogic. The device has a fixed PCI target interface with a OTP programmable FPGA fabric. There is no fee for the PCI core and full featured PCI testbench is provided for simulation. The advantage of this is it would provide you with a single part solution for you PCI and the rest of your logic. "David Collier" <from_usenet_comp_arch_fpga@dexdyne.com> wrote in message news:memo.20031118172109.1108B@DavidC.zen.co.uk... > I need to build a PCI interface - could be 64 bytes of write-only latches > and 1 byte of status readback. > > Then I want to implement the rest of my logic, not to complex, in a PLD. > > I'd LIKE it all to be in one device, but I don't want to spend any time > debugging PCI implementations. > > Anyone got any recommendations for where to go get my IP? > > DavidArticle: 63446
Tim Forcer wrote: > Neil Glenn Jacobson wrote: > >>iMPACT (all versions, full or WebPACK install) has >>supported and does support download via Parallel >>Cable III (in fact, I have one on my desk >>and it works just fine) as well as configuration >>of legacy devices. > > > Err, not the version embedded in Project Navigator. It scans > all the ports (USB, LPT1:n, COM1:n) looking for a compatible > cable. This takes quite a while. Then it stops and asks the > user to define the cable. Click "Parallel" and "lpt1" and it > says there's nothing there. There are several issues worthy of note: (1) You may have "old" Xilinx parallel port drivers installed on your system that should be removed. With the release of 5.1i, a new version of the parallel port drivers was included. There is no backward compatibility between iMPACT pre-5.1i and post-5.1i http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=16494 (2) You are using a "clone" of Parallel Cable III not the "real deal". We have seen situations in which the clones are not quite clones and fail for a variety of PC-related reasons. (3) You may need to set your BIOS to use the Bidirectional (rather than ECP or EPP) mode for the parallel port. > > We think we're not unique in having this problem: > <http://groups.google.com/groups?selm=%25Qjv7.59250%24y7.681072%40dbsch1.home.nl>. > > We did try the various fixes suggested by > <http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=15742> > - so far without success. What we've gone with for the time > being is Webpack iMPACT running stand-alone. >Article: 63447
Hi! > I guess this is a ray-tracing problem... But I need to do this task in as > high as possible speed/throughput. Here is my problem: > > Suppose I am given 25 rays and I am given a 3D cube and all parameters of > these rays and cube are given... > > I need to compute the length of the intersecting segment of the rays with > this cube as fast as possible. If some rays completely fall outside of the > cube, then it outputs 0, otherwise gives the length. - Are the vertices of the cube parallel to the coordinate axles? - Is the anything special about the cube (size, orientation, rotation, location, etc.)? - In what format are the rays and the cube defined? > I heard there are some very good graphic card with accelerator... and I > heard about the bus bandwidth to be as high as 500MHz... I am not sure if > they have good accelaration function for doing my task? Possibly no. First, you would have to get data *back* from the accelerator which is something they are not designed for. As someone said to me once, they operate in a 'write and forget' mode. Second, none of the accelerators I know of do ray-tracing. However your question is not a complete ray-trace problem, so you might be able to tweak the functions of an accelerator to give you your answer. > I also think of doing this using an FPGA which is hooked onto a Intel PC > with Linux... I don't know the details, but I guess it uses PCI or other bus > to interact with the CPU and serve as an coprocessor... That's a possiblity. You can find PCI FPGA prototyping cards for this purpose. BTW, if you need to process 1GB of data (assume that's the total amount of traffic) you would need at least at least 7.75 seconds just to transfer the data over a 33MHz PCI bus, not counting other PCI traffic, and other issues. If that's too slow, you would need a) 66MHz b) 64bit c) PIX-X bus and of course a PC that supports these. > I want to know which method is better? Depends on many things: - Speed requirement (as fast as possible is not enough) - Numerical Precision - Price concerns - Project deadlines - More precise description of the problem (see above) > Considering that after solving this throughput problem, the next bottleneck > will be a 1GB memory that I need... I wonder if the graphic card has 1GB > cache/memory inside it? None I've heard of. > Since a lot time it needs to do triple-buffling, I > guess... it should have a high speed huge memory, right? Huge means 128-256MB nowadays. > I also don't know what is the maximum processing speed of a high-end > graphical card comparing with a high end FPGA implementation? Impossible to answer in general. > Can anybody give me some comments/suggestions/advice/hints/pointers on this? What I would suggest is to write a SW only solution for your problem. That would give you, or anyone else a pretty good definition of the problem. After this, you probably will be able to state much better questions. Regards, Andras TantosArticle: 63448
"Alex Gibson" <alxx/*nospam*/@@/*nospam*/ihug./*nospam*/com./remove/au> wrote in message news:<bphg4m$dlu$1@lust.ihug.co.nz>... > "Mike Silva" <snarflemike@yahoo.com> wrote in message > news:20619edc.0311171148.4b9d44f5@posting.google.com... > > This Digilent combo package looks to me like an excellent way to learn > > FPGAs (but then, I don't know anything yet!): > > > > http://www.digilentinc.com/Catalog/digilab 2 dio2.html > > > > Do more experienced eyes see any gotchas with this setup? I realize > > the FPGA is bigger than a beginner needs, but the price seems good, > > and I gather the part is from a mainstream FPGA family. > > > > Thanks. > > I got myself a similar combo but with the dio1 > and a couple of the breadboards > http://www.digilentinc.com/Catalog/digilab io1.html > http://www.digilentinc.com/Catalog/digilab breadboard wire-wrap.html > the lack of memory is a bit annoying sometimes > > Have you had a look at http://www.burched.biz/ > http://www.burched.biz/b5xsvp.html Well, there's clear consensus that I'll be wanting RAM! I did look at the burched.biz stuff, but the 2.5X price put me off. Seems like it should be easy enough to cobble up some RAM on one of the digilent proto boards, yes?Article: 63449
andres.vazquez@gmx.de (Vazquez) wrote in message news:<eee19a7a.0311200628.263b82c9@posting.google.com>... > Dear Sir or Madame, > > attached you see a test project file. > > After compiling the design I open the Node Finder. > I use the following filter : Design entry (all names) > > Why is the signal "vector_out" (entity test.vhd) > (which is concurrently assigned by the registered signal > "l_vector") and the corresponding port map signal (toplevel entity) > "l_vector_out" shown to be combinatorial although they are > registers? > A change of the filter type does not change the result. > > Why do these signals not appear as registers in the NodeFinder? > > Thank you very much. > > Kind regards > > A. Vazquez > > toplevel file > ------------------------------------------------------ > ------------------------------------------------------ > > library ieee; > > use ieee.std_logic_1164.all; > use ieee.std_logic_arith.all; > > entity test_hierarch is > port( clk_in : in std_logic; > reset_in : in std_logic; > invec : in std_logic_vector(3 downto 0); > set : in std_logic_vector(3 downto 0); > show : out std_logic > ); > end test_hierarch; > > > architecture rtl of test_hierarch is > > component test is > port( clk : in std_logic; > reset : in std_logic; > indelay : in std_logic_vector(3 downto 0); > vector_out : out std_logic_vector(3 downto 0) > ); > end component; > > -- local signals > signal l_vector_out : std_logic_vector(3 downto 0); > > begin > > i1 : test > port map ( clk => clk_in, > reset => reset_in, > indelay => invec, > vector_out => l_vector_out > ); > > process(reset_in, clk_in) > begin > if reset_in='1' then > show <= '0'; > elsif clk_in='1' and clk_in'event then > if ( (l_vector_out = "0001") and (set="1111") ) then > show <= '1'; > end if; > end if; > end process; > end rtl; > ---------------------------------------------------- > ---------------------------------------------------- > > > > component file > ----------------------------------------------------- > ----------------------------------------------------- > library ieee; > use ieee.std_logic_1164.all; > use ieee.std_logic_arith.all; > > > entity test is > port( clk : in std_logic; > reset : in std_logic; > indelay : in std_logic_vector(3 downto 0); > vector_out : out std_logic_vector(3 downto 0) > ); > end test; > > architecture behavior of test is > > signal l_vector : std_logic_vector(3 downto 0); > > begin > > -- concurrent statement > vector_out <= l_vector; > -- > > process(clk, reset) > begin > if reset='1' then > l_vector <= (others => '0'); > > elsif clk='1' and clk'event then > l_vector <= indelay; > end if; > end process; > > end behavior; > > ----------------------------------------------- > ----------------------------------------------- "vector_out" and "l_vector_out" are wires that are connected to the register "l_vector". Quartus considers wires to be combinational entities, even if they are electrically connected to the output of a register. Subroto Datta Altera Corp.
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