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Messages from 63350

Article: 63350
Subject: Re: Anyone use HDL as design tool for PCBs?
From: "Matt" <bielstein2002@comcast.net>
Date: Thu, 20 Nov 2003 04:11:12 GMT
Links: << >>  << T >>  << A >>
> Matt, it is true that they are useful for system level simulation. But
> the way of the development is IMO just the opposite: _first_ you do a
> simulation, also on system level, _after this_ you design your chips and

Janos --  agreed on the system simulation up front.


> board. For the system level simulation you need a HDL entity, like
> ¨Board¨ that connects the HDL Units representing the chips. You can do
> this by the Testbench unit, but IMO it is a better approach to separate
> the testbench and board functions. And you are there: you have a ¨Board¨

Agreement here as well. However I am not talking about Board = Testbench.
Let me clarify. :-) "Board" is what I am talking about. Here testbench
instantiates the "board" which instantiates "chips", resistors, capacitors,
connectors etc. The tools generate "Board" from either a schematic capture
tool or more importantly, the PCB tools. The reason I would prefer PCB tools
is that if there are problems in the layout these could be detected in the
simulation. All of this is automated to reduce human error. The things that
you can catch are those things that DRC normally doesn't catch like
incorrectly wired connectors and components.

> HDL that contains all inter-chip connections, it would be perfect to use
> this for PCB Netlist generation.
>

I am talking about the opposite approach. PCB netlist is used to generate
"Board".

-- Matt






Article: 63351
Subject: Re: 400 Mb/s ADC
From: "MM" <mbmsv@yahoo.com>
Date: Thu, 20 Nov 2003 00:06:40 -0500
Links: << >>  << T >>  << A >>
> yes, repacking might allow a 64/66 PCI to accept the data. i worry
> that we will spend lots of time and money, but the margin will be
> insufficient for it to actually work.  i have heard that some PCI
> cores are not too efficient.

Spend money and time on what? With regards to PCI, I am pretty sure it will
work. You can ask PCI crowd on the PCI mailing list
(http://www.pcisig.com/developers/technical_support/pci_forum), they will
tell you for sure.And it doesn't have to be a core, you could use an
industry proven silicon, e.g. from PLX. I would be more worried about
processing all this data in your PC. I don't think any PC can do FFT's while
keeping up with such a data flow. Let's say you want to do 1024 point FFT.
At  400 MSPS it will take only 2.56 us to accumulate a new block of data.
The latest and greatest ADI ADSP-TS201S can do a 1024-point complex FFT time
in 16.8 microseconds. I doubt any of the Intel chips can do it faster.
AFAIK, TI DSP's aren't faster either. So, in my opinion you will either need
an array of fast DSP's or some sort of FPGA based processing. Trying to do
this kind of processing in host doesn't sound feasible to me.


/Mikhail



Article: 63352
Subject: Re: Acek 1K - Quartus II - timing issues
From: vbetz@altera.com (Vaughn Betz)
Date: 19 Nov 2003 21:12:32 -0800
Links: << >>  << T >>  << A >>
Hi Manfred,

Here are a few things you can try to meet timing:

1. Turn off "optimize i/o cell register placement for timing".  That
option enables some aggressive optimizations for registered IO timing.
 These optimizations can hurt internal clock frequencies (fmax).  If
you are meeting your IO (Tsu & Tco) timing, but missing a clock timing
constraint, turning this option off may help.

2.  Changing the fitter seed can let you search for a better fit. 
Usually things only improve a few % if you search over several seeds,
but on some designs the gains can be larger.

3.  You can automatically search for a better fit with the Design
Space Explorer (DSE) script that ships with Quartus.  It will
automatically sweep the fitter seed for you, and turn on some hidden
try-harder options for placement, and save the best fit.  For newer
familes like Stratix & Cyclone, it will also experiment with different
forms of physical synthesis and register packing, but those
optimizations are not available for the ACEX 1K family.

To use DSE type:

quartus_sh -t [quartus_install_dir]/bin/tcl_scripts/dse.tcl

It pops up a simple, self-explanatory GUI.

4.  It sounds like you are using Quartus for synthesis.  Make sure you
have "default logic synthesis style" = speed selected (this is the
default).  It's under Settings->Default Logic Options.

5.  Make sure you've set all your timing constraints.

6.  Send us the design, and we can check if there is some poor
optimization going on in either synthesis or the fitter.

Hope this helps.

Vaughn
Altera


rickman <spamgoeshere4@yahoo.com> wrote in message news:<3FBB0854.A9C37455@yahoo.com>...
> If you are going to play with the seed, you need to try several settings
> before you can say it won't work.  
> 
> I once worked on a real b--ch of a design and my coworker set up a
> script that would run multiple passes overnight.  That was the only way
> we ever got the thing working.  he also had to write AWK scripts to
> parse the timing results since this was MaxPlus2 and the thing pretty
> well sucked for timing analysis.  I believe Quartus is much better now. 
> But it left a bad taste in my mouth for Altera software.  I'll get over
> it some day...
> 
> 
> Kumaran wrote:
> > 
> > Hi Manfred,
> > Thanks for your response. I am using the dedicated clock pin 79. I had
> > a look at other threads for optimizing the speed. Some one mentioned
> > that by increasing the seed in the fitter setting might increase the
> > speed, but, they also mentioned that there will only be a slight
> > improvement, and I saw a slight increase in the speed(not good
> > enough). Any other suggestions? Thanks for your time.
> > 
> > Thanks,
> > Kumaran
> > 
> > "Manfred Balik" <e8825130@stud4.tuwien.ac.at> wrote in message news:<3fb9d94f$0$18702$3b214f66@tunews.univie.ac.at>...
> > > It looks like you didn't use the internal Clock-Network.
> > > Use the dedicated Clock Pins 79 or 183 (and maybe the internal PLL) to have
> > > the same delays of clock signal to each gate.
> > > Manfred
> > >
> > >
> > > "Kumaran" <kumaran@trlabs.ca> schrieb im Newsbeitrag
> > > news:40f2d3e9.0311171247.ab73d04@posting.google.com...
> > > > Hi all,
> > > > I am targeting my design on Acex EP1K100QC208-3 FPGA. I did most of my
> > > > development using Leonardo Spectrum synthesizer(2002) and Max +2. My
> > > > license for leonardo expired, and I decided to use Quartus II(v3.0).
> > > > When I compile using Quartus, Iam getting a negative slack time for
> > > > one of my clock. when I compiled the same FPGA code using LS and Max
> > > > +2, I did not have any timing issues . In the compiler settings, I
> > > > have enabled the "optimize i/o cell register placement for timing"
> > > > option. I also tried different synthesis tool in quartus (FPGA
> > > > express, LS,..) but I could not get the timing right. Can anyone help
> > > > me?
> > > >
> > > > Thanks,
> > > >
> > > > Kumaran
>  
> --

Article: 63353
Subject: Re: 400 Mb/s ADC
From: Larry Doolittle <ldoolitt@recycle.lbl.gov>
Date: Thu, 20 Nov 2003 05:29:37 +0000 (UTC)
Links: << >>  << T >>  << A >>
Jeff Peterson wrote:
> "Nik Simpson" <n_simpson@bellsouth.net> wrote in message news:<vQPub.41$zi3.40@bignews3.bellsouth.net>...
>> > we accumualte averages (of cross products of fourier tranforms)
>> 
>> So the basic problem is getting 400MB/s of data into memory and processing
>> it, but are you reading 400MB every second, or sampling say once every ten
>> seconds. If it's every second, then you've got a bigger problem because I'd
>> be surprised if you can process it fast enough to get the job done before
>> the next sample comes along.
> we will take about 64K samples, then can pause while processing...
> however all the time we are pausing we are losing data.  so we do want to
> keep the duty cycle up.  50% dudty cyle is not a problem. 5% would be.

As stated elsethread, if you give up trying to get this throughput
on a conventional PC platform, you probably can do this on a "big enough"
FPGA.  From your memory needs alone (64K x 6 x some overhead in which
to do your FFT) you're probably looking north of an XC2V2000, and the
single chip price is measured in the thousands of US$.  For the c.a.f
group to estimate with any precision the smallest practical part, you
need to do things like compute the number of bits precision you need
for your butterflies.  The 96 18x18 multipliers on an XC2V3000 would
come in real handy, especially if they didn't need to be cascaded for
more precision.  If you can make your design work at 200 MS/s (DDR),
Even 32 multipliers would let you run the FFT as fast as data points
stream in -- although that would also require 16 x 64K x 18 bits
storage, out of reach for the current Xilinx offerings at least.

I know who I'd ask first for help (ahem-ray-cough).

        - Larry

Article: 63354
Subject: Re: regarding clock routing
From: praveen@cg-coreel.com (praveen)
Date: 19 Nov 2003 22:40:12 -0800
Links: << >>  << T >>  << A >>
Hi peter,
 
first of all thanks for your reply . But in your reply one of the
sentences was not clear here it goes.
 
"Running the clock against the data flow sacrifices performance by
 increasing the set-up time".
 
what was not clear to me was you say that it sacrifices perfomance.
Could you please elaborate on what parameters it is based.
 
rgds,
praveen
 

Peter Alfke <peter@xilinx.com> wrote in message news:<3FBBA6A5.D509B341@xilinx.com>...
> praveen wrote:
> 
> > i have no of  D flip flops cascaded now there are two ways clock can be routed.
> > 
> > 1) in the direction of the data flow.
> > 2) opposite to the direction of the data flow.
> > 
> > which of the above is good??
> 
> Good question, Praveen. Since 1988, every young engineer that I
> interviewed for employment here at Xilinx ( i.e. a couple of hundred)
> had to come up with an answer to that question.
> 
> If you have a choice ( in an FPGA you should use global clocks, so you
> have no measurable delay difference anyhow) there is a trade-off:
> 
> Running the clock against the data flow sacrifices performance by
> increasing the set-up time, but it is the safeest method, and therefore recommended.
> 
> Running the clock in the direction of the data flow reduces set-up time
> and thus alllows a higher clock rate, but changes the input requirements
> in the direction of a positive (or more positive) hold time. If
> overdone, this can create a race condition, and "failure at any clock
> speed". 
> Therefore not recommended.
> 
> Peter Alfke, Xilinx Applications

Article: 63355
Subject: Re: State Machines....
From: hmurray@suespammers.org (Hal Murray)
Date: Thu, 20 Nov 2003 07:23:42 -0000
Links: << >>  << T >>  << A >>
>I am not asking for the Nobel prize. I just wonder whether this is a
>practical, compact, cheap, fast and easy way to build a state machine
>inside an FPGA...

I think it's a great idea.  But I'm probably biased because I
learned hardware back in the days when people built that sort
of state machine out of real ROMs and various gates and I think
writing that type of firmware is fun.

(Registered ROMs were a big advance - they saved a whole chip.)

I think the main advantage of this approach is that it changes
a hardware problem (state machine) into a software problem
(microcode).  At some level of complexity (number of states
or instructions) it just seems easier to think about the
problem as software.

Your idea would probably get used a lot more if there was
an example all worked out.  In particular, you need an assembler
so that other people can use it as a skeleton.  And as others
have mentioned, you need an example that shows how the microcode
gets through the tool chain and merged into the FPGA bit stream.

What's a good toy example?  Can we think of something semi-useful
(toy) that would run on a demo board?  It would need 50-100 states.
I might be willing to hack together some software if somebody would
do the rest of the work.

Has anybody considered using LUT sized ROMs for state machines?
It doesn't seem likely to be practical but might make an interesing
exercise.  The classic traffic light controller or vending machine
might fit.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 63356
Subject: Re: Altera's altsyncram MAXIMUM_DEPTH
From: =?iso-8859-15?Q?Manfred_M=FCcke?= <manfred.getmuecke@ridgmxof.thisat>
Date: Thu, 20 Nov 2003 08:29:36 +0100
Links: << >>  << T >>  << A >>
Hi Subroto,

> The FIFO megafunctions do not support non-power-of-2 depths, so the 
> memory example I gave does not apply.

This is a very clean answer to a very long service request issue, it would 
have saved me a lot of time getting the very same answer from Altera 
mySupport. Instead they left me with a dangling service request and the 
information that there is a potential bug in Quartus. Do you have the 
possibility to look into that, or to share your knowledge with your support 
team? I would appreciate getting an official answer from mySuport, really 
closing my service request.
BTW: Why do you restrict FIFO depths to powers of two? That would allow 
trading memory usage versus implementation speed (like with altsyncram).

Regards, Manfred

Article: 63357
Subject: Re: Xilinx microblaze : SRAM external mem controller
From: "Erik Hansen" <nospam-comp-arch-fpga@erik-hansen.de>
Date: Thu, 20 Nov 2003 09:49:16 +0100
Links: << >>  << T >>  << A >>
Hi Richard,
> I am working with xilinx microblaze and I am trying to set up my
microblaze to communicate with a 128 KB asynchronous SRAM chip (IS63LV1024).
> So far I'e been able to set up the opb_emc (External Memory Controller) to
communicate with the SRAM chip. However, I can only write to the
> SRAM in 4 bytes rds. I cannot write byte by byte. Example:
> If I try to write to byte 0x0F10_0001, the whole word at 0x0F10_0000 gets
updated instead.

There are two possiblilites

Software:
---------
So how do you write to memory?
In C you should be aware to declare your pointer according to the data width
you want to write.

int  *my_memory_pointer = 0x0f100001;
*my_memory_pointer = 0x31;
will set the whole word.

char *my_memory_pointer =  0x0f100001;
*my_memory_pointer = 0x31;
will write only one byte

Hardware:
----------
How is your memory connected?  Are you shure your byte - enable signals an
not
tied together?

---
In order to check whether your hardware or your software is the
reason for your problem try writing to memory using xmd.
Do not start any software on your microblaze.
Start xmd.
Connect to the microblaze.
Use the mwr command.
Example:

c:> xmd                                      -> this starts xmd
xmd> mbconnect (stub/mdm)      -> connects you to your microblaze, in case
you do not now
                                                  -> how this works check
the mb docmentation
xmd> mrd 0x0f100000              -> read address 0x0f100000 (the whole word)
[...]                                            -> there should be the
content of your memory
xmd> mwr 0x0f100001 0x31 b -> writes _b_ytewise to memrory
xmd> mrd 0x0f100000              -> read address 0x0f100000
[...]                                            -> did it succeed? when
not, your hw might be wrong
                                                  -> otherwise you have to
change your programm

Erik



Article: 63358
Subject: Re: 400 Mb/s ADC
From: news@sulimma.de (Kolja Sulimma)
Date: 20 Nov 2003 00:57:33 -0800
Links: << >>  << T >>  << A >>
jbp@cmu.edu (Jeff Peterson) wrote in message news:<369b6e8b.0311190715.4d66f38f@posting.google.com>...
> We are building a new radio telescope called PAST
> (http://astrophysics.phys.cmu.edu/~jbp/past6.pdf)
> which we will install at the South Pole or in Western China.
> 
> To make this work, will need to sample (6 to 8 bit precision) dozens
> of analog voltages at 400 Msample/sec and feed these data streams into
> PCs. One PC per sampler.
> 
> The flash ADCs we need are available (Maxim), but we are finding it
> difficult to get the data into the PC.

You should definitely talk to High Energy Physics People. Like the
STAR experiment at BNL or ALICE at CERN. Talk to the data aquisition
and Level 3 Trigger people there. You probably can just buy boards
with fast links and DSPs from them.

If you want to design it yourself, here are some comments:
1)
If you use a busmaster device you and you want to read data with 50%
duty cycle you can buffer the events in your readout board and reduce
the data rate to 200MByte/s. You add one event of latency.

2)
The fastest slots on a PC Mainboard are the memory expansion slots.
It's an easy to design hardware interface and if you use a server
mainboard with multiple memory channels you get a hell lot of
bandwidth. I remember seeing a cryptoaccelerator on a DIMM somewhere
and SUN used to place graphics boards in memory slots.

3.
If your political environment is similar to high energy physics, than
if you can reduce the duty cycle it does not really matter how
expensive the readout boards are. With a large FPGA on a PCI board you
can try to perform all computations on the board and achieve a 100%
duty cycle.

Kolja Sulimma

Article: 63359
Subject: Re: 400 Mb/s ADC
From: "Maxim S. Shatskih" <maxim@storagecraft.com>
Date: Thu, 20 Nov 2003 12:07:53 +0300
Links: << >>  << T >>  << A >>
> The fastest slots on a PC Mainboard are the memory expansion slots.
> It's an easy to design hardware interface and if you use a server
> mainboard with multiple memory channels you get a hell lot of
> bandwidth.

...and forget Windows support. Only the specially hacked Linux will be your
friend.

> and SUN used to place graphics boards in memory slots.

Sorry? Sun used S-Bus for them, which is not memory slot.

--
Maxim Shatskih, Windows DDK MVP
StorageCraft Corporation
maxim@storagecraft.com
http://www.storagecraft.com



Article: 63360
Subject: Re: State Machines....
From: "Ulf Samuelsson" <ulf@NOSPAMatmel.com>
Date: Thu, 20 Nov 2003 10:21:37 +0100
Links: << >>  << T >>  << A >>
If you have an FPGA with lots of RAM, doing it in microcode is surely
feasable.

256 states
3 possible next states for each state (8 additional bits per "possible new
state").
100 outputs (will have 4 additional bits so 104 outputs is OK)

256 * (104 + (3 * 8)) = 256 * 128 = 32768 bits or 4 KB.

If there is not extremely high clock frequencies, you can build the state
machine
using deeper SRAMs.

  512 * 64 @ 2 clocks per state machine update
1024 * 32 @ 4 clocks per state machine update
2048 * 16 @ 8 clocks per state machine update
4096 *   8 @16 clocks per state machine update

The update will read the SRAM to a shadow register, one slice at the time
and will update the outputs simultaneously during the last clock.
The next state is determined from the inputs which will select
one of the three possible "next" states (S1,S2,S3) by controlling a 3->1
multiplexer.
The output of the multiplexer can be written to the "state" register.
If you want to stay in the same state, then you do not write to the state
register.

You can reduce the number of inputs you react to by having additional output
bits in the RAM which controls input multiplexers.
You need to figure out the maximum number of inputs any state will react to
and create that many input multiplexers.

The outputs of those muxes, and the "current" state
can then be used as an address a second 4 bit SRAM.
The output is used to select the next state (Keep,S1,S2,S3).

Lots of SRAM and very little Logic.
Would work with an 5 k gate FPSLIC...


-- 
Best Regards
Ulf at atmel dot com
These comments are intended to be my own opinion and they
may, or may not be shared by my employer, Atmel Sweden.

"Peter Alfke" <peter@xilinx.com> wrote in message
news:3FBBFCC8.E3A34A0D@xilinx.com...
> I am not asking for the Nobel prize. I just wonder whether this is a
> practical, compact, cheap, fast and easy way to build a state machine
> inside an FPGA...
> Peter Alfke
> =============================
> rickman wrote:
> >
> > Using RAM/ROM for a FSM is about as basic as it gets.  I remember using
> > that method some 20 years ago about the same time fuse PLDs were
> > starting to appear.  Back then fuse ROMs were just about this same
> > size.
> >
> > Peter Alfke wrote:
> > >
> > > There is an April 2001 TechXclusives "Using leftover multipliers and
> > > BlockRAMs" that describes a surprisingly simple structure for a state
> > > machine with up to 256 states. I never got any feedback on this idea.
> > > There is no software tool, but it's pretty straightforward, and
"pencil
> > > and paper" might suffice...
> > > http://support.xilinx.com/xlnx/xweb/xil_tx_home.jsp
> > >
> > > Peter Alfke, Xilinx Applications
> > > =============================
> > > Robert Sefton wrote:
> > > >
> > > > Stan -
> > > >
> > > > I agree with Jonathan that 200 states is nuts. Very error prone and
> > > > probably very difficult to maintain/modify. Were you parsing the
> > > > incoming data stream and making state decisions based on that? If
so, a
> > > > programmable communications processor or an embedded processor (like
> > > > Nios for Altera) is a much better and more flexible choice. Some
tasks
> > > > just aren't meant to be done in hardware, and parsing data streams
is
> > > > one of them.
> > > >
> > > > Nice reward for delivering a working design. I hope you find a way
to
> > > > exit that situation.
> > > >
> > > > Robert
> > > >
> > > > "stan" <stanandsue2000@yahooREMOVE.com> wrote in message
> > > > news:3fbb8795.3574357@news.compuserve.com...
> > > > > hi ... I have a question for the experts , I am doing a post
mortem of
> > > > > my last project , it was a communication processor that was
basicly a
> > > > > lot of dataflow paths controlled by several rather complex state
> > > > > machines ( 100-200 states ) ,  I did the design by thinking out
the
> > > > > control and drawing the state diagrams and then coding them into
VHDL
> > > > > for Quartus and into a Stratix .. it worked , after handing over
the
> > > > > design to the test department they loaded a board and signed off
on
> > > > > the design within a week. My fellow engineers were rather
impressed
> > > > > since they knew how complex the control was.
> > > > >
> > > > > The downside here was the state machines became complex and took
quite
> > > > > a while to figure out ... then transcibing them into VHDL and also
> > > > > drawing a pretty state chart for documenting the design took a
while.
> > > > > Yes I know some say start right with typing VHDL but I find that
hard
> > > > > to comceptualize.  Since this is a small company big $$ tools are
out
> > > > > of the question.
> > > > >
> > > > > So my question ... are there tools out there that can make this
> > > > > process faster ?  like drawing the state charts on the screen and
> > > > > outputing VHDL ?  or other suggestions ???  again if these are
$5-10K
> > > > > tools I won't be getting them in this company so shareware or <$1K
> > > > > tools are preferred even if they lack in some areas.
> > > > >
> > > > > The bigger downside here is that since the state machines took
longer
> > > > > than I expected ( I scheduled 3 weeks of design, project took 6
weeks
> > > > > )  my manager has warned me to find another job ( fat chance ) as
he
> > > > > has handed in a review requesting a 20% pay cut ... but my real
> > > > > question is about the tools so I may do better next time
> > > > >
> > > > > thanks for any constructive feedback , stan
> >
> > --
> >
> > Rick "rickman" Collins
> >
> > rick.collins@XYarius.com
> > Ignore the reply address. To email me use the above address with the XY
> > removed.
> >
> > Arius - A Signal Processing Solutions Company
> > Specializing in DSP and FPGA design      URL http://www.arius.com
> > 4 King Ave                               301-682-7772 Voice
> > Frederick, MD 21701-3110                 301-682-7666 FAX



Article: 63361
Subject: Virtex Benchmarks
From: panjuhwa_fpga@yahoo.com (PanJuHwa)
Date: 20 Nov 2003 01:37:33 -0800
Links: << >>  << T >>  << A >>
Hi,

  I'm currently working on an honours thesis involving configuration
compression for Virtex FPGAs. I need to collect benchmarks in my
analysis of the algorithms that I've implemented, for any Virtex
devices, preferably with utilization > 70%. If you do not mind
providing any bitstreams you have at hand for my research, please
reply to this post or send them to me at panjuhwa_fpga@yahoo.com. Many
thanks!

Regards,
Ju Hwa

Article: 63362
Subject: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
From: "Ken" <aeu96186_MENOWANTSPAM@yahoo.co.uk>
Date: Thu, 20 Nov 2003 10:07:51 -0000
Links: << >>  << T >>  << A >>

> Ken,
>     Have you read the constraints guide in the Xilinx software manuals?
Look
> for the RLOC section. You end up with stuff in your UCF like :-
>
> INST "*un6_burp_cry_0" RLOC = "X6Y4";
> INST "*un6_burp_cry_1" RLOC = "X6Y4";
> INST "*un6_burp_cry_2" RLOC = "X6Y5";
> INST "*un6_burp_cry_3" RLOC = "X6Y5";
> INST "*un6_burp_cry_4" RLOC = "X6Y8";
> etc...
>
>     I used the floorplanner to get the names of things I want to RLOC. For
> your problem, you could place the carry chain with floorplanner and send
the
> output to a temporary UCF to give you a start on your RLOC stuff. Hope
that
> makes sense! Read about H_SETs, HU_SETs and U_SETs too.
>         good luck, Syms.


Syms,

Thanks for the reply,

I am familiar with the Xilinx contraints guide but I would like to put the
constraint in the VHDL rather than the ucf and I do not want to make it
Xilinx specific.

An adder is such a simple thing and the device has specific wires to
implement it quickly - surely there must be a way to inform the tools to use
the carry chain in one column only for max speed?

Cheers,

Ken



Article: 63363
Subject: Re: Memory Initialization: mif, coe, hex, etc,
From: Tero Rissa <no_spam_for_me@thanks.invalid>
Date: Thu, 20 Nov 2003 11:25:56 +0000 (UTC)
Links: << >>  << T >>  << A >>
Josh Pfrimmer <yeah_spam_me@thisaddress.com> wrote:

> In the interest of fully exploring the issue, though (though I may very
> well take your suggestion) How do people cope with the problem below, when
> CoreGen _is_ used?

For similar situation, I had a script that translates assembly instructions
directly to .coe and .mif files and edits the ram initialization in the .edf. 
In the case of a single block ram, the edit of .edf is quite trivial. If 
you need more than one block, the words will be distributed between the 
rams, which complicates the script a bit, but is also quite doable.

On the other hand, regenerating the .edf is just one click in CoreGen.

-- 
T.Rissa
tpr at doc ic ac uk


Article: 63364
Subject: avoiding GCLK
From: Mastupristi <cialdi_NO_SP@AM_firenze.net>
Date: Thu, 20 Nov 2003 13:36:39 +0100
Links: << >>  << T >>  << A >>
I use Xilinx ise web pack 6.1 sp 2.

In my project I have a signal that is used as clock in only one flip
flop.
I have a constrain that place this signal on a generic iob.

in the map process I obtain the following error:
Using target part "2s50eft256-6".
ERROR:MapLib:93 - Illegal LOC on IPAD symbol "din<0>" or BUFGP symbol
   "din_0_BUFGP" (output signal=din_0_BUFGP), IPAD-IBUFG should only be
   LOCed to GCLKIOB site.

How can I force this signal to be placed in a non-GCLK pin?

thanks

-- 
Mastupristi?

Posted from X-Privat Free NNTP server - www.x-privat.org

Article: 63365
Subject: Altera Max 7000 cpld's
From: Wing Fong Wong <skyings@dbzmail.com>
Date: Thu, 20 Nov 2003 12:45:25 +0000 (UTC)
Links: << >>  << T >>  << A >>
Does anyone know where I can get Altera Max 7000s series cplds in 
Australia and maybe some prototyping boards as well?

-- 
Wing Wong.
Webpage: http://wing.ucc.asn.au


Article: 63366
Subject: Xilinx Microblaze SDRAM burst access
From: dziegelmeier@de.pepperl-fuchs.com (Dirk Ziegelmeier)
Date: 20 Nov 2003 05:42:46 -0800
Links: << >>  << T >>  << A >>
Hello Group,

I'm currently evaluating a Xilinx Microblaze system. One of the
must-have features is a fast memcopy. Therefore, I implemented a basic
system consisting of a Microblaze core (no caches, but program runs in
BlockRAM) and a SDRAM controller. Burst support of the SDRAM core is
enabled. Burst support of the microblaze core should work
out-of-the-box according to the manuals.
The system consists of:
- Microblaze 2.0 core
- OPB bus v20
- OPB SDRAM controller

Memcopy delivers unsatisfactory performance, an analysis shows that
the main reason is that the SDRAM controller does not perform burst
accesses to the RAM. The memcopy routine is quite optimal, it consists
of four consecutive read and four write instructions, so bursting
should work in theory.

Is there anything more I need to do to get bursts to work? I already
spent two days reading manuals and FAQs trying to identify the
problem, but no success.

TIA,
Dirk

Article: 63367
Subject: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
From: Marc Randolph <mrand@my-deja.com>
Date: Thu, 20 Nov 2003 14:11:53 GMT
Links: << >>  << T >>  << A >>
Ken wrote:
>
> I am familiar with the Xilinx contraints guide but I would like to put the
> constraint in the VHDL rather than the ucf and I do not want to make it
> Xilinx specific.

If you are using RLOC's, aren't you making it Xilinx specific?

Not only that, are RLOC's guaranteed to even be the same from one Xilinx 
family to another Xilinx family?

> An adder is such a simple thing and the device has specific wires to
> implement it quickly - surely there must be a way to inform the tools to use
> the carry chain in one column only for max speed?

I'm sure you've already thought of this, but can you not break the adder 
up?

Good luck,

    Marc


Article: 63368
Subject: Quartus II Node Finder
From: andres.vazquez@gmx.de (Vazquez)
Date: 20 Nov 2003 06:28:05 -0800
Links: << >>  << T >>  << A >>
Dear Sir or Madame,

attached you see a test project file.

After compiling the design I open the Node Finder.
I use the following filter : Design entry (all names)

Why is the signal "vector_out" (entity test.vhd)
(which is  concurrently assigned by the registered signal
"l_vector")   and the corresponding port map signal (toplevel entity)
"l_vector_out" shown to be combinatorial although they are
registers?
A change of the filter type does not change the result.

Why do these signals not appear as registers in the NodeFinder?

Thank you very much.

Kind regards

A. Vazquez

toplevel file
------------------------------------------------------
------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity test_hierarch is
port( clk_in   : in  std_logic;
      reset_in : in  std_logic;
      invec    : in  std_logic_vector(3 downto 0);
      set      : in  std_logic_vector(3 downto 0);
      show     : out std_logic
    );
end test_hierarch;


architecture rtl of test_hierarch is

   component test is
             port( clk        : in  std_logic;
                   reset      : in  std_logic;
                   indelay    : in  std_logic_vector(3 downto 0);
                   vector_out : out std_logic_vector(3 downto 0)
                  );
   end component;

-- local signals
signal l_vector_out : std_logic_vector(3 downto 0);

begin

i1 : test
port map ( clk        => clk_in,
           reset      => reset_in,
           indelay    => invec,
           vector_out => l_vector_out
          );

 process(reset_in, clk_in)
 begin
    if reset_in='1' then
       show <= '0';
    elsif clk_in='1' and clk_in'event then
       if ( (l_vector_out = "0001") and (set="1111") ) then
          show <= '1';
       end if;
    end if;
 end process;
end rtl;
----------------------------------------------------
----------------------------------------------------



component file
-----------------------------------------------------
-----------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;


entity test is
port( clk        : in  std_logic;
      reset      : in  std_logic;
      indelay    : in  std_logic_vector(3 downto 0);
      vector_out : out std_logic_vector(3 downto 0)
    );
end test;

architecture behavior of test is

signal l_vector : std_logic_vector(3 downto 0);

begin

-- concurrent statement
vector_out <= l_vector;
--

 process(clk, reset)
 begin
   if reset='1' then
      l_vector <= (others => '0');

   elsif clk='1' and clk'event then
      l_vector <= indelay;
   end if;
 end process;

end behavior;

-----------------------------------------------
-----------------------------------------------

Article: 63369
Subject: Re: avoiding GCLK
From: Martin Kellermann <martin.kellermann@nospam.xilinx.com>
Date: Thu, 20 Nov 2003 15:45:00 +0100
Links: << >>  << T >>  << A >>
Just instantiate a normal buffer (buf) and route the output of this 
signal to the clock-input of the FF. That'll work.

Martin



Mastupristi wrote:

> I use Xilinx ise web pack 6.1 sp 2.
> 
> In my project I have a signal that is used as clock in only one flip
> flop.
> I have a constrain that place this signal on a generic iob.
> 
> in the map process I obtain the following error:
> Using target part "2s50eft256-6".
> ERROR:MapLib:93 - Illegal LOC on IPAD symbol "din<0>" or BUFGP symbol
>    "din_0_BUFGP" (output signal=din_0_BUFGP), IPAD-IBUFG should only be
>    LOCed to GCLKIOB site.
> 
> How can I force this signal to be placed in a non-GCLK pin?
> 
> thanks
> 
> 


Article: 63370
Subject: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
From: "Ken" <aeu96186_MENOWANTSPAM@yahoo.co.uk>
Date: Thu, 20 Nov 2003 15:03:15 -0000
Links: << >>  << T >>  << A >>
> If you are using RLOC's, aren't you making it Xilinx specific?
>
> Not only that, are RLOC's guaranteed to even be the same from one Xilinx
> family to another Xilinx family?

I would rather not use RLOCs - I just want to inform the tools that using
the carry chain in one column is more important than any fancy optimisations
that save a few slices but cause the fast carry chain to broken.

>
> > An adder is such a simple thing and the device has specific wires to
> > implement it quickly - surely there must be a way to inform the tools to
use
> > the carry chain in one column only for max speed?
>
> I'm sure you've already thought of this, but can you not break the adder
> up?

Quite possibly but that would be a pain in the neck.

I just don't see why this should be difficult.

Cheers,

Ken



Article: 63371
Subject: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
From: "Ken" <aeu96186_MENOWANTSPAM@yahoo.co.uk>
Date: Thu, 20 Nov 2003 15:04:48 -0000
Links: << >>  << T >>  << A >>

Francisco,

Many thanks for your detailed response and the code.

If I go down the road of abandoning trying to get synthesis to accomplish
this then I will certainly be referring to your implementation.

Cheers,

Ken



> > Ken,
> >     Have you read the constraints guide in the Xilinx software manuals?
> Look
> > for the RLOC section. You end up with stuff in your UCF like :-
> >
> > INST "*un6_burp_cry_0" RLOC = "X6Y4";
> > INST "*un6_burp_cry_1" RLOC = "X6Y4";
> > INST "*un6_burp_cry_2" RLOC = "X6Y5";
> > INST "*un6_burp_cry_3" RLOC = "X6Y5";
> > INST "*un6_burp_cry_4" RLOC = "X6Y8";
> > etc...
> >
> >     I used the floorplanner to get the names of things I want to RLOC.
For
> > your problem, you could place the carry chain with floorplanner and send
> the
> > output to a temporary UCF to give you a start on your RLOC stuff. Hope
> that
> > makes sense! Read about H_SETs, HU_SETs and U_SETs too.
> >         good luck, Syms.
> >
>
> I prefer the way used in one of Xilinx's TechXclusives to embed RLOC
> attributes
> directly in VHDL (Relationally Placed Macros). Here's an example of a RPM
to
> perform a registered a + b, using
> the carry chain using the U_SET attribute.
>
>
> -- begin VHDL code
> library ieee;
> use ieee.std_logic_1164.all;
> library unisim;
> use unisim.vcomponents.all;
> use work.rlocs.all;
>
> entity a_plus_b_reg is
>     generic (width: integer := 32; setn: integer := 1);
>  port (
>   clock  : IN  std_logic;
>   enable : IN  std_logic;
>   a :      IN  std_logic_vector (width-1 downto 0);
>   b :      IN  std_logic_vector (width-1 downto 0);
>   q :      OUT std_logic_vector (width-1 downto 0)
>  );
> end a_plus_b_reg;
>
> architecture rpm_arch of a_plus_b_reg is
>
>     attribute INIT:  string;
>     attribute BEL:   string;
>     attribute RLOC:  string;
>     attribute U_SET: string;
>
>     signal prexor_int_q: std_logic_vector (width-1 downto 0);
>     signal int_carry:    std_logic_vector (width-1 downto 0);
>     signal y:            std_logic_vector (width-1 downto 0);
>
> begin
>
>     int_carry(0)  <= '0';
>
>     reg: for i in 0 to width-1 generate
>         attribute U_SET of q_reg: label is "uset" & integer'image(setn);
>         attribute RLOC  of q_reg: label is "X0" & "Y" &
> integer'image(integer(i/2));
>         attribute BEL   of q_reg: label is "FF" & belname_xy(i);
>     begin
>         q_reg: FDE port map (
>                    D => y(i), CE => enable, C => clock,
>                    Q => q(i));
>     end generate;
>
>     gena: for i in 0 to width-2 generate
>         attribute INIT  of q_lut: label is "6";
>         attribute U_SET of q_lut: label is "uset" & integer'image(setn);
>         attribute U_SET of q_mxy: label is "uset" & integer'image(setn);
>         attribute U_SET of q_xor: label is "uset" & integer'image(setn);
>         attribute RLOC  of q_lut: label is "X0" & "Y" &
> integer'image(integer(i/2));
>         attribute RLOC  of q_mxy: label is "X0" & "Y" &
> integer'image(integer(i/2));
>         attribute RLOC  of q_xor: label is "X0" & "Y" &
> integer'image(integer(i/2));
>         attribute BEL   of q_lut: label is belname_fg(i);
>         attribute BEL   of q_xor: label is "XOR" & belname_fg(i);
>     begin
>         q_lut: LUT2
>                --synthesis off
>          generic map (INIT => x"6")
>       --synthesis on
>       port map (
>                    I1 => b(i), I0 => a(i),
>                    O  => prexor_int_q(i) );
>         q_mxy: MUXCY port map (
>                    DI => a(i), CI => int_carry(i), S => prexor_int_q(i),
>                    O  => int_carry(i+1) );
>         q_xor: XORCY port map (
>                    LI => prexor_int_q(i), CI => int_carry(i),
>                    O  => y(i) );
>     end generate;
>
>     genb: for i in width-1 to width-1 generate
>         attribute INIT  of q_lut: label is "6";
>         attribute U_SET of q_lut: label is "uset" & integer'image(setn);
>         attribute U_SET of q_xor: label is "uset" & integer'image(setn);
>         attribute RLOC  of q_lut: label is "X0" & "Y" &
> integer'image(integer(i/2));
>         attribute RLOC  of q_xor: label is "X0" & "Y" &
> integer'image(integer(i/2));
>         attribute BEL   of q_lut: label is belname_fg(i);
>         attribute BEL   of q_xor: label is "XOR" & belname_fg(i);
>     begin
>         q_lut: LUT2
>                    --synthesis off
>                    generic map (INIT => x"6")
>                    --synthesis on
>                    port map (
>                        I1 => b(i), I0 => a(i),
>                        O  => prexor_int_q(i) );
>         q_xor: XORCY port map (
>                    LI => prexor_int_q(i), CI => int_carry(i),
>                    O  => y(i) );
>     end generate;
>
> end rpm_arch;
> -- end VHDL code
>
>
> The resulting RPM is a column of 1 x w/2 slices, being w the value
assigned
> to the width the generic
> The setn generic lets you create different U_SET names for different
> instances of the entity (if the instances
> have no relative positions) or the same U_SET name and applying different
> RLOCs to each instance
> (if the instances have relative positions).
>
> The rlocs package contains a couple of simple functions to return the
> strings "F" or "G"
> or the couple "X" or "Y", to differentiate the luts/ffs inside a single
> slice. Read the constraints guide
> about RLOC, RLOC_ORIGIN and the different kinds of sets you can create.
And
> the RPM techxcluvise,
> of course.
>
> If you prefer the placer to select the absolute positioning of the RPM,
then
> that's all you need.
> If you want total control, then you can select the RPM position attaching
an
> RLOC_ORIGIN
> to the U_SET name in the UCF file.
>
> I've successfully used this entity on the virtex2 architecture & XST.
Don't
> know how to tell
> Synplify Pro to attach those attributes, but it shouldn't be that
difficult.
>
> The drawback is your design is no longer portable. You're stuck with
Xilinx
> parts that use the XY
> coordinate system (not all of them). But you can create different versions
> for different architectures, of course.
>
> Best regards
>
>     Francisco Rodriguez
>
>
>
>
>



Article: 63372
Subject: vhdl construct problem
From: "sudip saha" <>
Date: Thu, 20 Nov 2003 07:06:39 -0800
Links: << >>  << T >>  << A >>
Hi, 
In my vhdl code, on construct is as follows 
case to_integer(addr) is 
when to_integer(fifo1_base + fifo_status )=> 

Where addr is signal of type unsigned(11 downto 0) and fifo1_base and fifo_status is constant of type unsigned(11 downto 0) 

I tried to compile my code in Cadence tool(ncvhdl) and modelsim. In both the cases it said 
for "when" statement 
expecting a locally static statement. 

But surprisingly the code got compiled successfully in quartus. 
Where is the problem while trying to compile with cadence and modelsim? I am using vhdl 93 flag. 



Article: 63373
Subject: Re: 400 Mb/s ADC
From: news@sulimma.de (Kolja Sulimma)
Date: 20 Nov 2003 07:32:58 -0800
Links: << >>  << T >>  << A >>
> > The fastest slots on a PC Mainboard are the memory expansion slots.
> > It's an easy to design hardware interface and if you use a server
> > mainboard with multiple memory channels you get a hell lot of
> > bandwidth.
> 
> ...and forget Windows support. Only the specially hacked Linux will be your
> friend.
????
The need to write their own driver anyway.

I do not know much about windows driver programming, but it should be
possible for a driver developer to map arbitrary physical address
ranges to user space.
You need chipset specific code to enable access to the dimm after
boot, because it must start disabled to prevent windows from using the
memory. But as they use the board only in a single setup, this is no
problem at all.
Anyway, an experiment of that type is likely to use an real time OS
anyway, neither windows nor plain vanilla linux. Maybe OS9 or VxWorks.
 
> Sorry? Sun used S-Bus for them, which is not memory slot.
They did, but they also had UMA archtiectures based on DIMMS.

Kolja Sulimma

Article: 63374
Subject: Re: vhdl construct problem
From: "Jonathan Bromley" <jonathan.bromley@doulos.com>
Date: Thu, 20 Nov 2003 15:50:57 -0000
Links: << >>  << T >>  << A >>
<sudip saha> wrote in
message news:ee81337.-1@WebX.sUN8CHnE...

> case to_integer(addr) is
>   when to_integer(fifo1_base + fifo_status )=>
> Where addr is signal of type unsigned(11 downto 0)
> and fifo1_base and
> fifo_status is constant of type unsigned(11 downto 0)
> I tried to compile my code in Cadence tool(ncvhdl)
> and modelsim. In both the cases it said
>   for "when" statement expecting a locally static statement.
> But surprisingly the code got compiled successfully in quartus.
> Where is the problem while trying to compile with
> cadence and modelsim? I am using vhdl 93 flag.

Quartus is bending the rules here.

Create another constant:

> constant fifo_base_status : integer :=
>      to_integer(fifo1_base + fifo_status );

and use that in your case statement.

(By the way, this is purely a VHDL question and would be
better directed to comp.lang.vhdl)
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223                    mail: jonathan.bromley@doulos.com
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