Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hello, is it possible to start the Xilinx WebPack 6.1 with WINE under Linux (SuSE 9.0)? If I start ise.exe I will get the message, that msvcp60.dll isn't find. Thank you for your answer. bye martin sauerArticle: 63451
Hi, I recently went through the exercise of updating my material from XSE 2.1i to XSE 4.2i. It was a lot of work, I will admit. All of the schematic based projects needed to be converted into Verilog. Plus new hardware (Spartan-IIE). Anyone who is doing the same, or considering doing the same, please feel free to borrow anything that helps you from my class website: http://www.engr.sjsu.edu/crabill Thanks, Eric Tim wrote: > > Tim Forcer wrote: > > Peter Alfke top-posted: > >> > >> Tim, you have to get over the idea of still > >> getting something from your old chip investment. > >> Xilinx FPGAs have become 100 times (!) cheaper, > >> have added functionality and better software > >> support since the days when you bought the > >> XC4013s. > > > > It's not the chip investment that's the *big* hangup, but the > > equipment investment. The chips were chosen deliberately in > > pin-grid-array package so we could replace as and when we wanted > > - including when/if they got blown up by misuse. Throw-away ICs > > we can live with - even at the price of PGA 4013s. Throw-away > > experimental units is another ball game. > > I suspect your best compromise may be to select the latest > and greatest - in Xilinx' case, this is currently Spartan-3 > - and have a tiny daughter board built with FPGA, regulator > and protection/interface chips. > > Of course you would still have to address the issue of > updating all the course material, as Jonathan discussed > a month or so ago. > > And you would have to repeat the exercise every five years > or so.Article: 63452
> Well, there's clear consensus that I'll be wanting RAM! I did look at > the burched.biz stuff, but the 2.5X price put me off. I don't know whether it is a consensus. It all depends on what you are going to be working on... If your goal is to design a microprocessor and port linux on it then you clearly need some RAM. On the other hand if you want to do a black jack game or a traffic light controller you won't need any RAM. > Seems like it should be easy enough to cobble up some RAM on one of > the digilent proto boards, yes? You will need to build a little board with a proper connector. This will probably cost you at least as much as the difference in the prices between the boards you looked at... Have you checked with Digilent? They might be offering expansion boards... /MikhailArticle: 63453
Robert Baumgartner wrote:
> In xilinx coregen generate a .coe file with the memory editor (found in the
> tool menu) with the correct depth
> an width for the memory you want. This will give you a .coe and a .mif file.
> Then generate your memory with
> coregen. Go to the last page of the configuration (for a dual port block
> memory for virtex pro it is page 4);
> there you select "load init file" , push on the button "load file" and fill
> in the name of the .coe file you
> generated before. Look in the generated VHDL file, the name of the .mif file
> in the VHDL file should match
> the file generated by the memory editor. For the Simulation put a .mif file
> with the correct content in your
> simulation directory. Your Simulator should read the .mif file via textio.
Or use an array of constants for
ease of simulation, and let
synthesis handle the rom details.
-- Mike Treseler
Article: 63454Chuck Levin <clevin1234@comcast.net> wrote: : I think that you should check out the QL5030 from QuickLogic. The device has : a fixed PCI target interface with a OTP programmable FPGA fabric. There is : no fee for the PCI core and full featured PCI testbench is provided for : simulation. The advantage of this is it would provide you with a single part : solution for you PCI and the rest of your logic. At the cost of a defect chip for every programming error. Be sure what you do. If cost are a issue, consider the Opencore PCI core. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de ======================================================= Free software means: Contribute nothing, expect nothing =======================================================Article: 63455
Martin Sauer <msauer@gmx.net> wrote: : Hello, : is it possible to start the Xilinx WebPack 6.1 with WINE under Linux : (SuSE 9.0)? If I start ise.exe I will get the message, that msvcp60.dll : isn't find. : Thank you for your answer. Did you install with wine? The program installer is responsible for deploying all needed dlls. You can try to fix that by hand, but that needs good resoning and some knowledge about wine debugging. Installing with wine often doesn't go flawless, perhaps rerun. Setting the wine-version to "win2k" for ISE is also a good idea, also "win98" seems to work again ( even on "real" win98), while 5.1/5.2 stalled with ersion "win98" in wine and in "real'. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de ======================================================= Free software means: Contribute nothing, expect nothing =======================================================Article: 63456
Hi All,
I'll open a webcase too, but I'm posting in hope of a super quick
answer! Here's my question:-
V2P has on-chip differential terminations for LVDS signals, e.g. LVDS_25_DT.
See answer #17244. However, although 3.3V banks can support LVDS receivers,
the terminated mode is not allowed. I quote:-
"Requirement to Turn on the On-chip Input Differential Termination
The VCCO of the I/O bank must be connected to 2.5V to provide 100 ohms of
effective termination.
NOTE: Starting ISE 6.1i, this requirement is implemented in the software. "
So, this sounds like it's just the new 6.1 software that stops you turning
on the termination in 3.3V banks. What happens if you use old software and
turn on the termination in a 3.3V bank? Why is it not allowed? Is it just
that the termination impedance is different? If so, what is it? It's not
hard to change the characteristic impedance of my traces to match a
different termination. Is the problem that it's not tested when the parts
are produced?
My problem is in banks 4 and 5 where a 3.3V 8 bit data bus configures
the device. These banks also contain some dedicated clock input pins that I
want to use internal terminations on.
Thanks for reading, Syms.
Article: 63457Chuck Levin <clevin1234@comcast.net> wrote: : Actually there is no cost for defect errors since they have a WebAsic : program that allows you to get programmed samples for free. ... : > At the cost of a defect chip for every programming error. : > : > Be sure what you do. : > : > If cost are a issue, consider the Opencore PCI core. : > So there is either the cost for a socket or a need to unsolder the chip witheach programming error. Also for each webasic you have to wait some time for delivery, not good for a normal delivery flow with program, run, fail, debug and reprogramm. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de ======================================================= Free software means: Contribute nothing, expect nothing =======================================================Article: 63458
Symon wrote:
My problem is in banks 4 and 5 where a 3.3V 8 bit data bus configures
> the device. These banks also contain some dedicated clock input pins that I
> want to use internal terminations on.
>
I would change the Vcco to 2.5 V on those banks. That cannot cause any
problems with the incoming 3.3-Vdata bus.
Peter Alfke
Article: 63459
Hi Peter,
OK, but the signals come from another board, they're ringy (is that a
word?) and I'm concerned about over/undershoot, I'd prefer to give myself
the safety margin of 3.3V VCCO.
Anyway, nice attempt to change the subject ;-) , I wonder what the deal
is with the on chip terminations?
thanks again, Syms.
"Peter Alfke" <peter@xilinx.com> wrote in message
news:3FBE86F3.D6AC5071@xilinx.com...
>
> Symon wrote:
> My problem is in banks 4 and 5 where a 3.3V 8 bit data bus configures
> > the device. These banks also contain some dedicated clock input pins
that I
> > want to use internal terminations on.
> >
> I would change the Vcco to 2.5 V on those banks. That cannot cause any
> problems with the incoming 3.3-Vdata bus.
> Peter Alfke
Article: 63460
Also, are you sure about this Peter? When I read the data sheet for LVCMOS25
inputs, the Vih max is VCCO + 0.4V, so putting 3.3V into a 2.5V bank is
against the rules. I would expect the catch diodes to conduct.
Where am I going wrong?
thanks, Syms.
"Peter Alfke" <peter@xilinx.com> wrote in message
news:3FBE86F3.D6AC5071@xilinx.com...
>
> Symon wrote:
> My problem is in banks 4 and 5 where a 3.3V 8 bit data bus configures
> > the device. These banks also contain some dedicated clock input pins
that I
> > want to use internal terminations on.
> >
> I would change the Vcco to 2.5 V on those banks. That cannot cause any
> problems with the incoming 3.3-Vdata bus.
> Peter Alfke
Article: 63461"MM" <mbmsv@yahoo.com> wrote in message news:<bplpmb$1pjjup$1@ID-204311.news.uni-berlin.de>... > > Well, there's clear consensus that I'll be wanting RAM! I did look at > > the burched.biz stuff, but the 2.5X price put me off. > > I don't know whether it is a consensus. It all depends on what you are going > to be working on... If your goal is to design a microprocessor and port > linux on it then you clearly need some RAM. On the other hand if you want to > do a black jack game or a traffic light controller you won't need any RAM. Just looking for a system to learn about FPGAs in my spare time. In all honesty I probably will never use more than a few percent of the device. Plenty of blinking lights is clearly the most important feature. :) > > > Seems like it should be easy enough to cobble up some RAM on one of > > the digilent proto boards, yes? > > You will need to build a little board with a proper connector. This will > probably cost you at least as much as the difference in the prices between > the boards you looked at... Have you checked with Digilent? They might be > offering expansion boards... Well, I can buy a couple of 128Kx8 SRAMs for 12 bucks, and another $12 for a proto board that's designed to plug into the FPGA board. For a little effort I still save $250. I also notice that the Spartan device comes with 56k bits of block RAM. I gather that I could use that for small RAM needs.Article: 63462
Symon, V2P does not support 3.3V Vcco powered LVDS (at least, that is what the data sheet says). Austin Symon wrote: > Hi All, > I'll open a webcase too, but I'm posting in hope of a super quick > answer! Here's my question:- > > V2P has on-chip differential terminations for LVDS signals, e.g. LVDS_25_DT. > See answer #17244. However, although 3.3V banks can support LVDS receivers, > the terminated mode is not allowed. I quote:- > > "Requirement to Turn on the On-chip Input Differential Termination > The VCCO of the I/O bank must be connected to 2.5V to provide 100 ohms of > effective termination. > NOTE: Starting ISE 6.1i, this requirement is implemented in the software. " > > So, this sounds like it's just the new 6.1 software that stops you turning > on the termination in 3.3V banks. What happens if you use old software and > turn on the termination in a 3.3V bank? Why is it not allowed? Is it just > that the termination impedance is different? If so, what is it? It's not > hard to change the characteristic impedance of my traces to match a > different termination. Is the problem that it's not tested when the parts > are produced? > My problem is in banks 4 and 5 where a 3.3V 8 bit data bus configures > the device. These banks also contain some dedicated clock input pins that I > want to use internal terminations on. > > Thanks for reading, Syms.Article: 63463
"Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message
news:3FBE981D.8DD51B38@xilinx.com...
> Symon,
>
> V2P does not support 3.3V Vcco powered LVDS (at least, that is what the
data
> sheet says).
>
> Austin
>
> Symon wrote:
>
> > Hi All,
> > I'll open a webcase too, but I'm posting in hope of a super quick
> > answer! Here's my question:-
> >
> > V2P has on-chip differential terminations for LVDS signals, e.g.
LVDS_25_DT.
> > See answer #17244. However, although 3.3V banks can support LVDS
receivers,
> > the terminated mode is not allowed. I quote:-
> >
> > "Requirement to Turn on the On-chip Input Differential Termination
> > The VCCO of the I/O bank must be connected to 2.5V to provide 100 ohms
of
> > effective termination.
> > NOTE: Starting ISE 6.1i, this requirement is implemented in the
software. "
> >
> > So, this sounds like it's just the new 6.1 software that stops you
turning
> > on the termination in 3.3V banks. What happens if you use old software
and
> > turn on the termination in a 3.3V bank? Why is it not allowed? Is it
just
> > that the termination impedance is different? If so, what is it? It's not
> > hard to change the characteristic impedance of my traces to match a
> > different termination. Is the problem that it's not tested when the
parts
> > are produced?
> > My problem is in banks 4 and 5 where a 3.3V 8 bit data bus
configures
> > the device. These banks also contain some dedicated clock input pins
that I
> > want to use internal terminations on.
> >
> > Thanks for reading, Syms.
>
Austin,
(With tongue in cheek) I think you'll find that
"The differential input buffers are powered by VCCAUX and are not
VCCO-dependent. For this reason, you can put LVDS_25 and LVPECL_25 input
buffers in a 3.3V bank; the software does not report errors and the device
is not damaged. In this case, the input specifications are as specified for
LVDS_25 and LVPECL_25."
Or at least that's the gospel according to answer 16830!!
So, I'm allowed LVDS inputs on a 3.3V bank, so why can't I terminate
them on-chip?
thanks, Syms.
Article: 63464Hiya, I heard it has been discontinued due to being too inaccurate - in a conservative way, though. No idea when or whether they'll be posting a new one. I suggest asking your local FAE whether he still has a copy. Best regards, BenArticle: 63465
erojr wrote: > I have transported a design from Altera APEX to STRATIX. The previous > design´s Lookup Tables (LUTs) that were in ¨lpm_rom¨ modules have been > transported to ¨altsynchram¨ modules. Now QuartusII3.0 sends an error > message: > > > Error: Groups cannot be assigned to nodes Doesn't sound like a familiar message. Can you post some code that instantiates the altsyncram? -- BenArticle: 63466
Actually there is no cost for defect errors since they have a WebAsic program that allows you to get programmed samples for free. "Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:bpltv5$kp4$1@news.tu-darmstadt.de... > Chuck Levin <clevin1234@comcast.net> wrote: > : I think that you should check out the QL5030 from QuickLogic. The device has > : a fixed PCI target interface with a OTP programmable FPGA fabric. There is > : no fee for the PCI core and full featured PCI testbench is provided for > : simulation. The advantage of this is it would provide you with a single part > : solution for you PCI and the rest of your logic. > > > At the cost of a defect chip for every programming error. > > Be sure what you do. > > If cost are a issue, consider the Opencore PCI core. > > Bye > > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > ======================================================= > > Free software means: Contribute nothing, expect nothing > > =======================================================Article: 63467
Symon, Hmmmm. I was thinking of both input and output. You are right. Perhaps the software thinks like I do? Austin Symon wrote: > "Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message > news:3FBE981D.8DD51B38@xilinx.com... > > Symon, > > > > V2P does not support 3.3V Vcco powered LVDS (at least, that is what the > data > > sheet says). > > > > Austin > > > > Symon wrote: > > > > > Hi All, > > > I'll open a webcase too, but I'm posting in hope of a super quick > > > answer! Here's my question:- > > > > > > V2P has on-chip differential terminations for LVDS signals, e.g. > LVDS_25_DT. > > > See answer #17244. However, although 3.3V banks can support LVDS > receivers, > > > the terminated mode is not allowed. I quote:- > > > > > > "Requirement to Turn on the On-chip Input Differential Termination > > > The VCCO of the I/O bank must be connected to 2.5V to provide 100 ohms > of > > > effective termination. > > > NOTE: Starting ISE 6.1i, this requirement is implemented in the > software. " > > > > > > So, this sounds like it's just the new 6.1 software that stops you > turning > > > on the termination in 3.3V banks. What happens if you use old software > and > > > turn on the termination in a 3.3V bank? Why is it not allowed? Is it > just > > > that the termination impedance is different? If so, what is it? It's not > > > hard to change the characteristic impedance of my traces to match a > > > different termination. Is the problem that it's not tested when the > parts > > > are produced? > > > My problem is in banks 4 and 5 where a 3.3V 8 bit data bus > configures > > > the device. These banks also contain some dedicated clock input pins > that I > > > want to use internal terminations on. > > > > > > Thanks for reading, Syms. > > > > Austin, > (With tongue in cheek) I think you'll find that > "The differential input buffers are powered by VCCAUX and are not > VCCO-dependent. For this reason, you can put LVDS_25 and LVPECL_25 input > buffers in a 3.3V bank; the software does not report errors and the device > is not damaged. In this case, the input specifications are as specified for > LVDS_25 and LVPECL_25." > Or at least that's the gospel according to answer 16830!! > > So, I'm allowed LVDS inputs on a 3.3V bank, so why can't I terminate > them on-chip? > > thanks, Syms.Article: 63468
Mike, > Just looking for a system to learn about FPGAs in my spare time. In > all honesty I probably will never use more than a few percent of the > device. Plenty of blinking lights is clearly the most important > feature. :) Well, then it sounds like this board has all that you will need... > > You will need to build a little board with a proper connector. This will > > probably cost you at least as much as the difference in the prices between > > the boards you looked at... Have you checked with Digilent? They might be > > offering expansion boards... > > Well, I can buy a couple of 128Kx8 SRAMs for 12 bucks, and another $12 > for a proto board that's designed to plug into the FPGA board. For a > little effort I still save $250. The problem with this approach is signal integrity.... It will work in principle but it might not work at the board's full speed (at whatever the clock rate is there). However, it doesn't sound as you will need extra RAM anytime soon anyway... > I also notice that the Spartan device comes with 56k bits of block > RAM. I gather that I could use that for small RAM needs. Yes, sure! That's what it is there for! /MikhailArticle: 63469
Can anybody tell me how can I use .MIF to generated a rom using xilinx core generator. I dont know why it is taking only .coe file and not .mif file.Article: 63470
The WebASIC turn around is usually 24 Hours. It is important to remember that the PCI side of the design will work from the start and it sounds like the rest of the design is somewhat trivial. The last design I did was for a PCI to 8051 bridge and it only required 2 spins for completion. Also remember that a little added time with the simulation saves consider effort for any development cycle. "Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:bplvc3$l3k$1@news.tu-darmstadt.de... > Chuck Levin <clevin1234@comcast.net> wrote: > : Actually there is no cost for defect errors since they have a WebAsic > : program that allows you to get programmed samples for free. > > ... > : > At the cost of a defect chip for every programming error. > : > > : > Be sure what you do. > : > > : > If cost are a issue, consider the Opencore PCI core. > : > > > So there is either the cost for a socket or a need to unsolder the chip > witheach programming error. Also for each webasic you have to wait some time > for delivery, not good for a normal delivery flow with program, run, fail, > debug and reprogramm. > > Bye > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > ======================================================= > > Free software means: Contribute nothing, expect nothing > > =======================================================Article: 63471
On Fri, 21 Nov 2003 14:25:04 -0800, "Symon" <symon_brewer@hotmail.com> wrote: >Hi Peter, > OK, but the signals come from another board, they're ringy (is that a >word?) and I'm concerned about over/undershoot, I'd prefer to give myself >the safety margin of 3.3V VCCO. I believe you have *less* safety margin with the 3.3V VCCO. The abs max voltages on the pin are Gnd + 3.6V to VCCO - 3.6V. With a 3.3V VCCO, you can exceed the abs max voltage (with your "ringy" signals) before the catch diode conducts. With a 2.5V VCCO, the diodes will stop you from exceeding the voltage rating, but you may exceed the current rating when driving from a 3.3V device with stiff outputs. A small value series resistor fixes that problem. (You probably need a series resistor for signal integrity reasons anyway.) On my current board I use all 2.5V signalling on the FPGA (not including the LVDS stuff). There was a legacy 3.3V level processor interface, and I used a number of 74ALVC164245 to handle the level translation. Regards, Allan.Article: 63472
On 18 Nov 2003 16:11:26 -0800, komara5@comcast.net (Kevin O'Mara) wrote: >I am attempting to use this XILINX software with this board and chip. >In order to test it, I create a simple design that incorporates an >AND2 gate, two input buffers, and one output buffer all of which (the >input and output buffers) are connected to IPADs. The IPADs are >assigned pin numbers on the Schematic with the parameters LOC=Pxx, >where xx is 27, 28, and 69. These correspond to SW1, SW2, and LD1. > >The design implements correctly, and the bit file is generated >successfully. When I transfer the design to the board, NOTHING >HAPPENS! Does the Done pin go high? Try something even simpler: just connect an output from the OSC4 block to an output. Philip Philip Freidin FliptronicsArticle: 63473
Are there any reference designs for video frame memory control logic to work with Philips SAA7111 decoder? email to fwang11@pub3.fz.fj.cn Thanks, Wang, FengArticle: 63474
Hi everybody, I was wondering if anyone knew where I could get my hands on a cheap fpga development board... I'm a university student at Carleton U. in Ottawa so I can't afford anything to fancy (tuition fees drained my pocket). Anyways... if anyone can direct me to someone or some merchant I would greatly appreciate it. Thanks Nadeem
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z